From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit ae4f3443209ab154b48b706a146e5f557ab147cb:

  Merge tag 'qtest-20260819-pull-request' of https://gitlab.com/farosas/qemu into staging (2026-08-19 08:21:57 -0700)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260820-1

for you to fetch changes up to b07529241a24a4417366f378755aa978783e49f9:

  target/riscv: Restore register dump zero padding (2026-08-20 13:32:46 +1000)

----------------------------------------------------------------
RISC-V PR

* Add K230 DDR controller and PHY models
* Add optional UART1 to virt machine
* Add gsdma and decomp_gzip to K230
* Synchronize KVM privilege mode
* Preserve KVM MP state across migration
* Fix PC sync in trans_sspopchk for CFI exception handling
* Use SXL instead of MXL for read_sstatus
* Fix memory leak in riscv_trigger_unrealize()
* Support the true Zicclsm extension
* Always send MRIF notice MSI
* Do not count ECALL in minstret
* Fix seed CSR sign extension
* Fix immediate decoding and extraction
* Fix U-bit check to apply only to leaf S/VS-stage PTEs for IOMMU
* Preserve requested perm in spa_fetch() for IOMMU
* Allow menvcfg/henvcfg LPE and SSE bits on RV32
* Reorganize the disassembler
* Dix reserved/illegal instruction encodings
* Remove trace output from k230 watchdog test
* Restore register dump zero padding

----------------------------------------------------------------
A-Shehab (1):
      target/riscv: allow menvcfg/henvcfg LPE and SSE bits on RV32

Abhigyan Kumar (1):
      target/riscv: use SXL instead of MXL for read_sstatus

Andrew Jones (2):
      hw/riscv/riscv-iommu: fix U-bit check to apply only to leaf S/VS-stage PTEs
      hw/riscv/riscv-iommu: preserve requested perm in spa_fetch()

Chao Liu (1):
      tests/qtest: remove trace output from k230 watchdog test

Flavien Solt (3):
      hw/misc/iommu-testdev: support PCI MSI test writes
      hw/riscv/riscv-iommu.c: always send MRIF notice MSI
      tests/qtest: add RISC-V IOMMU MRIF notice tests

Frank Chang (7):
      target/riscv: Add Zicclsm CPU option and enable it for the eligible CPUs
      hw/riscv: sifive_u: Align ROM reset vector data
      target/riscv: Support raising misaligned exceptions for scalar loads/stores
      target/riscv: Support raising misaligned exceptions for floating-point loads/stores
      target/riscv: Support raising misaligned exceptions for vector loads/stores
      target/riscv: Expose Zicclsm as a CPU property and update RVA22U64 profile
      tests/tcg/riscv64: Add test for Zicclsm

Ivan Efremov (2):
      target/riscv: Fix seed CSR sign extension
      tests/qtest: Add seed CSR zero extension test

Joel Stanley (1):
      target/riscv: Restore register dump zero padding

Junze Cao (3):
      hw/misc: Add K230 DDR controller and PHY models
      hw/riscv: Connect K230 DDR controller and PHY models
      tests/qtest: Add K230 DDR controller tests

Max Chou (1):
      target/riscv: Fix PC sync in trans_sspopchk for CFI exception handling

Richard Henderson (52):
      disas/riscv: Move operand extractors earlier in file
      disas/riscv: Reduce rv_insn to uint32_t
      disas/riscv: Tidy dec initialization in disasm_inst
      disas/riscv: Pass rv_opcode_data pointer to decode_inst_operands
      disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_decompress
      disas/riscv: Pass rv_opcode_data pointer to/from decode_inst_lift_pseudo
      disas/riscv: Pass rv_opcode_data pointer to format_inst
      disas/riscv: Tidy disasm_inst main loop
      disas/riscv: Set dec->opcode_data in decode function
      disas/riscv: Drop explicit zero of rv_opcode_data fields
      disas/riscv: Drop useless const in structures
      disas/riscv: Drop codec from rv_decode
      disas/riscv: Handle c.addi4spn imm != 0 during decode
      disas/riscv: Simplify c.addi
      disas/riscv: Handle c.lui imm != 0 during decode
      disas/riscv: Handle c.{srli,srai} imm during decode
      disas/riscv: Handle c.slli imm != 0 during decode
      disas/riscv: Do not recognize c.{addw, subw} with rv32
      disas/riscv: Remove rvcd_imm_nz
      disas/riscv: Unify decomp_rv{32,64,128}
      disas/riscv: Drop always true branch pseudos
      disas/riscv: Handle aliases of csrrw during decode
      disas/riscv: Handle aliases of csrrs during decode
      disas/riscv: Handle aliases of csrrwi during decode
      disas/riscv: Break pseudo loop for jal and jalr
      disas/riscv: Allow decode_inst_lift_pseudo to loop
      disas/riscv: Handle decompression via decode_inst_lift_pseudo
      disas/riscv: Drop format from DECOMP insns
      disas/riscv: Tidy rv_comp_data terminators
      disas/riscv: Chain "ret" pseudo off "jr" pseudo
      disas/riscv: Chain "nop" pseudo off "mv" pseudo
      disas/riscv: Use rv_codec_illegal for pseudos
      disas/riscv: Simplify some insn decompressions
      disas/riscv: Store op pointer in rv_comp_data
      disas/riscv: Return rv_opcode_data pointer from decoders
      disas/riscv: Skip post-processing of illegal insns
      disas/riscv: Reject all of OP-32 and OP-IMM-32 for RV32
      disas/riscv: Fix rv32 encoding of zext.h
      disas/riscv: Fix isa decoding of rev8
      disas/riscv: Fix typo in th.lbib format
      disas/riscv: Split ventana_opcode_data
      disas/riscv: Split xlrbr_opcode_data
      disas/riscv: Split xthead_opcode_data
      disas/riscv: Move rv_op_illegal to riscv.c
      disas/riscv: Split out riscv-op.c.inc
      disas/riscv: Merge all mop.r.n to one pattern
      disas/riscv: Merge all mop.rr.n to one pattern
      disas/riscv: Merge all c.mop.n to one pattern
      disas/riscv: Tidy decode of c.mop.n
      disas/riscv: Tidy decode of mop.r.n and mop.rr.n
      disas/riscv: Split rvi_opcode_data
      disas/riscv: Sort riscv-op.c.inc

TANG Tiancheng (5):
      disas/riscv: Fix th.srri decoding
      disas/riscv: Fix 6-bit immediate extraction
      disas/riscv: Use signed type for vector immediates
      disas/riscv: Decode unsigned vector immediates as unsigned
      disas/riscv: Use extract helpers for operand fields

Tao Ding (6):
      hw/dma: add K230 gsdma
      hw/riscv: k230: add gsdma in K230 board
      tests/qtest: add test for K230 gsdma
      hw/riscv: k230: add decomp gzip in K230 board
      tests/qtest: add test for K230 decomp gzip
      hw/riscv: k230: add a noc stub region in K230 board

Xie Bo (2):
      target/riscv/kvm: Synchronize privilege mode
      target/riscv/kvm: Preserve MP state across migration

Yanfeng Liu (1):
      riscv/virt: Add optional UART1

Zeng Chi (1):
      target/riscv: Fix memory leak in riscv_trigger_unrealize()

Zephyr Li (1):
      target/riscv: do not count ECALL in minstret

wangyang (3):
      target/riscv: honor zicbo* envcfg gating in linux-user mode
      target/riscv: reject FMV.X.W/FMV.W.X under Zfinx
      target/riscv: enforce even register constraints for Zdinx fcvt pairs

 MAINTAINERS                                       |    9 +
 docs/system/riscv/k230.rst                        |    6 +
 docs/system/riscv/virt.rst                        |    5 +-
 disas/riscv-xlrbr.h                               |    4 +-
 disas/riscv-xthead.h                              |   24 +-
 disas/riscv-xventana.h                            |    4 +-
 disas/riscv.h                                     |   47 +-
 include/hw/dma/k230_gsdma.h                       |  130 +
 include/hw/misc/iommu-testdev.h                   |    1 +
 include/hw/misc/k230_ddr.h                        |   59 +
 include/hw/misc/k230_decomp_gzip.h                |   92 +
 include/hw/riscv/k230.h                           |    9 +
 include/hw/riscv/virt.h                           |    3 +
 target/riscv/cpu.h                                |    4 +
 target/riscv/cpu_bits.h                           |   10 +-
 target/riscv/kvm/kvm_riscv.h                      |    2 +-
 target/riscv/tcg/pmu.h                            |    1 +
 target/riscv/cpu_cfg_fields.h.inc                 |    2 +
 disas/riscv-xlrbr.c                               |   57 +-
 disas/riscv-xthead.c                              |  509 +-
 disas/riscv-xventana.c                            |   23 +-
 disas/riscv.c                                     | 5305 +++++++--------------
 hw/dma/k230_gsdma.c                               |  551 +++
 hw/misc/iommu-testdev.c                           |   14 +-
 hw/misc/k230_ddr.c                                |  556 +++
 hw/misc/k230_decomp_gzip.c                        |  511 ++
 hw/riscv/k230.c                                   |   57 +-
 hw/riscv/riscv-iommu.c                            |   77 +-
 hw/riscv/sifive_u.c                               |   11 +-
 hw/riscv/virt-acpi-build.c                        |   12 +-
 hw/riscv/virt.c                                   |   40 +-
 target/riscv/cpu.c                                |   27 +-
 target/riscv/kvm/kvm-cpu.c                        |   62 +-
 target/riscv/machine.c                            |   49 +-
 target/riscv/tcg/csr.c                            |   54 +-
 target/riscv/tcg/debug.c                          |    2 +-
 target/riscv/tcg/op_helper.c                      |   17 +-
 target/riscv/tcg/pmu.c                            |   44 +-
 target/riscv/tcg/vector_helper.c                  |   65 +-
 tests/qtest/iommu-riscv-test.c                    |  102 +
 tests/qtest/k230-ddr-test.c                       |  226 +
 tests/qtest/k230-decomp-gzip-test.c               |  200 +
 tests/qtest/k230-gsdma-test.c                     |  201 +
 tests/qtest/k230-wdt-test.c                       |    2 +-
 tests/qtest/riscv-csr-test.c                      |   26 +
 disas/riscv-op.c.inc                              |  913 ++++
 disas/riscv-xlrbr-op.c.inc                        |    8 +
 disas/riscv-xthead-op.c.inc                       |  125 +
 disas/riscv-xventana-op.c.inc                     |    2 +
 target/riscv/tcg/insn_trans/trans_rvd.c.inc       |    6 +
 target/riscv/tcg/insn_trans/trans_rvf.c.inc       |   12 +-
 target/riscv/tcg/insn_trans/trans_rvi.c.inc       |    6 +
 target/riscv/tcg/insn_trans/trans_rvv.c.inc       |   18 +-
 target/riscv/tcg/insn_trans/trans_rvzfh.c.inc     |    8 +
 target/riscv/tcg/insn_trans/trans_rvzicfiss.c.inc |    2 +-
 hw/dma/Kconfig                                    |    3 +
 hw/dma/meson.build                                |    1 +
 hw/dma/trace-events                               |    6 +
 hw/misc/Kconfig                                   |    3 +
 hw/misc/meson.build                               |    2 +
 hw/misc/trace-events                              |    4 +
 hw/riscv/Kconfig                                  |    2 +
 tests/qtest/meson.build                           |    3 +-
 tests/tcg/riscv64/Makefile.softmmu-target         |   26 +
 tests/tcg/riscv64/test-minstret-ecall.S           |   55 +
 tests/tcg/riscv64/test-zicclsm.S                  |  368 ++
 66 files changed, 6485 insertions(+), 4300 deletions(-)
 create mode 100644 include/hw/dma/k230_gsdma.h
 create mode 100644 include/hw/misc/k230_ddr.h
 create mode 100644 include/hw/misc/k230_decomp_gzip.h
 create mode 100644 hw/dma/k230_gsdma.c
 create mode 100644 hw/misc/k230_ddr.c
 create mode 100644 hw/misc/k230_decomp_gzip.c
 create mode 100644 tests/qtest/k230-ddr-test.c
 create mode 100644 tests/qtest/k230-decomp-gzip-test.c
 create mode 100644 tests/qtest/k230-gsdma-test.c
 create mode 100644 disas/riscv-op.c.inc
 create mode 100644 disas/riscv-xlrbr-op.c.inc
 create mode 100644 disas/riscv-xthead-op.c.inc
 create mode 100644 disas/riscv-xventana-op.c.inc
 create mode 100644 tests/tcg/riscv64/test-minstret-ecall.S
 create mode 100644 tests/tcg/riscv64/test-zicclsm.S