SH-4 manual for reference:
https://0x04.net/~mwk/doc/sh/e602156_sh4.pdf

There is an issue with the current TCG code generation for `fmov` 
instructions. When the operands are double-register to memory 
(or vice versa), the generated code treats it as an f64 load/store. 
However, as specified in the manual, this operation is only supported 
when the PR flag is 0 (single-precision) and the SZ flag is 1 
(pair transfer size). The correct semantics then are to read/write a 
pair of f32 values, rather than a single f64 value. This is 
semantically different in little-endian mode, as the word-ordering 
gets reversed writing two f32s versus one f64.

This PR adds TCG tests for all permutations of `fmov` operands,
and fixes the issues above by ensuring the PR and SZ flags are correct 
and properly handling an f32 pair instead of a single f64.

Signed-off-by: Randy Schifflin <randy.schifflin@gmail.com>
---
Randy Schifflin (2):
      target/sh4: add tcg tests for fmov instructions
      target/sh4: fixup tcg generation for sh4 `fmov` instructions.

 target/sh4/translate.c        |  82 ++++---
 tests/tcg/sh4/Makefile.target |   3 +
 tests/tcg/sh4/test-fpu-fmov.c | 518 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 568 insertions(+), 35 deletions(-)
---
base-commit: e1705a25aff35635c360bbaba4c2731d019a422a
change-id: 20260729-sh4-fix-fmov-instructions-b4-7610a3a19906

Best regards,
-- 
Randy Schifflin <randy.schifflin@gmail.com>