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Wed, 29 Jul 2026 13:55:45 -0700 (PDT) From: Randy Schifflin Date: Wed, 29 Jul 2026 13:55:07 -0700 Subject: [PATCH 1/2] target/sh4: add tcg tests for fmov instructions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260729-sh4-fix-fmov-instructions-b4-v1-1-65cc9679025a@gmail.com> References: <20260729-sh4-fix-fmov-instructions-b4-v1-0-65cc9679025a@gmail.com> In-Reply-To: <20260729-sh4-fix-fmov-instructions-b4-v1-0-65cc9679025a@gmail.com> To: qemu-devel@nongnu.org Cc: Yoshinori Sato , qemu-trivial@nongnu.org, Randy Schifflin X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openssh-sha256; t=1785358542; l=14000; i=randy.schifflin@gmail.com; s=id_rsa; h=from:subject:message-id; bh=BSwpivmp4jY+2Pjwh4iaeavOawEQ5IaV/K9rAJljvF0=; b=U1NIU0lHAAAAAQAAAZcAAAAHc3NoLXJzYQAAAAMBAAEAAAGBALXHj1ozDvr3TmWcPoueK1kIy Q3yQ7HL5bbiu8J+P0QBzcchmw5nwN0avQmreXhYuMhz40g0dhCJPnJqNHg1FBflQPz2cgY7Utm3 9lQrK/CQqWsjRwXMinMR7LrmtMFp9+up7MzdXoxmTLgPsKJ/dQmx0rUHx++mUSl8zl7lHO50YVD hsw1RHrkrXlxnUjRi+jtjgErRHvoRwSZpKc44yR62wV8chkTMnHtrn8hgL0Hh+jhHteNn4JTQB/ wme8MghhliXR5oh9xirpeLlS9S4TBY3Vdk6ccgvncSS4uF/y2ZAAV5sNiLZ97OFkBhIQ0bXhVx9 w1LPMkho650Iu9da5/0koNheHS2KAVC2FdPTyaxvqeFAsAB8fCprfh4lpShdcVpyChdd2KXFS53 s9MAUQmZjG0pQvS/dqGCCDWqo7cY3J3VTMXwVtdzYkgZt5eMajL7z8VljXQ08ZgAStdizC/rHNg wy+fIL+6kgxvL/NhJwoiAWhC4D+xQY7SXjJGTvwAAAAZwYXRhdHQAAAAAAAAABnNoYTUxMgAAAZ QAAAAMcnNhLXNoYTItNTEyAAABgJytY41ZYpWIGAD/MBT0QESTNx3PCJJ7TTzD56VVN25IqUfyo +Avx+OpqXc23i8/5MTOVd+mRkAy8RaI7xMKGRTi0exJUqTZBY737Hy9VlpLcQDN/ddjSNki0UzG BRj5pG8MJXuJtgSGJ6jaWcsWqlnaRbFtX6/0aFAge2Jl4mPwps+C4Ji1hPtDn6KGuXMJQACzkzV oyS+W9YY+uJthXK/YvDMawpWHp8wxkOFi7jreAfnRND7klyja3KEJv1IuujsyPUtfKEcvtlZ1EY Hy1m1MzdkWA5/k7PiiNl1fmfEdKHvAcgYnG8ok1/Ot96ZJ8y3uoTR2RZEJpwFLZDUmggIBnAGAp f8AHE2OvUQ+qT+WiwxsCo6w0fKBkJu8mwEDAIApuusMBhMK0Xu+xbnqOidA0laW/NVRgIe6RVZa yVT0iJhzxHZbxXBIx/RozvQMH7dnhRIAWT/Gr5d7EqbO5quUdC/I5uiyB4ma6+txdsH6M8krdix SgZnwiwo6V8jzgA== X-Developer-Key: i=randy.schifflin@gmail.com; a=openssh; fpr=SHA256:7gww1tlDoVPb7symWGdTNhRWcHyTORA23OcjS8eyd8Y Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=randy.schifflin@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785358605007158500 Add tests for the TCG generation of the sh4-specific `fmov` instructions. Covers register/register and register/memory in each direction, for single and double precision fp registers, and with direct and indirect memory addressing. Signed-off-by: Randy Schifflin Reviewed-by: Yoshinori Sato --- tests/tcg/sh4/Makefile.target | 3 + tests/tcg/sh4/test-fpu-fmov.c | 518 ++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 521 insertions(+) diff --git a/tests/tcg/sh4/Makefile.target b/tests/tcg/sh4/Makefile.target index b7a8737be0..82f4898f90 100644 --- a/tests/tcg/sh4/Makefile.target +++ b/tests/tcg/sh4/Makefile.target @@ -16,3 +16,6 @@ TESTS +=3D test-addv =20 test-subv: CFLAGS +=3D -O -g TESTS +=3D test-subv + +test-fpu-fmov: CFLAGS +=3D -O -g +TESTS +=3D test-fpu-fmov diff --git a/tests/tcg/sh4/test-fpu-fmov.c b/tests/tcg/sh4/test-fpu-fmov.c new file mode 100644 index 0000000000..90e51923ed --- /dev/null +++ b/tests/tcg/sh4/test-fpu-fmov.c @@ -0,0 +1,518 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +#define ARR_SIZE 16 +static const float in_arr[ARR_SIZE] =3D { + 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, + 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0 +}; + +static float out_arr[ARR_SIZE] =3D { + 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, + 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 +}; + +static const unsigned long FPSCR_PR_BIT =3D 1UL << 19; +static void single_precision_mode(void) +{ + unsigned long fpscr; + asm volatile("sts fpscr, %0" : "=3Dr" (fpscr)); + fpscr &=3D ~FPSCR_PR_BIT; + asm volatile("lds %0, fpscr" : : "r" (fpscr)); +} + +static void double_precision_mode(void) +{ + unsigned long fpscr; + asm volatile("sts fpscr, %0" : "=3Dr" (fpscr)); + fpscr |=3D FPSCR_PR_BIT; + asm volatile("lds %0, fpscr" : : "r" (fpscr)); +} + +static void fill_arr(float *arr, float n) +{ + for (int i =3D 0; i < ARR_SIZE; i++) { + arr[i] =3D n; + } +} + +/* uses fmov frm,frn instruction */ +static int test_fmov_freg_freg(void) +{ + int pass =3D true; + + register float out asm ("fr0") =3D 0.0; + asm volatile( + "fldi1 fr1\n" + "fmov fr1,%0\n" + : "=3Df" (out) + ); + + if (out !=3D 1.0) { + fprintf( + stderr, + "fmov freg,freg failed. Expected %f, got %f\n", 1.0, out + ); + pass =3D false; + } + + return pass; +} + +/* uses fmov frm,@rn instruction */ +static int test_fmov_freg_addr(float *out) +{ + int pass =3D true; + fill_arr(out, 0); + + register float *out_addr =3D out; + asm volatile( + "fldi1 fr0\n" + "fmov.s fr0,@%0\n" + : : "r" (out_addr) : "memory" + ); + + if (out[0] !=3D 1.0) { + fprintf( + stderr, + "fmov freg,addr failed. Expected %f, got %f\n", 1.0, out[0] + ); + pass =3D false; + } + + fill_arr(out, 0); + return pass; +} + +/* uses fmov @rm,frn instruction */ +static int test_fmov_addr_freg(const float *in) +{ + int pass =3D true; + const register float *in_addr =3D in; + register float out =3D 0.0; + asm volatile( + "fmov.s @%1,%0\n" + : "=3Df" (out) : "r" (in_addr) + ); + + if (out !=3D 1.0) { + fprintf( + stderr, + "fmov addr,freg failed. Expected %f, got %f\n", 1.0, out + ); + pass =3D false; + } + + return pass; +} + +/* uses fmov frm,@(r0,rn) instruction */ +static int test_fmov_freg_indirect_addr(float *out) +{ + int pass =3D true; + fill_arr(out, 0.0); + + register float *out_addr =3D out; + asm volatile( + "mov #4,r0\n" + "fldi1 fr0\n" + "fmov.s fr0, @(r0, %0)\n" + : : "r" (out_addr) : "memory" + ); + + if (out[1] !=3D 1.0) { + fprintf( + stderr, + "fmov freg,indirect_addr failed. Expected %f, got %f\n", 1.0, = out[1] + ); + pass =3D false; + } + + fill_arr(out, 0.0); + return pass; +} + +/* uses fmov @(r0,rm),frn instruction */ +static int test_fmov_indirect_addr_freg(const float *in) +{ + int pass =3D true; + + const register float *in_addr asm ("r1") =3D in; + register float out asm ("fr0") =3D 0.0; + asm volatile( + "mov #4,r0\n" + "fmov.s @(r0, %1), %0\n" + : "=3Df" (out) : "r" (in_addr) : "memory" + ); + + if (out !=3D in[1]) { + fprintf( + stderr, + "fmov indirect_addr,freg failed. Expected %f, got %f\n", in[1]= , out + ); + pass =3D false; + } + + return pass; +} + +/* uses fmov drm,drn instruction */ +static int test_fmov_dreg_dreg(void) +{ + int pass =3D true; + double_precision_mode(); + + register double out asm ("dr0") =3D 0.0; + asm volatile( + "mov #42,r0\n" + "lds r0,fpul\n" + "float fpul,dr2\n" + "fmov dr2,%0\n" + : "=3Df" (out) + ); + + if (out !=3D 42.0) { + fprintf( + stderr, + "fmov dreg,dreg failed. Expected %f, got %f\n", 42.0, out + ); + pass =3D false; + } + + single_precision_mode(); + return pass; +} + +/* uses fmov drm,@rn instruction */ +static int test_fmov_dreg_addr(float *out) +{ + int pass =3D true; + fill_arr(out, -1.0); + + register float *out_addr =3D out; + asm volatile( + "fldi0 fr0\n" + "fldi1 fr1\n" + "fschg\n" /* Set fast pairs on */ + "fmov dr0, @%0\n" + "fschg\n" /* Set fast pairs off */ + : : "r" (out_addr) : "memory" + ); + + if (out[0] !=3D 0.0) { + fprintf( + stderr, + "fmov dreg,addr failed. " \ + "Expected element 0 to be %f, got %f\n", 0.0, out[0] + ); + pass =3D false; + } + if (out[1] !=3D 1.0) { + fprintf( + stderr, + "fmov dreg,addr failed. " \ + "Expected element 1 to be %f, got %f\n", 1.0, out[1] + ); + pass =3D false; + } + + fill_arr(out, 0.0); + return pass; +} + +/* uses fmov @rm,drn instruction */ +static int test_fmov_addr_dreg(const float *in) +{ + int pass =3D true; + + const register float *in_addr asm ("r1") =3D in; + register float write_out_0 asm ("fr0") =3D 0.0; + register float write_out_1 asm ("fr1") =3D 0.0; + + asm volatile( + "fschg\n" /* Set fast pairs on */ + "fmov @%2,dr0\n" + "fschg\n" /* Set fast pairs off */ + : "=3Df" (write_out_0), "=3Df" (write_out_1) : "r" (in_addr) : "me= mory" + ); + + if (write_out_0 !=3D in[0]) { + fprintf( + stderr, + "fmov addr,dreg failed. " \ + "Expected element 0 to be %f, got %f\n", in[0], write_out_0 + ); + pass =3D false; + } + if (write_out_1 !=3D in[1]) { + fprintf( + stderr, + "fmov addr,dreg failed. " \ + "Expected element 1 to be %f, got %f\n", in[1], write_out_1 + ); + pass =3D false; + } + + return pass; +} + +/* uses fmov drm,@(r0,rn) instruction */ +static int test_fmov_dreg_indirect_addr(float *out) +{ + int pass =3D true; + fill_arr(out, -1.0); + + register float *out_addr =3D out; + asm volatile( + "mov #8,r0\n" + "fldi0 fr0\n" + "fldi1 fr1\n" + "fschg\n" /* Set fast pairs on */ + "fmov dr0, @(r0, %0)\n" + "fschg\n" /* Set fast pairs off */ + : : "r" (out_addr) : "memory" + ); + + if (out[2] !=3D 0.0) { + fprintf( + stderr, + "fmov dreg,indirect_addr failed. " \ + "Expected element 0 to be %f, got %f\n", 0.0, out[2] + ); + pass =3D false; + } + + if (out[3] !=3D 1.0) { + fprintf( + stderr, + "fmov dreg,indirect_addr failed. " \ + "Expected element 1 to be %f, got %f\n", 1.0, out[3] + ); + pass =3D false; + } + + fill_arr(out, 0.0); + return pass; +} + +/* uses fmov @(r0,rm),drn instruction */ +static int test_fmov_indirect_addr_dreg(const float *in) +{ + int pass =3D true; + + const register float *in_addr asm ("r1") =3D in; + register float write_out_0 asm ("fr0") =3D 0.0; + register float write_out_1 asm ("fr1") =3D 0.0; + asm volatile( + "mov #8,r0\n" + "fschg\n" /* Set fast pairs on */ + "fmov @(r0, %2), dr0\n" + "fschg\n" /* Set fast pairs off */ + : "=3Df" (write_out_0), "=3Df" (write_out_1) : "r" (in_addr) : "me= mory" + ); + + if (write_out_0 !=3D in[2]) { + fprintf( + stderr, + "fmov indirect_addr,dreg failed. " \ + "Expected element 0 to be %f, got %f\n", in[2], write_out_0 + ); + pass =3D false; + } + + if (write_out_1 !=3D in[3]) { + fprintf( + stderr, + "fmov indirect_addr,dreg failed. " \ + "Expected element 1 to be %f, got %f\n", in[3], write_out_1 + ); + pass =3D false; + } + + return pass; +} + +/* + * reads in data from `in` using fast pairs + * writes data to `out` using slow singles + * uses fmov @rm+,drn instruction + * uses fmov frm,@-rn instruction + */ +static int test_fmov_fast_in_slow_out(const float *in, float *out) +{ + int pass =3D true; + fill_arr(out, 0.0); + + const register float *in_addr =3D in; + register float *out_addr =3D out; + asm volatile( + "fschg\n" /* Set fast pairs on */ + "fmov @%0+,dr0\n" + "fmov @%0+,dr2\n" + "fmov @%0+,dr4\n" + "fmov @%0+,dr6\n" + "fmov @%0+,dr8\n" + "fmov @%0+,dr10\n" + "fmov @%0+,dr12\n" + "fmov @%0+,dr14\n" + "fschg\n" /* Set fast pairs off */ + + "add #64,%1\n" /* Start at the back and work to the front */ + "fmov fr15,@-%1\n" + "fmov fr14,@-%1\n" + "fmov fr13,@-%1\n" + "fmov fr12,@-%1\n" + "fmov fr11,@-%1\n" + "fmov fr10,@-%1\n" + "fmov fr9,@-%1\n" + "fmov fr8,@-%1\n" + "fmov fr7,@-%1\n" + "fmov fr6,@-%1\n" + "fmov fr5,@-%1\n" + "fmov fr4,@-%1\n" + "fmov fr3,@-%1\n" + "fmov fr2,@-%1\n" + "fmov fr1,@-%1\n" + "fmov fr0,@-%1\n" + : "+r" (in_addr), "+r" (out_addr) :: "memory" + ); + + for (int i =3D 0; i < ARR_SIZE; i++) { + if (in[i] !=3D out[i]) { + fprintf( + stderr, + "fmov fast->slow failed. " \ + "Expected element %i to be %f, got %f\n", i, in[i], ou= t[i] + ); + pass =3D false; + } + } + + fill_arr(out, 0.0); + return pass; +} + +/* reads in data from `in` using slow singles */ +/* writes data to `out` using fast pairs */ +/* uses fmov @rm+,frn instruction */ +/* uses fmov drm,@-rn instruction */ +static int test_fmov_slow_in_fast_out(const float in[16], float out[16]) +{ + int pass =3D true; + fill_arr(out, 0.0); + + const register float *in_addr =3D in; + register float *out_addr =3D out; + asm volatile( + "fmov @%0+,fr0\n" + "fmov @%0+,fr1\n" + "fmov @%0+,fr2\n" + "fmov @%0+,fr3\n" + "fmov @%0+,fr4\n" + "fmov @%0+,fr5\n" + "fmov @%0+,fr6\n" + "fmov @%0+,fr7\n" + "fmov @%0+,fr8\n" + "fmov @%0+,fr9\n" + "fmov @%0+,fr10\n" + "fmov @%0+,fr11\n" + "fmov @%0+,fr12\n" + "fmov @%0+,fr13\n" + "fmov @%0+,fr14\n" + "fmov @%0+,fr15\n" + + "fschg\n" /* Set fast pairs on */ + "add #64,%1\n" /* Start at the back and work to the front */ + "fmov dr14,@-%1\n" + "fmov dr12,@-%1\n" + "fmov dr10,@-%1\n" + "fmov dr8,@-%1\n" + "fmov dr6,@-%1\n" + "fmov dr4,@-%1\n" + "fmov dr2,@-%1\n" + "fmov dr0,@-%1\n" + "fschg\n" /* Set fast pairs off */ + : "+r" (in_addr), "+r" (out_addr) :: "memory" + ); + + for (int i =3D 0; i < ARR_SIZE; i++) { + if (in[i] !=3D out[i]) { + fprintf( + stderr, + "fmov slow->fast failed. " \ + "Expected element %i to be %f, got %f\n", i, in[i], ou= t[i] + ); + pass =3D false; + } + } + + fill_arr(out, 0.0); + return pass; +} + +int main(void) +{ + single_precision_mode(); + int pass =3D true; + + if (!test_fmov_freg_freg()) { + pass =3D false; + }; + + if (!test_fmov_freg_addr(out_arr)) { + pass =3D false; + } + + if (!test_fmov_addr_freg(in_arr)) { + pass =3D false; + } + + if (!test_fmov_freg_indirect_addr(out_arr)) { + pass =3D false; + } + + if (!test_fmov_indirect_addr_freg(in_arr)) { + pass =3D false; + }; + + if (!test_fmov_dreg_dreg()) { + pass =3D false; + } + + if (!test_fmov_dreg_addr(out_arr)) { + pass =3D false; + } + + if (!test_fmov_addr_dreg(in_arr)) { + pass =3D false; + } + + if (!test_fmov_dreg_indirect_addr(out_arr)) { + pass =3D false; + } + + if (!test_fmov_indirect_addr_dreg(in_arr)) { + pass =3D false; + }; + + if (!test_fmov_fast_in_slow_out(in_arr, out_arr)) { + pass =3D false; + } + + if (!test_fmov_slow_in_fast_out(in_arr, out_arr)) { + pass =3D false; + } + + if (!pass) { + fprintf( + stderr, + "Fmov tests failed\n" + ); + abort(); + } + + return 0; +} --=20 2.43.0 From nobody Mon Sep 28 02:08:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1785358595; cv=none; d=zohomail.com; s=zohoarc; b=M3b4fB2KPLPp4KZfJ8QmCAli0NUu2YGmXSZ3iwrHE0mLLLZuZuOP0AD/hykFEgLdLrdljrRw/XNDMVCJePvx6zMfnZGL7xI78IZjVztDLGZ7Z6Ov2cv4owUAGOCcBGP+pbBrx0nIsIfNwgUMesOHDWSI+GvpUsKQpC6ijfLgxbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785358595; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 29 Jul 2026 13:55:47 -0700 (PDT) From: Randy Schifflin Date: Wed, 29 Jul 2026 13:55:08 -0700 Subject: [PATCH 2/2] target/sh4: fixup tcg generation for sh4 `fmov` instructions. MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260729-sh4-fix-fmov-instructions-b4-v1-2-65cc9679025a@gmail.com> References: <20260729-sh4-fix-fmov-instructions-b4-v1-0-65cc9679025a@gmail.com> In-Reply-To: <20260729-sh4-fix-fmov-instructions-b4-v1-0-65cc9679025a@gmail.com> To: qemu-devel@nongnu.org Cc: Yoshinori Sato , qemu-trivial@nongnu.org, Randy Schifflin X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openssh-sha256; t=1785358542; l=7410; i=randy.schifflin@gmail.com; s=id_rsa; h=from:subject:message-id; bh=08WCZqu/9I1ItEc38de3w3oVAgSe2Jwf4MRVglV4fIA=; b=U1NIU0lHAAAAAQAAAZcAAAAHc3NoLXJzYQAAAAMBAAEAAAGBALXHj1ozDvr3TmWcPoueK1kIy Q3yQ7HL5bbiu8J+P0QBzcchmw5nwN0avQmreXhYuMhz40g0dhCJPnJqNHg1FBflQPz2cgY7Utm3 9lQrK/CQqWsjRwXMinMR7LrmtMFp9+up7MzdXoxmTLgPsKJ/dQmx0rUHx++mUSl8zl7lHO50YVD hsw1RHrkrXlxnUjRi+jtjgErRHvoRwSZpKc44yR62wV8chkTMnHtrn8hgL0Hh+jhHteNn4JTQB/ wme8MghhliXR5oh9xirpeLlS9S4TBY3Vdk6ccgvncSS4uF/y2ZAAV5sNiLZ97OFkBhIQ0bXhVx9 w1LPMkho650Iu9da5/0koNheHS2KAVC2FdPTyaxvqeFAsAB8fCprfh4lpShdcVpyChdd2KXFS53 s9MAUQmZjG0pQvS/dqGCCDWqo7cY3J3VTMXwVtdzYkgZt5eMajL7z8VljXQ08ZgAStdizC/rHNg wy+fIL+6kgxvL/NhJwoiAWhC4D+xQY7SXjJGTvwAAAAZwYXRhdHQAAAAAAAAABnNoYTUxMgAAAZ QAAAAMcnNhLXNoYTItNTEyAAABgJjD4YoyAJVx6YtKFG4DSSZ/lM6zGXP9xkBv7C+WE5SzuSsdd LedRuHa39qoKmU6v3H/r/pH8lg0GWUXg5ch8vWkPmCVdNTN9bcOzWz4BrEtvS5GWMx+aPQbTOxI ANWgmRIm2zSNBouVhlm0VEJf8MojWDrBEIZI7AtB2BEo2hM/UpSCM4E+U02ymKjasXEL+ykMXZ3 x64eXVrqHpokqY++awMVml87SO6jQwfM6ek20UqBR3G9cT5Ofd0qitKzfYD3EjX+lvU6IbExt6N DSKobS78MkZy7ef4OjVVpn7JMOiYGR+UJMPFsfe74apOk2Uyd48/pUUOgGTqgAFSIPWCDgqpgul WCGAkFqjdo+f+Ho5t6I0O9gQBG+THI3lHfcs5EL6ffdCJZdlmgQrfpuXGoOWQpphbNGL7Ecvd6R cLoJb5wAPqhOuwYZpY0eZ6nk7CKDp38QB/NZJasW9d5jFWvxJZReIqhkBpt9TrcmebbgUSMZZfv hIgcG3no2hgilAA== X-Developer-Key: i=randy.schifflin@gmail.com; a=openssh; fpr=SHA256:7gww1tlDoVPb7symWGdTNhRWcHyTORA23OcjS8eyd8Y Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=randy.schifflin@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1785358598608158500 Fixes TCG generation for sh4 `fmov` instructions. Updates the current logic for these instructions to correctly handle SH4 pair single-precision data transfer semantics. According to the SH4 cpu manual, `fmov` between a double-precision register operand and memory requires the precision mode to be single-precision and the transfer size mode to be pairwise f32. The result is reading/writing a pair of two f32 values to/from memory. In little-endian mode, this has slightly different semantics than the current implementation which handles reads/writes as a single f64 value- the first and second words get incorrectly reversed. Signed-off-by: Randy Schifflin Reviewed-by: Yoshinori Sato --- target/sh4/translate.c | 82 +++++++++++++++++++++++++++++-----------------= ---- 1 file changed, 47 insertions(+), 35 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 373950fd66..8fe3b15e50 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -962,10 +962,14 @@ static void _decode_opc(DisasContext * ctx) case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, XHACK(B7_4)); - tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, - MO_TEUQ | MO_ALIGN); + TCGv addr =3D tcg_temp_new_i32(); + int xsrc =3D XHACK(B7_4); + + tcg_gen_qemu_st_i32(FREG(xsrc), REG(B11_8), ctx->memidx, + MO_TEUL | MO_ALIGN); + tcg_gen_addi_i32(addr, REG(B11_8), 4); + tcg_gen_qemu_st_i32(FREG(xsrc + 1), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); } else { tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL | MO_ALIGN); @@ -974,23 +978,29 @@ static void _decode_opc(DisasContext * ctx) case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv_i64 fp =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, - MO_TEUQ | MO_ALIGN); - gen_store_fpr64(ctx, fp, XHACK(B11_8)); + TCGv addr =3D tcg_temp_new_i32(); + int xdst =3D XHACK(B11_8); + tcg_gen_qemu_ld_i32(FREG(xdst), REG(B7_4), ctx->memidx, + MO_TEUL | MO_ALIGN); + tcg_gen_addi_i32(addr, REG(B7_4), 4); + tcg_gen_qemu_ld_i32(FREG(xdst + 1), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL | MO_ALIGN); } return; + case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv_i64 fp =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, - MO_TEUQ | MO_ALIGN); - gen_store_fpr64(ctx, fp, XHACK(B11_8)); - tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); + int xdst =3D XHACK(B11_8); + tcg_gen_qemu_ld_i32(FREG(xdst), REG(B7_4), ctx->memidx, + MO_TEUL | MO_ALIGN); + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); + tcg_gen_qemu_ld_i32(FREG(xdst + 1), REG(B7_4), ctx->memidx, + MO_TEUL | MO_ALIGN); + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL | MO_ALIGN); @@ -999,20 +1009,18 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED - { - TCGv addr =3D tcg_temp_new_i32(); - if (ctx->tbflags & FPSCR_SZ) { - TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, XHACK(B7_4)); - tcg_gen_subi_i32(addr, REG(B11_8), 8); - tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, - MO_TEUQ | MO_ALIGN); - } else { - tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, - MO_TEUL | MO_ALIGN); - } - tcg_gen_mov_i32(REG(B11_8), addr); + if (ctx->tbflags & FPSCR_SZ) { + int xdst =3D XHACK(B7_4); + tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); + tcg_gen_qemu_st_i32(FREG(xdst + 1), REG(B11_8), ctx->memidx, + MO_TEUL | MO_ALIGN); + tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); + tcg_gen_qemu_st_i32(FREG(xdst), REG(B11_8), ctx->memidx, + MO_TEUL | MO_ALIGN); + } else { + tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); + tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUL | MO_ALIGN); } return; case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ @@ -1021,10 +1029,12 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new_i32(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - TCGv_i64 fp =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, - MO_TEUQ | MO_ALIGN); - gen_store_fpr64(ctx, fp, XHACK(B11_8)); + int xdst =3D XHACK(B11_8); + tcg_gen_qemu_ld_i32(FREG(xdst), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); + tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_qemu_ld_i32(FREG(xdst + 1), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEUL | MO_ALIGN); @@ -1037,10 +1047,12 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, XHACK(B7_4)); - tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, - MO_TEUQ | MO_ALIGN); + int xsrc =3D XHACK(B7_4); + tcg_gen_qemu_st_i32(FREG(xsrc), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); + tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_qemu_st_i32(FREG(xsrc + 1), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); } else { tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL | MO_ALIGN); --=20 2.43.0