[PATCH 0/2] target/i386: Add missing features for Hygon Dhyana and support for Dharma

Yanjing Zhou posted 2 patches 1 day, 18 hours ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260723115220.258924-1-zhouyanjing@open-hieco.net
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Zhao Liu <zhao1.liu@intel.com>
target/i386/cpu.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
[PATCH 0/2] target/i386: Add missing features for Hygon Dhyana and support for Dharma
Posted by Yanjing Zhou 1 day, 18 hours ago
This series adds missing CPU feature bits for the Hygon Dhyana model and
introduces support for the new Hygon Dharma CPU model.

Patch 1 adds several features that were previously missing on the Dhyana
model:
  - perfctr-core, clzero, xsaveerptr, aes, pclmulqdq, sha-ni

Patch 2 adds the Dharma CPU model (2nd Gen Hygon Processor) with the
following additional features compared to Dhyana:
  - stibp, ibrs, umip, ssbd
  - Full cache information (L1/L2/L3) and proper CPUID topology

Yanjing Zhou (2):
  target/i386: Add missing cpu feature bits in Dhyana model
  target/i386: Add support for Hygon Dharma CPU model

 target/i386/cpu.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

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2.34.1