From nobody Sat Jul 25 06:35:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784810337621195.693326009354; Thu, 23 Jul 2026 05:38:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wmshQ-0000i2-WC; Thu, 23 Jul 2026 08:38:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wms5w-0004bb-W6 for qemu-devel@nongnu.org; Thu, 23 Jul 2026 08:00:09 -0400 Received: from [115.124.28.113] (helo=out28-113.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wms5n-00024s-BC for qemu-devel@nongnu.org; Thu, 23 Jul 2026 08:00:08 -0400 Received: from hygon.hygon.cn(mailfrom:zhouyanjing@open-hieco.net fp:SMTPD_---.iTBeEln_1784807548 cluster:ay29) by smtp.aliyun-inc.com; Thu, 23 Jul 2026 19:52:31 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.09242918|-1; BR=01201311R901S49rulernew998_84748_2000303; CH=blue; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.0103836-0.00598067-0.983636; FP=7486460455884130774|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033037071049; MF=zhouyanjing@open-hieco.net; NM=1; PH=DS; RN=2; RT=2; SR=0; TI=SMTPD_---.iTBeEln_1784807548; From: Yanjing Zhou To: qemu-devel@nongnu.org Cc: Yanjing Zhou Subject: [PATCH 1/2] target/i386: Add missing cpu feature bits in Dhyana model Date: Thu, 23 Jul 2026 11:52:19 +0000 Message-Id: <20260723115220.258924-2-zhouyanjing@open-hieco.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260723115220.258924-1-zhouyanjing@open-hieco.net> References: <20260723115220.258924-1-zhouyanjing@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.113 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.113; envelope-from=zhouyanjing@open-hieco.net; helo=out28-113.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 23 Jul 2026 08:38:50 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1784810339411158500 Content-Type: text/plain; charset="utf-8" Add the missing features(perfctr-core, clzero, xsaveerptr, aes, pclmulqdq, sha-ni) for Dhyana model Signed-off-by: Yanjing Zhou --- target/i386/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5805d33ab9..0ce5bdad38 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6754,6 +6754,19 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } }, }, + { .version =3D 3, + .props =3D (PropValue[]) { + { "perfctr-core", "on" }, + { "clzero", "on" }, + { "xsaveerptr", "on" }, + { "aes", "on" }, + { "pclmulqdq", "on" }, + { "sha-ni", "on" }, + { "model-id", + "Hygon Dhyana-v3 processor" }, + { /* end of list */ } + }, + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Sat Jul 25 06:35:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1784810354693889.2687579932118; Thu, 23 Jul 2026 05:39:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wmshQ-0000hX-Hb; Thu, 23 Jul 2026 08:38:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wms5v-0004bP-Kz for qemu-devel@nongnu.org; Thu, 23 Jul 2026 08:00:07 -0400 Received: from [115.124.28.107] (helo=out28-107.mail.aliyun.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wms5m-00027D-Sy for qemu-devel@nongnu.org; Thu, 23 Jul 2026 08:00:07 -0400 Received: from hygon.hygon.cn(mailfrom:zhouyanjing@open-hieco.net fp:SMTPD_---.iTBeEom_1784807551 cluster:ay29) by smtp.aliyun-inc.com; Thu, 23 Jul 2026 19:52:34 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436259|-1; BR=01201311R261S34rulernew998_84748_2000303; CH=blue; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0266512-0.0038128-0.969536; FP=5184497540002400085|0|0|0|0|-1|-1|-1; HT=maildocker-contentspam033045213054; MF=zhouyanjing@open-hieco.net; NM=1; PH=DS; RN=2; RT=2; SR=0; TI=SMTPD_---.iTBeEom_1784807551; From: Yanjing Zhou To: qemu-devel@nongnu.org Cc: Yanjing Zhou Subject: [PATCH 2/2] target/i386: Add support for Hygon Dharma CPU model Date: Thu, 23 Jul 2026 11:52:20 +0000 Message-Id: <20260723115220.258924-3-zhouyanjing@open-hieco.net> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260723115220.258924-1-zhouyanjing@open-hieco.net> References: <20260723115220.258924-1-zhouyanjing@open-hieco.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.124.28.107 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.107; envelope-from=zhouyanjing@open-hieco.net; helo=out28-107.mail.aliyun.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RDNS_NONE=0.793, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 23 Jul 2026 08:38:50 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1784810357853158500 Content-Type: text/plain; charset="utf-8" Add the support for 2nd Gen Hygon Processors. The model display name will be Hygon Dharma Processor. Add the following feature bits compare to Dhyana CPU model: stibp, ibrs, umip, ssbd Signed-off-by: Yanjing Zhou --- target/i386/cpu.c | 105 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0ce5bdad38..9125c22326 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3049,6 +3049,60 @@ static const CPUCaches epyc_turin_cache_info =3D { } }; =20 +static const CPUCaches dharma_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 512 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 1024, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 16 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .partitions =3D 1, + .sets =3D 16384, + .lines_per_tag =3D 1, + .self_init =3D true, + .no_invd_sharing =3D true, + .complex_indexing =3D false, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + static const CPUCaches xeon_spr_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { /* CPUID 0x4.0x0.EAX */ @@ -7323,6 +7377,57 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .name =3D "Dharma", + .level =3D 0xd, + .vendor =3D CPUID_VENDOR_HYGON, + .family =3D 24, + .model =3D 4, + .stepping =3D 0, + .features[FEAT_1_EDX] =3D + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUS= H | + CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | + CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | + CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | + CPUID_VME | CPUID_FP87, + .features[FEAT_1_ECX] =3D + CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | + CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | + CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | + CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | + CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | + CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | + CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | + CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, + .features[FEAT_8000_0008_EBX] =3D + CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | + CPUID_8000_0008_EBX_IBPB | CPUID_8000_0008_EBX_IBRS | + CPUID_8000_0008_EBX_STIBP | CPUID_8000_0008_EBX_AMD_SSBD, + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AV= X2 | + CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED= | + CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSH= OPT | + CPUID_7_0_EBX_SHA_NI, + .features[FEAT_7_0_ECX] =3D CPUID_7_0_ECX_UMIP, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] =3D + CPUID_6_EAX_ARAT, + .features[FEAT_SVM] =3D + CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, + .xlevel =3D 0x8000001E, + .model_id =3D "Hygon Dharma Processor", + .cache_info =3D &dharma_cache_info, + }, }; =20 /* --=20 2.34.1