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[PATCH v7 00/11] target/riscv: Implement Smsdid and Smmpt extension

LIU Zhiwei posted 11 patches 1 week, 3 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260715145016.17369-1-zhiwei._5Fliu@linux.alibaba.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Weiwei Li <liwei1518@gmail.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu@processmission.com>
There is a newer version of this series
disas/riscv.c                                 |   9 +-
target/riscv/cpu.c                            |  60 +++-
target/riscv/cpu.h                            |   8 +
target/riscv/cpu_bits.h                       |  27 ++
target/riscv/cpu_cfg_fields.h.inc             |   3 +
target/riscv/insn32.decode                    |   2 +
target/riscv/meson.build                      |   1 +
target/riscv/riscv_smmpt.c                    | 339 ++++++++++++++++++
target/riscv/riscv_smmpt.h                    |  26 ++
target/riscv/tcg/cpu_helper.c                 | 119 +++++-
target/riscv/tcg/csr.c                        | 106 ++++++
.../tcg/insn_trans/trans_privileged.c.inc     |  30 ++
target/riscv/tcg/pmp.h                        |   3 +
tests/tcg/riscv64/Makefile.softmmu-target     |  12 +
tests/tcg/riscv64/smmpt-common.S              | 256 +++++++++++++
tests/tcg/riscv64/test-smmpt.S                |  85 +++++
tests/tcg/riscv64/test-smmpt34.S              |  97 +++++
tests/tcg/riscv64/test-smmpt52.S              |  91 +++++
tests/tcg/riscv64/test-smmpt64.S              |  98 +++++
19 files changed, 1353 insertions(+), 19 deletions(-)
create mode 100644 target/riscv/riscv_smmpt.c
create mode 100644 target/riscv/riscv_smmpt.h
create mode 100644 tests/tcg/riscv64/smmpt-common.S
create mode 100644 tests/tcg/riscv64/test-smmpt.S
create mode 100644 tests/tcg/riscv64/test-smmpt34.S
create mode 100644 tests/tcg/riscv64/test-smmpt52.S
create mode 100644 tests/tcg/riscv64/test-smmpt64.S
[PATCH v7 00/11] target/riscv: Implement Smsdid and Smmpt extension
Posted by LIU Zhiwei 1 week, 3 days ago 
This patch set introduces support for the RISC-V Smsdid and Smmpt
(Supervisor Domain Identifier and Memory Protection Table) extensions
v0.4.9(https://github.com/riscv/riscv-smmtt/releases/tag/v0.4.9).
Smmpt provides a hardware mechanism for fine-grained memory protection,
checked after address translation, which is particularly useful for
supervisor-level sandboxing and security monitoring.

The rfc patch set:
https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html

v6->v7:
    The implementation is updated from the v0.3.4 specification to
    v0.4.9. The main changes are:
    1. Update the mmpt CSR number to 0x382 and msdcfg to 0x74E.
    2. Update the mmpt register layout: the SDID and PPN field positions
       changed and the RV64 PPN is now 44 bits.
    3. Rework the MPTE format: the N (NAPOT) bit now lives at bit 2, the
       non-leaf NAPOT form is removed, NAPOT leaf entries encode a single
       XWR tuple plus a G granularity field, and non-NAPOT leaf entries
       hold per-page XWR tuples.
    4. Treat XWR=000 as "no access" and a non-leaf entry with N=1 as a
       fault.
    5. Enforce the Smmpt64 root-table PPN alignment (low 3 bits zero).
    6. Rename the fence instructions mfence.spa/minval.spa to
       mfence.pa/minval.pa.
    7. Drop stale Reviewed-by tags on the substantially reworked patches.
    8. Introduce the configurable "smmpt-sdidlen" CPU property.
    9. Add disassembly support for the Smmpt.
    10. Add bare-metal M-mode system tests.
    11. Rebase to master.

v5->v6:
    1. Use explicitly bit fields extract instead of mpte_union_t.
    2. Use the same exception behavior for MPT valiation as PMP
       valiation.
    3. Use PAGE_* instead of MPT_ACCESS_* as they have same value.
    4. Use address_space_*_le instead of address_space_* for SMMPT.
    5. Only print SMMPT address check log when SMMPT is enabled.
    6. Add implied rule for SMMPT as it depends on SMSDID.
    7. Rebase to master.

v4->v5:
    1. Rebase to master.
v3->v4:
    1. Add missing review tags.
v2->v3:
    1. Fix build error in patch 2.
    2. Rebase to master.

rfc->v2:
    1. When ext_smmpt is false or BARE mode, make other fields in mmpt
       CSR zero.
    2. Add patch 5 to fix smrnmi ISA string order.
    3. Fix patch 6 smmpt and smsdid ISA string order.
    4. Make smmpt and smsdid experiment extensions.
    5. Add review tags.

LIU Zhiwei (11):
  target/riscv: Add basic definitions and CSRs for SMMPT
  target/riscv: Add smmpt-sdidlen property for the mmpt SDID field
  target/riscv: Implement core SMMPT lookup logic
  target/riscv: Integrate SMMPT checks into MMU and TLB fill
  target/riscv: Implement SMMPT fence instructions
  target/riscv: Fix smrnmi isa alphabetical order
  target/riscv: Add disassembly for Smmpt instructions and CSRs
  target/riscv: Enable SMMPT extension
  target/riscv: Add system test for SMMPT extension
  target/riscv: Add system tests for Smmpt52 and Smmpt64
  target/riscv: Add system test for Smmpt34

 disas/riscv.c                                 |   9 +-
 target/riscv/cpu.c                            |  60 +++-
 target/riscv/cpu.h                            |   8 +
 target/riscv/cpu_bits.h                       |  27 ++
 target/riscv/cpu_cfg_fields.h.inc             |   3 +
 target/riscv/insn32.decode                    |   2 +
 target/riscv/meson.build                      |   1 +
 target/riscv/riscv_smmpt.c                    | 339 ++++++++++++++++++
 target/riscv/riscv_smmpt.h                    |  26 ++
 target/riscv/tcg/cpu_helper.c                 | 119 +++++-
 target/riscv/tcg/csr.c                        | 106 ++++++
 .../tcg/insn_trans/trans_privileged.c.inc     |  30 ++
 target/riscv/tcg/pmp.h                        |   3 +
 tests/tcg/riscv64/Makefile.softmmu-target     |  12 +
 tests/tcg/riscv64/smmpt-common.S              | 256 +++++++++++++
 tests/tcg/riscv64/test-smmpt.S                |  85 +++++
 tests/tcg/riscv64/test-smmpt34.S              |  97 +++++
 tests/tcg/riscv64/test-smmpt52.S              |  91 +++++
 tests/tcg/riscv64/test-smmpt64.S              |  98 +++++
 19 files changed, 1353 insertions(+), 19 deletions(-)
 create mode 100644 target/riscv/riscv_smmpt.c
 create mode 100644 target/riscv/riscv_smmpt.h
 create mode 100644 tests/tcg/riscv64/smmpt-common.S
 create mode 100644 tests/tcg/riscv64/test-smmpt.S
 create mode 100644 tests/tcg/riscv64/test-smmpt34.S
 create mode 100644 tests/tcg/riscv64/test-smmpt52.S
 create mode 100644 tests/tcg/riscv64/test-smmpt64.S


base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
-- 
2.43.0
Re: [PATCH v7 00/11] target/riscv: Implement Smsdid and Smmpt extension
Posted by Alistair 3 days, 15 hours ago 
On Wed, 2026-07-15 at 22:50 +0800, LIU Zhiwei wrote:
> This patch set introduces support for the RISC-V Smsdid and Smmpt
> (Supervisor Domain Identifier and Memory Protection Table) extensions
> v0.4.9(https://github.com/riscv/riscv-smmtt/releases/tag/v0.4.9).
> Smmpt provides a hardware mechanism for fine-grained memory
> protection,
> checked after address translation, which is particularly useful for
> supervisor-level sandboxing and security monitoring.

Can you include a link to the upstream submitted patches to use this
functionality

Alistair

> 
> The rfc patch set:
> https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html
> 
> v6->v7:
>     The implementation is updated from the v0.3.4 specification to
>     v0.4.9. The main changes are:
>     1. Update the mmpt CSR number to 0x382 and msdcfg to 0x74E.
>     2. Update the mmpt register layout: the SDID and PPN field
> positions
>        changed and the RV64 PPN is now 44 bits.
>     3. Rework the MPTE format: the N (NAPOT) bit now lives at bit 2,
> the
>        non-leaf NAPOT form is removed, NAPOT leaf entries encode a
> single
>        XWR tuple plus a G granularity field, and non-NAPOT leaf
> entries
>        hold per-page XWR tuples.
>     4. Treat XWR=000 as "no access" and a non-leaf entry with N=1 as
> a
>        fault.
>     5. Enforce the Smmpt64 root-table PPN alignment (low 3 bits
> zero).
>     6. Rename the fence instructions mfence.spa/minval.spa to
>        mfence.pa/minval.pa.
>     7. Drop stale Reviewed-by tags on the substantially reworked
> patches.
>     8. Introduce the configurable "smmpt-sdidlen" CPU property.
>     9. Add disassembly support for the Smmpt.
>     10. Add bare-metal M-mode system tests.
>     11. Rebase to master.
> 
> v5->v6:
>     1. Use explicitly bit fields extract instead of mpte_union_t.
>     2. Use the same exception behavior for MPT valiation as PMP
>        valiation.
>     3. Use PAGE_* instead of MPT_ACCESS_* as they have same value.
>     4. Use address_space_*_le instead of address_space_* for SMMPT.
>     5. Only print SMMPT address check log when SMMPT is enabled.
>     6. Add implied rule for SMMPT as it depends on SMSDID.
>     7. Rebase to master.
> 
> v4->v5:
>     1. Rebase to master.
> v3->v4:
>     1. Add missing review tags.
> v2->v3:
>     1. Fix build error in patch 2.
>     2. Rebase to master.
> 
> rfc->v2:
>     1. When ext_smmpt is false or BARE mode, make other fields in
> mmpt
>        CSR zero.
>     2. Add patch 5 to fix smrnmi ISA string order.
>     3. Fix patch 6 smmpt and smsdid ISA string order.
>     4. Make smmpt and smsdid experiment extensions.
>     5. Add review tags.
> 
> LIU Zhiwei (11):
>   target/riscv: Add basic definitions and CSRs for SMMPT
>   target/riscv: Add smmpt-sdidlen property for the mmpt SDID field
>   target/riscv: Implement core SMMPT lookup logic
>   target/riscv: Integrate SMMPT checks into MMU and TLB fill
>   target/riscv: Implement SMMPT fence instructions
>   target/riscv: Fix smrnmi isa alphabetical order
>   target/riscv: Add disassembly for Smmpt instructions and CSRs
>   target/riscv: Enable SMMPT extension
>   target/riscv: Add system test for SMMPT extension
>   target/riscv: Add system tests for Smmpt52 and Smmpt64
>   target/riscv: Add system test for Smmpt34
> 
>  disas/riscv.c                                 |   9 +-
>  target/riscv/cpu.c                            |  60 +++-
>  target/riscv/cpu.h                            |   8 +
>  target/riscv/cpu_bits.h                       |  27 ++
>  target/riscv/cpu_cfg_fields.h.inc             |   3 +
>  target/riscv/insn32.decode                    |   2 +
>  target/riscv/meson.build                      |   1 +
>  target/riscv/riscv_smmpt.c                    | 339
> ++++++++++++++++++
>  target/riscv/riscv_smmpt.h                    |  26 ++
>  target/riscv/tcg/cpu_helper.c                 | 119 +++++-
>  target/riscv/tcg/csr.c                        | 106 ++++++
>  .../tcg/insn_trans/trans_privileged.c.inc     |  30 ++
>  target/riscv/tcg/pmp.h                        |   3 +
>  tests/tcg/riscv64/Makefile.softmmu-target     |  12 +
>  tests/tcg/riscv64/smmpt-common.S              | 256 +++++++++++++
>  tests/tcg/riscv64/test-smmpt.S                |  85 +++++
>  tests/tcg/riscv64/test-smmpt34.S              |  97 +++++
>  tests/tcg/riscv64/test-smmpt52.S              |  91 +++++
>  tests/tcg/riscv64/test-smmpt64.S              |  98 +++++
>  19 files changed, 1353 insertions(+), 19 deletions(-)
>  create mode 100644 target/riscv/riscv_smmpt.c
>  create mode 100644 target/riscv/riscv_smmpt.h
>  create mode 100644 tests/tcg/riscv64/smmpt-common.S
>  create mode 100644 tests/tcg/riscv64/test-smmpt.S
>  create mode 100644 tests/tcg/riscv64/test-smmpt34.S
>  create mode 100644 tests/tcg/riscv64/test-smmpt52.S
>  create mode 100644 tests/tcg/riscv64/test-smmpt64.S
> 
> 
> base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
Re: [PATCH v7 00/11] target/riscv: Implement Smsdid and Smmpt extension
Posted by LIU Zhiwei 3 days, 13 hours ago 
On 7/22/26 8:56 AM, Alistair wrote:
> On Wed, 2026-07-15 at 22:50 +0800, LIU Zhiwei wrote:
>> This patch set introduces support for the RISC-V Smsdid and Smmpt
>> (Supervisor Domain Identifier and Memory Protection Table) extensions
>> v0.4.9(https://github.com/riscv/riscv-smmtt/releases/tag/v0.4.9).
>> Smmpt provides a hardware mechanism for fine-grained memory
>> protection,
>> checked after address translation, which is particularly useful for
>> supervisor-level sandboxing and security monitoring.
Hi Alistair,
> Can you include a link to the upstream submitted patches to use this
> functionality
Xiangyi is currently working on OpenSBI support for SMMPT, and we 
already have an internal implementation in place. We plan to upstream 
the OpenSBI support as soon as possible, and once that is done, I’ll be 
able to include a link here.

Thanks,
Zhiwei
>
> Alistair
>
>> The rfc patch set:
>> https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html
>>
>> v6->v7:
>>      The implementation is updated from the v0.3.4 specification to
>>      v0.4.9. The main changes are:
>>      1. Update the mmpt CSR number to 0x382 and msdcfg to 0x74E.
>>      2. Update the mmpt register layout: the SDID and PPN field
>> positions
>>         changed and the RV64 PPN is now 44 bits.
>>      3. Rework the MPTE format: the N (NAPOT) bit now lives at bit 2,
>> the
>>         non-leaf NAPOT form is removed, NAPOT leaf entries encode a
>> single
>>         XWR tuple plus a G granularity field, and non-NAPOT leaf
>> entries
>>         hold per-page XWR tuples.
>>      4. Treat XWR=000 as "no access" and a non-leaf entry with N=1 as
>> a
>>         fault.
>>      5. Enforce the Smmpt64 root-table PPN alignment (low 3 bits
>> zero).
>>      6. Rename the fence instructions mfence.spa/minval.spa to
>>         mfence.pa/minval.pa.
>>      7. Drop stale Reviewed-by tags on the substantially reworked
>> patches.
>>      8. Introduce the configurable "smmpt-sdidlen" CPU property.
>>      9. Add disassembly support for the Smmpt.
>>      10. Add bare-metal M-mode system tests.
>>      11. Rebase to master.
>>
>> v5->v6:
>>      1. Use explicitly bit fields extract instead of mpte_union_t.
>>      2. Use the same exception behavior for MPT valiation as PMP
>>         valiation.
>>      3. Use PAGE_* instead of MPT_ACCESS_* as they have same value.
>>      4. Use address_space_*_le instead of address_space_* for SMMPT.
>>      5. Only print SMMPT address check log when SMMPT is enabled.
>>      6. Add implied rule for SMMPT as it depends on SMSDID.
>>      7. Rebase to master.
>>
>> v4->v5:
>>      1. Rebase to master.
>> v3->v4:
>>      1. Add missing review tags.
>> v2->v3:
>>      1. Fix build error in patch 2.
>>      2. Rebase to master.
>>
>> rfc->v2:
>>      1. When ext_smmpt is false or BARE mode, make other fields in
>> mmpt
>>         CSR zero.
>>      2. Add patch 5 to fix smrnmi ISA string order.
>>      3. Fix patch 6 smmpt and smsdid ISA string order.
>>      4. Make smmpt and smsdid experiment extensions.
>>      5. Add review tags.
>>
>> LIU Zhiwei (11):
>>    target/riscv: Add basic definitions and CSRs for SMMPT
>>    target/riscv: Add smmpt-sdidlen property for the mmpt SDID field
>>    target/riscv: Implement core SMMPT lookup logic
>>    target/riscv: Integrate SMMPT checks into MMU and TLB fill
>>    target/riscv: Implement SMMPT fence instructions
>>    target/riscv: Fix smrnmi isa alphabetical order
>>    target/riscv: Add disassembly for Smmpt instructions and CSRs
>>    target/riscv: Enable SMMPT extension
>>    target/riscv: Add system test for SMMPT extension
>>    target/riscv: Add system tests for Smmpt52 and Smmpt64
>>    target/riscv: Add system test for Smmpt34
>>
>>   disas/riscv.c                                 |   9 +-
>>   target/riscv/cpu.c                            |  60 +++-
>>   target/riscv/cpu.h                            |   8 +
>>   target/riscv/cpu_bits.h                       |  27 ++
>>   target/riscv/cpu_cfg_fields.h.inc             |   3 +
>>   target/riscv/insn32.decode                    |   2 +
>>   target/riscv/meson.build                      |   1 +
>>   target/riscv/riscv_smmpt.c                    | 339
>> ++++++++++++++++++
>>   target/riscv/riscv_smmpt.h                    |  26 ++
>>   target/riscv/tcg/cpu_helper.c                 | 119 +++++-
>>   target/riscv/tcg/csr.c                        | 106 ++++++
>>   .../tcg/insn_trans/trans_privileged.c.inc     |  30 ++
>>   target/riscv/tcg/pmp.h                        |   3 +
>>   tests/tcg/riscv64/Makefile.softmmu-target     |  12 +
>>   tests/tcg/riscv64/smmpt-common.S              | 256 +++++++++++++
>>   tests/tcg/riscv64/test-smmpt.S                |  85 +++++
>>   tests/tcg/riscv64/test-smmpt34.S              |  97 +++++
>>   tests/tcg/riscv64/test-smmpt52.S              |  91 +++++
>>   tests/tcg/riscv64/test-smmpt64.S              |  98 +++++
>>   19 files changed, 1353 insertions(+), 19 deletions(-)
>>   create mode 100644 target/riscv/riscv_smmpt.c
>>   create mode 100644 target/riscv/riscv_smmpt.h
>>   create mode 100644 tests/tcg/riscv64/smmpt-common.S
>>   create mode 100644 tests/tcg/riscv64/test-smmpt.S
>>   create mode 100644 tests/tcg/riscv64/test-smmpt34.S
>>   create mode 100644 tests/tcg/riscv64/test-smmpt52.S
>>   create mode 100644 tests/tcg/riscv64/test-smmpt64.S
>>
>>
>> base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
Re: [PATCH v7 00/11] target/riscv: Implement Smsdid and Smmpt extension
Posted by Daniel Henrique Barboza 2 days, 20 hours ago 

On 7/22/2026 12:11 AM, LIU Zhiwei wrote:
> 
> On 7/22/26 8:56 AM, Alistair wrote:
>> On Wed, 2026-07-15 at 22:50 +0800, LIU Zhiwei wrote:
>>> This patch set introduces support for the RISC-V Smsdid and Smmpt
>>> (Supervisor Domain Identifier and Memory Protection Table) extensions
>>> v0.4.9(https://github.com/riscv/riscv-smmtt/releases/tag/v0.4.9).
>>> Smmpt provides a hardware mechanism for fine-grained memory
>>> protection,
>>> checked after address translation, which is particularly useful for
>>> supervisor-level sandboxing and security monitoring.
> Hi Alistair,
>> Can you include a link to the upstream submitted patches to use this
>> functionality
> Xiangyi is currently working on OpenSBI support for SMMPT, and we already have an internal implementation in place. We plan to upstream the OpenSBI support as soon as possible, and once that is done, I’ll be able to include a link here.

Please be aware that Rahul already sent OpenSBI patches for smmpt and smsdid:

[RFC PATCH 0/5] Add Smsdid and Smmpt supervisor domain protection
https://lists.infradead.org/pipermail/opensbi/2026-July/010235.html

In fact, as I said in another thread [1], Rahul also has a QEMU implementation of his own.
His OpenSBI patches works with his QEMU changes:

https://github.com/pathakraul/qemu/tree/rpathak_smmpt_v1

But seems like his OpenSBI patches does *not* work with this QEMU patches, but works
with his QEMU implementation.  Seems like there might be things to improve in both
implementations.

I asked him to not send his QEMU patches on top of yours because I'd rather work in
collaboration on top of a single series, and I advise to not send another OpenSBI support
for the same stuff in that mailing as well.

IMO you and Rahul should sync up in both OpenSBI and QEMU bits to avoid effort duplication
on both sides.


Cheers,
Daniel


[1] https://lore.kernel.org/qemu-devel/2e2de5da-9eb0-4d56-b193-d8b06b7a3512@oss.qualcomm.com/


> 
> Thanks,
> Zhiwei
>>
>> Alistair
>>
>>> The rfc patch set:
>>> https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html
>>>
>>> v6->v7:
>>>      The implementation is updated from the v0.3.4 specification to
>>>      v0.4.9. The main changes are:
>>>      1. Update the mmpt CSR number to 0x382 and msdcfg to 0x74E.
>>>      2. Update the mmpt register layout: the SDID and PPN field
>>> positions
>>>         changed and the RV64 PPN is now 44 bits.
>>>      3. Rework the MPTE format: the N (NAPOT) bit now lives at bit 2,
>>> the
>>>         non-leaf NAPOT form is removed, NAPOT leaf entries encode a
>>> single
>>>         XWR tuple plus a G granularity field, and non-NAPOT leaf
>>> entries
>>>         hold per-page XWR tuples.
>>>      4. Treat XWR=000 as "no access" and a non-leaf entry with N=1 as
>>> a
>>>         fault.
>>>      5. Enforce the Smmpt64 root-table PPN alignment (low 3 bits
>>> zero).
>>>      6. Rename the fence instructions mfence.spa/minval.spa to
>>>         mfence.pa/minval.pa.
>>>      7. Drop stale Reviewed-by tags on the substantially reworked
>>> patches.
>>>      8. Introduce the configurable "smmpt-sdidlen" CPU property.
>>>      9. Add disassembly support for the Smmpt.
>>>      10. Add bare-metal M-mode system tests.
>>>      11. Rebase to master.
>>>
>>> v5->v6:
>>>      1. Use explicitly bit fields extract instead of mpte_union_t.
>>>      2. Use the same exception behavior for MPT valiation as PMP
>>>         valiation.
>>>      3. Use PAGE_* instead of MPT_ACCESS_* as they have same value.
>>>      4. Use address_space_*_le instead of address_space_* for SMMPT.
>>>      5. Only print SMMPT address check log when SMMPT is enabled.
>>>      6. Add implied rule for SMMPT as it depends on SMSDID.
>>>      7. Rebase to master.
>>>
>>> v4->v5:
>>>      1. Rebase to master.
>>> v3->v4:
>>>      1. Add missing review tags.
>>> v2->v3:
>>>      1. Fix build error in patch 2.
>>>      2. Rebase to master.
>>>
>>> rfc->v2:
>>>      1. When ext_smmpt is false or BARE mode, make other fields in
>>> mmpt
>>>         CSR zero.
>>>      2. Add patch 5 to fix smrnmi ISA string order.
>>>      3. Fix patch 6 smmpt and smsdid ISA string order.
>>>      4. Make smmpt and smsdid experiment extensions.
>>>      5. Add review tags.
>>>
>>> LIU Zhiwei (11):
>>>    target/riscv: Add basic definitions and CSRs for SMMPT
>>>    target/riscv: Add smmpt-sdidlen property for the mmpt SDID field
>>>    target/riscv: Implement core SMMPT lookup logic
>>>    target/riscv: Integrate SMMPT checks into MMU and TLB fill
>>>    target/riscv: Implement SMMPT fence instructions
>>>    target/riscv: Fix smrnmi isa alphabetical order
>>>    target/riscv: Add disassembly for Smmpt instructions and CSRs
>>>    target/riscv: Enable SMMPT extension
>>>    target/riscv: Add system test for SMMPT extension
>>>    target/riscv: Add system tests for Smmpt52 and Smmpt64
>>>    target/riscv: Add system test for Smmpt34
>>>
>>>   disas/riscv.c                                 |   9 +-
>>>   target/riscv/cpu.c                            |  60 +++-
>>>   target/riscv/cpu.h                            |   8 +
>>>   target/riscv/cpu_bits.h                       |  27 ++
>>>   target/riscv/cpu_cfg_fields.h.inc             |   3 +
>>>   target/riscv/insn32.decode                    |   2 +
>>>   target/riscv/meson.build                      |   1 +
>>>   target/riscv/riscv_smmpt.c                    | 339
>>> ++++++++++++++++++
>>>   target/riscv/riscv_smmpt.h                    |  26 ++
>>>   target/riscv/tcg/cpu_helper.c                 | 119 +++++-
>>>   target/riscv/tcg/csr.c                        | 106 ++++++
>>>   .../tcg/insn_trans/trans_privileged.c.inc     |  30 ++
>>>   target/riscv/tcg/pmp.h                        |   3 +
>>>   tests/tcg/riscv64/Makefile.softmmu-target     |  12 +
>>>   tests/tcg/riscv64/smmpt-common.S              | 256 +++++++++++++
>>>   tests/tcg/riscv64/test-smmpt.S                |  85 +++++
>>>   tests/tcg/riscv64/test-smmpt34.S              |  97 +++++
>>>   tests/tcg/riscv64/test-smmpt52.S              |  91 +++++
>>>   tests/tcg/riscv64/test-smmpt64.S              |  98 +++++
>>>   19 files changed, 1353 insertions(+), 19 deletions(-)
>>>   create mode 100644 target/riscv/riscv_smmpt.c
>>>   create mode 100644 target/riscv/riscv_smmpt.h
>>>   create mode 100644 tests/tcg/riscv64/smmpt-common.S
>>>   create mode 100644 tests/tcg/riscv64/test-smmpt.S
>>>   create mode 100644 tests/tcg/riscv64/test-smmpt34.S
>>>   create mode 100644 tests/tcg/riscv64/test-smmpt52.S
>>>   create mode 100644 tests/tcg/riscv64/test-smmpt64.S
>>>
>>>
>>> base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
Re: [PATCH v7 00/11] target/riscv: Implement Smsdid and Smmpt extension
Posted by LIU Zhiwei 2 days, 12 hours ago 
On 7/23/26 3:52 AM, Daniel Henrique Barboza wrote:
>
>
> On 7/22/2026 12:11 AM, LIU Zhiwei wrote:
>>
>> On 7/22/26 8:56 AM, Alistair wrote:
>>> On Wed, 2026-07-15 at 22:50 +0800, LIU Zhiwei wrote:
>>>> This patch set introduces support for the RISC-V Smsdid and Smmpt
>>>> (Supervisor Domain Identifier and Memory Protection Table) extensions
>>>> v0.4.9(https://github.com/riscv/riscv-smmtt/releases/tag/v0.4.9).
>>>> Smmpt provides a hardware mechanism for fine-grained memory
>>>> protection,
>>>> checked after address translation, which is particularly useful for
>>>> supervisor-level sandboxing and security monitoring.
>> Hi Alistair,
>>> Can you include a link to the upstream submitted patches to use this
>>> functionality
>> Xiangyi is currently working on OpenSBI support for SMMPT, and we 
>> already have an internal implementation in place. We plan to upstream 
>> the OpenSBI support as soon as possible, and once that is done, I’ll 
>> be able to include a link here.
>
Hi Daniel
> Please be aware that Rahul already sent OpenSBI patches for smmpt and 
> smsdid:
>
> [RFC PATCH 0/5] Add Smsdid and Smmpt supervisor domain protection
> https://lists.infradead.org/pipermail/opensbi/2026-July/010235.html
>
> In fact, as I said in another thread [1], Rahul also has a QEMU 
> implementation of his own.
> His OpenSBI patches works with his QEMU changes:
>
> https://github.com/pathakraul/qemu/tree/rpathak_smmpt_v1
Thank you very much for pointing this out and for coordinating between 
us. I was not aware of Rahul's OpenSBI patches and QEMU implementation.
>
> But seems like his OpenSBI patches does *not* work with this QEMU patches,
It seams probe_sdidlen in OpenSBI write a sdid to mmpt with bare mode. 
According to the specification, in bare mode, "The remaining fields in 
mmpt (SDID, PPN) must
be set to zeros.
>  but works
> with his QEMU implementation.  Seems like there might be things to 
> improve in both
> implementations.
>
> I asked him to not send his QEMU patches on top of yours because I'd 
> rather work in
> collaboration on top of a single series, and I advise to not send 
> another OpenSBI support
> for the same stuff in that mailing as well.
>
> IMO you and Rahul should sync up in both OpenSBI and QEMU bits to 
> avoid effort duplication
> on both sides.

I agree with your suggestion that it is better to avoid duplicated 
effort and collaborate on a single direction for both the QEMU and 
OpenSBI sides.

Since the SMMPT v0.4.9 specification is already close to stabilization, 
and implementation work has already started in both OpenSBI and QEMU, I 
believe we should be able to converge quickly through collaboration and 
help move SMMPT upstream sooner.

Xiangyi and I will continue to review Rahul's OpenSBI patches to 
understand the current differences and why they are not yet compatible 
with our QEMU series. I will also reach out to Rahul directly so that we 
can sync up and work toward a common implementation.

Thanks again for the pointers.

Best regards,
Zhiwei

>
>
> Cheers,
> Daniel
>
>
> [1] 
> https://lore.kernel.org/qemu-devel/2e2de5da-9eb0-4d56-b193-d8b06b7a3512@oss.qualcomm.com/
>
>
>>
>> Thanks,
>> Zhiwei
>>>
>>> Alistair
>>>
>>>> The rfc patch set:
>>>> https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html
>>>>
>>>> v6->v7:
>>>>      The implementation is updated from the v0.3.4 specification to
>>>>      v0.4.9. The main changes are:
>>>>      1. Update the mmpt CSR number to 0x382 and msdcfg to 0x74E.
>>>>      2. Update the mmpt register layout: the SDID and PPN field
>>>> positions
>>>>         changed and the RV64 PPN is now 44 bits.
>>>>      3. Rework the MPTE format: the N (NAPOT) bit now lives at bit 2,
>>>> the
>>>>         non-leaf NAPOT form is removed, NAPOT leaf entries encode a
>>>> single
>>>>         XWR tuple plus a G granularity field, and non-NAPOT leaf
>>>> entries
>>>>         hold per-page XWR tuples.
>>>>      4. Treat XWR=000 as "no access" and a non-leaf entry with N=1 as
>>>> a
>>>>         fault.
>>>>      5. Enforce the Smmpt64 root-table PPN alignment (low 3 bits
>>>> zero).
>>>>      6. Rename the fence instructions mfence.spa/minval.spa to
>>>>         mfence.pa/minval.pa.
>>>>      7. Drop stale Reviewed-by tags on the substantially reworked
>>>> patches.
>>>>      8. Introduce the configurable "smmpt-sdidlen" CPU property.
>>>>      9. Add disassembly support for the Smmpt.
>>>>      10. Add bare-metal M-mode system tests.
>>>>      11. Rebase to master.
>>>>
>>>> v5->v6:
>>>>      1. Use explicitly bit fields extract instead of mpte_union_t.
>>>>      2. Use the same exception behavior for MPT valiation as PMP
>>>>         valiation.
>>>>      3. Use PAGE_* instead of MPT_ACCESS_* as they have same value.
>>>>      4. Use address_space_*_le instead of address_space_* for SMMPT.
>>>>      5. Only print SMMPT address check log when SMMPT is enabled.
>>>>      6. Add implied rule for SMMPT as it depends on SMSDID.
>>>>      7. Rebase to master.
>>>>
>>>> v4->v5:
>>>>      1. Rebase to master.
>>>> v3->v4:
>>>>      1. Add missing review tags.
>>>> v2->v3:
>>>>      1. Fix build error in patch 2.
>>>>      2. Rebase to master.
>>>>
>>>> rfc->v2:
>>>>      1. When ext_smmpt is false or BARE mode, make other fields in
>>>> mmpt
>>>>         CSR zero.
>>>>      2. Add patch 5 to fix smrnmi ISA string order.
>>>>      3. Fix patch 6 smmpt and smsdid ISA string order.
>>>>      4. Make smmpt and smsdid experiment extensions.
>>>>      5. Add review tags.
>>>>
>>>> LIU Zhiwei (11):
>>>>    target/riscv: Add basic definitions and CSRs for SMMPT
>>>>    target/riscv: Add smmpt-sdidlen property for the mmpt SDID field
>>>>    target/riscv: Implement core SMMPT lookup logic
>>>>    target/riscv: Integrate SMMPT checks into MMU and TLB fill
>>>>    target/riscv: Implement SMMPT fence instructions
>>>>    target/riscv: Fix smrnmi isa alphabetical order
>>>>    target/riscv: Add disassembly for Smmpt instructions and CSRs
>>>>    target/riscv: Enable SMMPT extension
>>>>    target/riscv: Add system test for SMMPT extension
>>>>    target/riscv: Add system tests for Smmpt52 and Smmpt64
>>>>    target/riscv: Add system test for Smmpt34
>>>>
>>>>   disas/riscv.c                                 |   9 +-
>>>>   target/riscv/cpu.c                            |  60 +++-
>>>>   target/riscv/cpu.h                            |   8 +
>>>>   target/riscv/cpu_bits.h                       |  27 ++
>>>>   target/riscv/cpu_cfg_fields.h.inc             |   3 +
>>>>   target/riscv/insn32.decode                    |   2 +
>>>>   target/riscv/meson.build                      |   1 +
>>>>   target/riscv/riscv_smmpt.c                    | 339
>>>> ++++++++++++++++++
>>>>   target/riscv/riscv_smmpt.h                    |  26 ++
>>>>   target/riscv/tcg/cpu_helper.c                 | 119 +++++-
>>>>   target/riscv/tcg/csr.c                        | 106 ++++++
>>>>   .../tcg/insn_trans/trans_privileged.c.inc     |  30 ++
>>>>   target/riscv/tcg/pmp.h                        |   3 +
>>>>   tests/tcg/riscv64/Makefile.softmmu-target     |  12 +
>>>>   tests/tcg/riscv64/smmpt-common.S              | 256 +++++++++++++
>>>>   tests/tcg/riscv64/test-smmpt.S                |  85 +++++
>>>>   tests/tcg/riscv64/test-smmpt34.S              |  97 +++++
>>>>   tests/tcg/riscv64/test-smmpt52.S              |  91 +++++
>>>>   tests/tcg/riscv64/test-smmpt64.S              |  98 +++++
>>>>   19 files changed, 1353 insertions(+), 19 deletions(-)
>>>>   create mode 100644 target/riscv/riscv_smmpt.c
>>>>   create mode 100644 target/riscv/riscv_smmpt.h
>>>>   create mode 100644 tests/tcg/riscv64/smmpt-common.S
>>>>   create mode 100644 tests/tcg/riscv64/test-smmpt.S
>>>>   create mode 100644 tests/tcg/riscv64/test-smmpt34.S
>>>>   create mode 100644 tests/tcg/riscv64/test-smmpt52.S
>>>>   create mode 100644 tests/tcg/riscv64/test-smmpt64.S
>>>>
>>>>
>>>> base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
>
Re: [PATCH v7 00/11] target/riscv: Implement Smsdid and Smmpt extension
Posted by Rahul Pathak via qemu development 2 days, 12 hours ago 
Hi Zhiwei,

A.
The mmpt probe in OpenSBI was deliberately set to detach
the mode and sdid write dependency.
Spec says mmpt=Bare then SDID and PPN must be 0
but it doesn't say whether this check is handled by hardware or software.
and upto the interpretation.

B.
Also, in your Qemu patch series, the mfence/minval encodings are different
from what they are suggested by the authors of SMMTT spec.
Please check the PR raised here in riscv-opcodes
https://github.com/riscv/riscv-opcodes/pull/389/

I understand that this is not fixed yet. However, in OpenSBI I chose to
use the same values as in the PR.

Though I haven't fully reviewed your patches,

If I change point A in OpenSBI and change point B in your Qemu,
I can make OpenSBI SMMPT work with your V7 Qemu SMMPT.

I agree with Daniel and appreciate that you agree to collaborate
and not duplicate efforts.

I can send a V2 of my OpenSBI series with the change of point A
and you can update the Qemu with at least the current proposal
encodings as defined in the PR in riscv-opcodes. This will
align both OpenSBI and QEMU SMSDID+SMMPT changes.

Thanks
Rahul

On Thu, Jul 23, 2026 at 9:17 AM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
>
> On 7/23/26 3:52 AM, Daniel Henrique Barboza wrote:
> >
> >
> > On 7/22/2026 12:11 AM, LIU Zhiwei wrote:
> >>
> >> On 7/22/26 8:56 AM, Alistair wrote:
> >>> On Wed, 2026-07-15 at 22:50 +0800, LIU Zhiwei wrote:
> >>>> This patch set introduces support for the RISC-V Smsdid and Smmpt
> >>>> (Supervisor Domain Identifier and Memory Protection Table) extensions
> >>>> v0.4.9(https://github.com/riscv/riscv-smmtt/releases/tag/v0.4.9).
> >>>> Smmpt provides a hardware mechanism for fine-grained memory
> >>>> protection,
> >>>> checked after address translation, which is particularly useful for
> >>>> supervisor-level sandboxing and security monitoring.
> >> Hi Alistair,
> >>> Can you include a link to the upstream submitted patches to use this
> >>> functionality
> >> Xiangyi is currently working on OpenSBI support for SMMPT, and we
> >> already have an internal implementation in place. We plan to upstream
> >> the OpenSBI support as soon as possible, and once that is done, I’ll
> >> be able to include a link here.
> >
> Hi Daniel
> > Please be aware that Rahul already sent OpenSBI patches for smmpt and
> > smsdid:
> >
> > [RFC PATCH 0/5] Add Smsdid and Smmpt supervisor domain protection
> > https://lists.infradead.org/pipermail/opensbi/2026-July/010235.html
> >
> > In fact, as I said in another thread [1], Rahul also has a QEMU
> > implementation of his own.
> > His OpenSBI patches works with his QEMU changes:
> >
> > https://github.com/pathakraul/qemu/tree/rpathak_smmpt_v1
> Thank you very much for pointing this out and for coordinating between
> us. I was not aware of Rahul's OpenSBI patches and QEMU implementation.
> >
> > But seems like his OpenSBI patches does *not* work with this QEMU patches,
> It seams probe_sdidlen in OpenSBI write a sdid to mmpt with bare mode.
> According to the specification, in bare mode, "The remaining fields in
> mmpt (SDID, PPN) must
> be set to zeros.
> >  but works
> > with his QEMU implementation.  Seems like there might be things to
> > improve in both
> > implementations.
> >
> > I asked him to not send his QEMU patches on top of yours because I'd
> > rather work in
> > collaboration on top of a single series, and I advise to not send
> > another OpenSBI support
> > for the same stuff in that mailing as well.
> >
> > IMO you and Rahul should sync up in both OpenSBI and QEMU bits to
> > avoid effort duplication
> > on both sides.
>
> I agree with your suggestion that it is better to avoid duplicated
> effort and collaborate on a single direction for both the QEMU and
> OpenSBI sides.
>
> Since the SMMPT v0.4.9 specification is already close to stabilization,
> and implementation work has already started in both OpenSBI and QEMU, I
> believe we should be able to converge quickly through collaboration and
> help move SMMPT upstream sooner.
>
> Xiangyi and I will continue to review Rahul's OpenSBI patches to
> understand the current differences and why they are not yet compatible
> with our QEMU series. I will also reach out to Rahul directly so that we
> can sync up and work toward a common implementation.
>
> Thanks again for the pointers.
>
> Best regards,
> Zhiwei
>
> >
> >
> > Cheers,
> > Daniel
> >
> >
> > [1]
> > https://lore.kernel.org/qemu-devel/2e2de5da-9eb0-4d56-b193-d8b06b7a3512@oss.qualcomm.com/
> >
> >
> >>
> >> Thanks,
> >> Zhiwei
> >>>
> >>> Alistair
> >>>
> >>>> The rfc patch set:
> >>>> https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html
> >>>>
> >>>> v6->v7:
> >>>>      The implementation is updated from the v0.3.4 specification to
> >>>>      v0.4.9. The main changes are:
> >>>>      1. Update the mmpt CSR number to 0x382 and msdcfg to 0x74E.
> >>>>      2. Update the mmpt register layout: the SDID and PPN field
> >>>> positions
> >>>>         changed and the RV64 PPN is now 44 bits.
> >>>>      3. Rework the MPTE format: the N (NAPOT) bit now lives at bit 2,
> >>>> the
> >>>>         non-leaf NAPOT form is removed, NAPOT leaf entries encode a
> >>>> single
> >>>>         XWR tuple plus a G granularity field, and non-NAPOT leaf
> >>>> entries
> >>>>         hold per-page XWR tuples.
> >>>>      4. Treat XWR=000 as "no access" and a non-leaf entry with N=1 as
> >>>> a
> >>>>         fault.
> >>>>      5. Enforce the Smmpt64 root-table PPN alignment (low 3 bits
> >>>> zero).
> >>>>      6. Rename the fence instructions mfence.spa/minval.spa to
> >>>>         mfence.pa/minval.pa.
> >>>>      7. Drop stale Reviewed-by tags on the substantially reworked
> >>>> patches.
> >>>>      8. Introduce the configurable "smmpt-sdidlen" CPU property.
> >>>>      9. Add disassembly support for the Smmpt.
> >>>>      10. Add bare-metal M-mode system tests.
> >>>>      11. Rebase to master.
> >>>>
> >>>> v5->v6:
> >>>>      1. Use explicitly bit fields extract instead of mpte_union_t.
> >>>>      2. Use the same exception behavior for MPT valiation as PMP
> >>>>         valiation.
> >>>>      3. Use PAGE_* instead of MPT_ACCESS_* as they have same value.
> >>>>      4. Use address_space_*_le instead of address_space_* for SMMPT.
> >>>>      5. Only print SMMPT address check log when SMMPT is enabled.
> >>>>      6. Add implied rule for SMMPT as it depends on SMSDID.
> >>>>      7. Rebase to master.
> >>>>
> >>>> v4->v5:
> >>>>      1. Rebase to master.
> >>>> v3->v4:
> >>>>      1. Add missing review tags.
> >>>> v2->v3:
> >>>>      1. Fix build error in patch 2.
> >>>>      2. Rebase to master.
> >>>>
> >>>> rfc->v2:
> >>>>      1. When ext_smmpt is false or BARE mode, make other fields in
> >>>> mmpt
> >>>>         CSR zero.
> >>>>      2. Add patch 5 to fix smrnmi ISA string order.
> >>>>      3. Fix patch 6 smmpt and smsdid ISA string order.
> >>>>      4. Make smmpt and smsdid experiment extensions.
> >>>>      5. Add review tags.
> >>>>
> >>>> LIU Zhiwei (11):
> >>>>    target/riscv: Add basic definitions and CSRs for SMMPT
> >>>>    target/riscv: Add smmpt-sdidlen property for the mmpt SDID field
> >>>>    target/riscv: Implement core SMMPT lookup logic
> >>>>    target/riscv: Integrate SMMPT checks into MMU and TLB fill
> >>>>    target/riscv: Implement SMMPT fence instructions
> >>>>    target/riscv: Fix smrnmi isa alphabetical order
> >>>>    target/riscv: Add disassembly for Smmpt instructions and CSRs
> >>>>    target/riscv: Enable SMMPT extension
> >>>>    target/riscv: Add system test for SMMPT extension
> >>>>    target/riscv: Add system tests for Smmpt52 and Smmpt64
> >>>>    target/riscv: Add system test for Smmpt34
> >>>>
> >>>>   disas/riscv.c                                 |   9 +-
> >>>>   target/riscv/cpu.c                            |  60 +++-
> >>>>   target/riscv/cpu.h                            |   8 +
> >>>>   target/riscv/cpu_bits.h                       |  27 ++
> >>>>   target/riscv/cpu_cfg_fields.h.inc             |   3 +
> >>>>   target/riscv/insn32.decode                    |   2 +
> >>>>   target/riscv/meson.build                      |   1 +
> >>>>   target/riscv/riscv_smmpt.c                    | 339
> >>>> ++++++++++++++++++
> >>>>   target/riscv/riscv_smmpt.h                    |  26 ++
> >>>>   target/riscv/tcg/cpu_helper.c                 | 119 +++++-
> >>>>   target/riscv/tcg/csr.c                        | 106 ++++++
> >>>>   .../tcg/insn_trans/trans_privileged.c.inc     |  30 ++
> >>>>   target/riscv/tcg/pmp.h                        |   3 +
> >>>>   tests/tcg/riscv64/Makefile.softmmu-target     |  12 +
> >>>>   tests/tcg/riscv64/smmpt-common.S              | 256 +++++++++++++
> >>>>   tests/tcg/riscv64/test-smmpt.S                |  85 +++++
> >>>>   tests/tcg/riscv64/test-smmpt34.S              |  97 +++++
> >>>>   tests/tcg/riscv64/test-smmpt52.S              |  91 +++++
> >>>>   tests/tcg/riscv64/test-smmpt64.S              |  98 +++++
> >>>>   19 files changed, 1353 insertions(+), 19 deletions(-)
> >>>>   create mode 100644 target/riscv/riscv_smmpt.c
> >>>>   create mode 100644 target/riscv/riscv_smmpt.h
> >>>>   create mode 100644 tests/tcg/riscv64/smmpt-common.S
> >>>>   create mode 100644 tests/tcg/riscv64/test-smmpt.S
> >>>>   create mode 100644 tests/tcg/riscv64/test-smmpt34.S
> >>>>   create mode 100644 tests/tcg/riscv64/test-smmpt52.S
> >>>>   create mode 100644 tests/tcg/riscv64/test-smmpt64.S
> >>>>
> >>>>
> >>>> base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
> >
>

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