Add disassembly support to the RISC-V disassembler for the machine CSRs
and fence instructions introduced by the Smmpt/Smsdid series:
- CSRs: mmpt (0x382), msdcfg (0x74e)
- Instructions: mfence.pa, minval.pa
Note that CSR 0x382 was previously mapped to the obsolete "mibase"
register from the removed base-and-bound draft; it is now reused by
Smmpt for mmpt.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
disas/riscv.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 7f1b262773..27770da097 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -990,6 +990,8 @@ typedef enum {
rv_op_cbo_flush = 958,
rv_op_cbo_zero = 959,
rv_op_mnret = 960,
+ rv_op_mfence_pa = 961,
+ rv_op_minval_pa = 962,
} rv_op;
/* register names */
@@ -2265,6 +2267,8 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "cbo.flush", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
{ "cbo.zero", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
{ "mnret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
+ { "mfence.pa", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
+ { "minval.pa", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
};
/* CSR names */
@@ -2356,7 +2360,7 @@ static const char *csr_name(int csrno)
case 0x0344: return "mip";
case 0x0380: return "mbase";
case 0x0381: return "mbound";
- case 0x0382: return "mibase";
+ case 0x0382: return "mmpt";
case 0x0383: return "mibound";
case 0x0384: return "mdbase";
case 0x0385: return "mdbound";
@@ -2440,6 +2444,7 @@ static const char *csr_name(int csrno)
case 0x03ed: return "pmpaddr61";
case 0x03ee: return "pmpaddr62";
case 0x03ef: return "pmpaddr63";
+ case 0x074e: return "msdcfg";
case 0x0780: return "mtohost";
case 0x0781: return "mfromhost";
case 0x0782: return "mreset";
@@ -4053,6 +4058,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 928: op = rv_op_wrs_sto; break;
}
break;
+ case 96: op = rv_op_minval_pa; break;
case 256:
switch ((inst >> 20) & 0b11111) {
case 2:
@@ -4089,6 +4095,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 576: op = rv_op_dret; break;
}
break;
+ case 2144: op = rv_op_mfence_pa; break;
}
break;
case 1: op = rv_op_csrrw; break;
--
2.43.0