[PATCH 0/9] hw/mips: add Octeon III EBB7304 support

Kirill A. Korinsky posted 9 patches 1 week, 5 days ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20260713112004.4956-1-kirill@korins.ky
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, "Philippe Mathieu-Daudé" <philmd@mailo.com>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <arikalo@gmail.com>
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[PATCH 0/9] hw/mips: add Octeon III EBB7304 support
Posted by Kirill A. Korinsky 1 week, 5 days ago
This series adds enough Cavium Octeon III CN73xx and EBB7304 board
support to boot a modern U-Boot EBB7304 image and OpenBSD/octeon; the
same machine also boots the U-Boot image from the Ubiquiti EdgeRouter
Infinity ER-8-XG recovery set. The model intentionally covers the
hardware exercised by these firmware and operating system paths.

The vendor recovery image reaches:

    Octeon ubnt_e1000(Failsafe)#

This is the expected command prompt of the recovery U-Boot environment;
"Failsafe" describes the recovery image and does not indicate an
emulation or boot failure.

The board model is based on Amir Mehmood's original Octeon host.patch;
the basic machine approach and several peripheral modelling ideas come
from that work. The implementation targets CN73xx hardware and the boot
paths above.

The prerequisite patches correct xHCI interrupt reassertion, use atomic
access for MIPS CP0 interrupt and timer state under MTTCG, fix MIPS64
segment access checks and tlbwr replacement semantics, then add Octeon
CP0 state, the CN73xx CPU model, PageMask handling, and unaligned
accesses. The final patch adds the EBB7304 board and its functional
test.

The machine currently models:

* the EBB7304 RAM layout, boot flash aliases, and boot-local RAM;
* CN73xx CPUs, Octeon CP0 state, CVMSEG, and configurable clocks;
* legacy CIU and CIU3 interrupt routing, mailboxes, and secondary CPU
  release;
* UART, TWSI and SPD, LMC state, fuses, RNG, POW, and the firmware
  probes required during initialization;
* two DWC3 controllers and a minimal PCIe host suitable for PCI e1000
  and USB storage.

With system U-Boot, the functional test enumerates PCI, obtains a DHCP
lease, downloads bsd.rd through user mode TFTP, and boots the
OpenBSD/octeon 7.9 installer with four CPUs.

The series was tested with:

    ninja -C build qemu-system-mips64
    gmake -C build check-qtest-mips64
    gmake -C build check-functional-mips64

The qtest suite reported 14 passes, 2 empty suite skips, and no
failures. The functional suite reported 7 passes, 2 expected skips,
and no failures; its Octeon case reached the OpenBSD installer prompt.

Before the final rebase, the machine also completed a GCC build inside
OpenBSD/octeon using:

    -m 16G -smp 4 -accel tcg,thread=multi

That workload ran for several days to build gcc-16.1.0 inside.

Known limitations are:

* native Octeon Ethernet and the complete MMC path are not modelled;
  the OpenBSD test uses PCI e1000;
* direct kernel boot through -kernel is not implemented;
* board CSR and interrupt state has no VMState description, therefore
  migration and savevm correctness is not established.

The first patch is a generic xHCI fix required for reliable USB
interrupt delivery on this machine. Patches 2 through 4 contain generic
MIPS fixes; patches 5 through 8 add Octeon target support; patch 9 adds
the EBB7304 machine and functional test.

The series is based ona759542a2c62f0fd3b65f5a66ad9868201014669.

Patch layout:

  1. hw/usb/xhci: reassert pending busy interrupts
  2. target/mips: make CP0 interrupt state atomic
  3. target/mips: fix MIPS64 segment access checks
  4. target/mips: drop hidden TLB shadowing for tlbwr
  5. target/mips: add Octeon CP0 register state
  6. target/mips: add Octeon CN73xx CPU model
  7. target/mips: accept Octeon PageMask encodings
  8. target/mips: allow Octeon unaligned accesses
  9. hw/mips: add Octeon III EBB7304 machine