This series adds enough Cavium Octeon III CN73xx and EBB7304 board
support for upstream U-Boot 2026.04 to boot OpenBSD/octeon from USB
storage or through PCI e1000 and TFTP; the same machine also reaches
the prompt of the vendor U-Boot 2013.07 image from the Ubiquiti
EdgeRouter Infinity ER-8-XG recovery set. The model intentionally
covers the hardware exercised by these firmware and operating system
paths.

The vendor recovery image is U-Boot 2013.07, UBNT build
e1000_002_ef3a9; it reaches:

    Octeon ubnt_e1000(Failsafe)#

This is the expected command prompt of the recovery U-Boot environment;
"Failsafe" describes the recovery image and does not indicate an
emulation or boot failure.

Early Octeon investigation used Amir Mehmood's original Octeon
host.patch as a behavioral reference; the basic machine approach and
several hardware model ideas come from that work. No code from that
patch remains in this implementation.

The series starts with three generic MIPS correctness fixes for MTTCG
interrupt state, MIPS64 segment checks, and architectural tlbwr
replacement semantics. It then adds Octeon CP0 state, the CN73xx CPU
model, PageMask handling, and unaligned accesses before introducing an
empty EBB7304 machine. The remaining patches add the machine state and
peripherals incrementally, followed by the functional test.

The machine currently models:

* the EBB7304 RAM layout, boot flash aliases, and boot-local RAM;
* CN73xx CPUs, Octeon CP0 state, CVMSEG, and configurable clocks;
* reset control, legacy CIU and CIU3 interrupt routing, mailboxes, and
  secondary CPU release;
* UART, two TWSI controllers, synthesized DDR4 SPD, four LMC register
  banks, fuses, RNG, POW, and the firmware probes used during platform
  initialization;
* the EMM registers needed for firmware MMC initialization;
* two UCTL-wrapped DWC3 controllers, sufficient for U-Boot USB storage;
* a minimal PCIe host bridge, sufficient for a PCI e1000 device.

The functional test starts upstream U-Boot with four CPUs, enumerates
PCI, obtains a DHCP lease, downloads bsd.rd through user mode TFTP, and
boots the OpenBSD/octeon 7.9 installer.

The OpenBSD boot and USB stress testing used Philippe Mathieu-Daudé's
suggested xHCI change which clears ERDP_EHB after a successful interrupt
callback: https://marc.info/?l=qemu-devel&m=178402329968274&w=2

That one-line change is kept in the development branch and is not part
of this series. With it applied, a full cvs -Q checkout of the OpenBSD
ports tree to USB storage completed without a stall.

Each submitted commit was built in sequence and given the meaningful
smoke test available at that point. The final tree was tested with:

    ninja -C build qemu-system-mips64
    gmake -C build check-qtest-mips64
    gmake -C build check-functional-mips64

The qtest suite reported 14 passes, 2 empty suite skips, and no
failures. The functional suite reported 7 passes, 2 expected skips,
and no failures; its Octeon case reached the OpenBSD installer prompt.

Before the final rebase, the machine also completed a GCC build inside
OpenBSD/octeon using:

    -m 16G -smp 4 -accel tcg,thread=multi

That workload ran for several days.

Known limitations are:

* native Octeon Ethernet is not modelled; the OpenBSD test uses PCI
  e1000;
* EMM implements the firmware initialization path, not a complete MMC
  data path;
* direct kernel boot through -kernel is not implemented;
* the newly modelled board and peripheral state lacks VMState
  descriptions; migration and savevm are not expected to preserve the
  complete machine state.

Changes since v1:

* split the single machine patch into the empty machine, CPU and memory,
  controller, peripheral, wiring, and test changes;
* moved the TWSI, USB, and PCI host models to hw/i2c, hw/usb, and
  hw/pci-bridge respectively;
* replaced DEVICE_NATIVE_ENDIAN with explicit MMIO endianness;
* moved mutable peripheral state into its owning device and converted
  reset handling to the Resettable interface;
* dropped the xHCI interrupt reassertion patch from the submitted
  series.

Patches 1 through 3 are generic MIPS correctness fixes. Patches 4
through 7 add Octeon target support. Patch 8 adds the empty machine;
patches 9 through 24 add CPUs, memory, controllers, and peripherals.
Patch 25 adds the functional test.

The series is based on
499039798cdad7d86b787fec0eaf1da4151c0f05, which already contains the
Octeon COP2 implementation.

Patch layout:

  1. target/mips: make CP0 interrupt state atomic
  2. target/mips: fix MIPS64 segment access checks
  3. target/mips: drop hidden TLB shadowing for tlbwr
  4. target/mips: add Octeon CP0 register state
  5. target/mips: add Octeon CN73xx CPU model
  6. target/mips: accept Octeon PageMask encodings
  7. target/mips: allow Octeon unaligned accesses
  8. hw/mips: add empty Octeon III machine
  9. hw/mips: add Octeon CPUs and boot memory
 10. hw/mips: add Octeon reset controller
 11. hw/mips: add Octeon CIU3 CPU control
 12. hw/mips: add Octeon CIU3 interrupt routing
 13. hw/mips: add Octeon legacy CIU
 14. hw/mips: add Octeon CSR window
 15. hw/mips: expose Octeon reset CSRs
 16. hw/mips: add Octeon MIO boot support
 17. hw/mips: wire the Octeon UART
 18. hw/i2c: add Octeon TWSI controller
 19. hw/mips: add Octeon EMM controller
 20. hw/mips: add Octeon LMC controllers
 21. hw/mips: add Octeon boot support registers
 22. hw/usb: add Octeon USB controller
 23. hw/pci-bridge: add Octeon PCI host bridge
 24. hw/pci-bridge: add Octeon PCI memory window
 25. tests/functional: test Octeon III boot