tcg/x86_64: declare MO_ATOM_WITHIN16 host atomicity support

[PATCH] tcg/x86_64: declare MO_ATOM_WITHIN16 host atomicity support

Posted by Andrew Jones 2 weeks, 4 days ago

Just like aarch64's prepare_host_addr(), x86_64 should use
MO_ATOM_WITHIN16 for the memop when it's capable. Unlike aarch64,
which needs to check a CPU feature, x86 has been capable since P6
family processors and newer (see Intel SDM Vol. 3 §11.1.1).

Since a 16-byte aligned region always fits within a 16-byte multiple
sized cache line (x86_64 implementations always have cache lines of
at least 64 bytes), then this enables riscv cpu models with Zama16b
to use the fast path, just as cpu models without Zama16b do.

Cc: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
---
 tcg/x86_64/tcg-target.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc
index 92251f832738..99b6559eed88 100644
--- a/tcg/x86_64/tcg-target.c.inc
+++ b/tcg/x86_64/tcg-target.c.inc
@@ -1934,7 +1934,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
         *h = x86_guest_base;
     }
     h->base = addr;
-    h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
+    h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_WITHIN16, s_bits == MO_128);
     a_mask = (1 << h->aa.align) - 1;
 
     if (tcg_use_softmmu) {
-- 
2.43.0

Re: [PATCH] tcg/x86_64: declare MO_ATOM_WITHIN16 host atomicity support

Posted by Richard Henderson 2 weeks, 4 days ago

On 7/7/26 05:28, Andrew Jones wrote:
> Just like aarch64's prepare_host_addr(), x86_64 should use
> MO_ATOM_WITHIN16 for the memop when it's capable. Unlike aarch64,
> which needs to check a CPU feature, x86 has been capable since P6
> family processors and newer (see Intel SDM Vol. 3 §11.1.1).
> 
> Since a 16-byte aligned region always fits within a 16-byte multiple
> sized cache line (x86_64 implementations always have cache lines of
> at least 64 bytes), then this enables riscv cpu models with Zama16b
> to use the fast path, just as cpu models without Zama16b do.
> 
> Cc: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
> ---
>   tcg/x86_64/tcg-target.c.inc | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc
> index 92251f832738..99b6559eed88 100644
> --- a/tcg/x86_64/tcg-target.c.inc
> +++ b/tcg/x86_64/tcg-target.c.inc
> @@ -1934,7 +1934,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
>           *h = x86_guest_base;
>       }
>       h->base = addr;
> -    h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
> +    h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_WITHIN16, s_bits == MO_128);
>       a_mask = (1 << h->aa.align) - 1;
>   
>       if (tcg_use_softmmu) {

You should update both uses of atom_and_align_for_opc.

With that,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH] tcg/x86_64: declare MO_ATOM_WITHIN16 host atomicity support

Posted by Richard Henderson 2 weeks, 4 days ago

On 7/7/26 10:46, Richard Henderson wrote:
> On 7/7/26 05:28, Andrew Jones wrote:
>> Just like aarch64's prepare_host_addr(), x86_64 should use
>> MO_ATOM_WITHIN16 for the memop when it's capable. Unlike aarch64,
>> which needs to check a CPU feature, x86 has been capable since P6
>> family processors and newer (see Intel SDM Vol. 3 §11.1.1).
>>
>> Since a 16-byte aligned region always fits within a 16-byte multiple
>> sized cache line (x86_64 implementations always have cache lines of
>> at least 64 bytes), then this enables riscv cpu models with Zama16b
>> to use the fast path, just as cpu models without Zama16b do.
>>
>> Cc: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
>> ---
>>   tcg/x86_64/tcg-target.c.inc | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc
>> index 92251f832738..99b6559eed88 100644
>> --- a/tcg/x86_64/tcg-target.c.inc
>> +++ b/tcg/x86_64/tcg-target.c.inc
>> @@ -1934,7 +1934,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, 
>> HostAddress *h,
>>           *h = x86_guest_base;
>>       }
>>       h->base = addr;
>> -    h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
>> +    h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_WITHIN16, s_bits == MO_128);
>>       a_mask = (1 << h->aa.align) - 1;
>>       if (tcg_use_softmmu) {
> 
> You should update both uses of atom_and_align_for_opc.
> 
> With that,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

I'll update this myself and queue for today's PR.

r~