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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=andrew.jones@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1783427335957158500 Just like aarch64's prepare_host_addr(), x86_64 should use MO_ATOM_WITHIN16 for the memop when it's capable. Unlike aarch64, which needs to check a CPU feature, x86 has been capable since P6 family processors and newer (see Intel SDM Vol. 3 =C2=A711.1.1). Since a 16-byte aligned region always fits within a 16-byte multiple sized cache line (x86_64 implementations always have cache lines of at least 64 bytes), then this enables riscv cpu models with Zama16b to use the fast path, just as cpu models without Zama16b do. Cc: LIU Zhiwei Signed-off-by: Andrew Jones Reviewed-by: Richard Henderson --- tcg/x86_64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/x86_64/tcg-target.c.inc b/tcg/x86_64/tcg-target.c.inc index 92251f832738..99b6559eed88 100644 --- a/tcg/x86_64/tcg-target.c.inc +++ b/tcg/x86_64/tcg-target.c.inc @@ -1934,7 +1934,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, *h =3D x86_guest_base; } h->base =3D addr; - h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits =3D= =3D MO_128); + h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_WITHIN16, s_bits =3D= =3D MO_128); a_mask =3D (1 << h->aa.align) - 1; =20 if (tcg_use_softmmu) { --=20 2.43.0