[v1] Implement FEAT_FPRCVT in cpu_max

[PATCH 0/3] Implement FEAT_FPRCVT in cpu_max

Jim MacArthur posted 3 patches 1 month, 1 week ago

Diff against v2 v3
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git fetch https://github.com/patchew-project/qemu tags/patchew/20260618-jmac-fprcvt-v1-0-1b4475bacf51@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

There is a newer version of this series

target/arm/tcg/a64.decode         |   15 +
target/arm/tcg/cpu64.c            |    1 +
target/arm/tcg/translate-a64.c    |   66 +
tests/tcg/aarch64/Makefile.target |   25 +-
tests/tcg/aarch64/fcvt-fprcvt.ref | 3331 +++++++++++++++++++++++++++++++++++++
tests/tcg/arm/fcvt.c              |   26 +
6 files changed, 3458 insertions(+), 6 deletions(-)

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[PATCH 0/3] Implement FEAT_FPRCVT in cpu_max

Posted by Jim MacArthur 1 month, 1 week ago

This introduces new forms of FCVTXX instructions which convert floating
point to integer but place the results in SIMD & FP registers, and
forms of the [SU]CVTF instructions which convert from integer to FP
with a source in SIMD & FP registers. The logic for conversion and test
values are otherwise the same as the versions which use general-purpose
registers.

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
Jim MacArthur (3):
      target/arm/tcg: Implement new instructions for FPRCVT
      tests/tcg/arm: Tests for new FPRCVT instructions
      target/arm/tcg/cpu64.c: Add FEAT_FPRCVT to cpu_max

 target/arm/tcg/a64.decode         |   15 +
 target/arm/tcg/cpu64.c            |    1 +
 target/arm/tcg/translate-a64.c    |   66 +
 tests/tcg/aarch64/Makefile.target |   25 +-
 tests/tcg/aarch64/fcvt-fprcvt.ref | 3331 +++++++++++++++++++++++++++++++++++++
 tests/tcg/arm/fcvt.c              |   26 +
 6 files changed, 3458 insertions(+), 6 deletions(-)
---
base-commit: b0df6e2f2c6c45df8d4d286933799c623e124d98
change-id: 20260618-jmac-fprcvt-1554d4c80bc8

Best regards,
-- 
Jim MacArthur <jim.macarthur@linaro.org>