[v3] Implement FEAT_FPRCVT in cpu_max

[PATCH v3 0/6] Implement FEAT_FPRCVT in cpu_max

Jim MacArthur posted 6 patches 3 weeks, 4 days ago

Diff against v1 v2
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260630-jmac-fprcvt-v3-0-f4840d5e0a7f@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>, Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>, Laurent Vivier <laurent@vivier.eu>, Helge Deller <deller@gmx.de>

docs/system/arm/emulation.rst     |   1 +
linux-user/aarch64/elfload.c      |   1 +
target/arm/cpu-features.h         |   5 ++
target/arm/tcg/a64.decode         |  15 ++++++
target/arm/tcg/cpu64.c            |   1 +
target/arm/tcg/translate-a64.c    | 101 +++++++++++++++++++++++++++-----------
tests/tcg/aarch64/Makefile.target |  14 +++++-
tests/tcg/arm/fcvt.c              |   7 +++
8 files changed, 115 insertions(+), 30 deletions(-)

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[PATCH v3 0/6] Implement FEAT_FPRCVT in cpu_max

Posted by Jim MacArthur 3 weeks, 4 days ago

This introduces new forms of FCVTXX instructions which convert floating
point to integer but place the results in SIMD & FP registers, and
forms of the [SU]CVTF instructions which convert from integer to FP
with a source in SIMD & FP registers. The logic for conversion and test
values are otherwise the same as the versions which use general-purpose
registers.

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
Changes in v3:
- do_fcvt_simd rolled into do_fcvt_f.
- Test assembler rewriten to avoid unintended clobber
- Link to v2: https://lore.kernel.org/qemu-devel/20260624-jmac-fprcvt-v2-0-dc6cf8e512b6@linaro.org

Changes in v2:
- New instructions are gated on FPRCVT flag
- do_cvtf_simd removed; changes folded into do_cvtf_f
- Some vector forms of instructions are now allowed in streaming mode (new patch)
- Tests restructured to avoid the duplication of fcvt.ref
- docs/system/arm/emulation.rst updated to indicate FPRCVT support
- linux-user/aarch64/elfload.c now reports FPRCVT
- Link to v1: https://lore.kernel.org/qemu-devel/20260618-jmac-fprcvt-v1-0-1b4475bacf51@linaro.org

---
Jim MacArthur (6):
      target/arm/tcg: Implement new instructions for FPRCVT
      target/arm/tcg: Allow vector FP conversions with FPRCVT
      target/arm/tcg/cpu64.c: Add FEAT_FPRCVT to cpu_max
      linux-user/aarch64/elfload.c: Add FPRCVT
      docs/system/arm: Add FEAT_FPRCVT to A-profile support
      tests/tcg/arm: Tests for new FPRCVT instructions

 docs/system/arm/emulation.rst     |   1 +
 linux-user/aarch64/elfload.c      |   1 +
 target/arm/cpu-features.h         |   5 ++
 target/arm/tcg/a64.decode         |  15 ++++++
 target/arm/tcg/cpu64.c            |   1 +
 target/arm/tcg/translate-a64.c    | 101 +++++++++++++++++++++++++++-----------
 tests/tcg/aarch64/Makefile.target |  14 +++++-
 tests/tcg/arm/fcvt.c              |   7 +++
 8 files changed, 115 insertions(+), 30 deletions(-)
---
base-commit: 30e8a06b64aa58a3990ba39cb5d09531e7d265e0
change-id: 20260618-jmac-fprcvt-1554d4c80bc8

Best regards,
-- 
Jim MacArthur <jim.macarthur@linaro.org>

Re: [PATCH v3 0/6] Implement FEAT_FPRCVT in cpu_max

Posted by Peter Maydell 3 weeks, 2 days ago

On Tue, 30 Jun 2026 at 14:17, Jim MacArthur <jim.macarthur@linaro.org> wrote:
>
> This introduces new forms of FCVTXX instructions which convert floating
> point to integer but place the results in SIMD & FP registers, and
> forms of the [SU]CVTF instructions which convert from integer to FP
> with a source in SIMD & FP registers. The logic for conversion and test
> values are otherwise the same as the versions which use general-purpose
> registers.
>
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>



Applied to target-arm.next, thanks.

-- PMM