This patchset has some fixes for minor GICv5 issues that I noticed
while I've been working on the GICv5 virtualization support:
 - 2 actual (but minor) bugs
 - the GICv5 spec now has a final URL we can cite
 - a minor cleanup of how we say "no pending interrupt"
 - the ICC_HAPR_EL1 register is removed in the latest version
   of the spec, so we can drop it from our implementation

thanks
-- PMM

Peter Maydell (5):
  arm/gicv5: Add URL to GICv5 specification
  target/arm: GICv5 cpuif: Recalculate IRQ/FIQ on ICC_PCR_EL1 write
  target/arm: GICv5 cpuif: Tag ICC_PPI_PRIORITYR<n> regs as
    ARM_CP_NO_RAW
  target/arm: GICv5 cpuif: Remove ICC_HAPR_EL1
  hw/intc/gicv5: Define and use GICV5_PENDING_IRQ_NONE

 hw/intc/arm_gicv5.c               | 11 +++++++----
 include/hw/intc/arm_gicv5_types.h |  4 ++++
 target/arm/tcg/gicv5-cpuif.c      | 29 ++++++++++-------------------
 3 files changed, 21 insertions(+), 23 deletions(-)

-- 
2.43.0

On 6/15/26 03:50, Peter Maydell wrote:
> Peter Maydell (5):
>    arm/gicv5: Add URL to GICv5 specification
>    target/arm: GICv5 cpuif: Recalculate IRQ/FIQ on ICC_PCR_EL1 write
>    target/arm: GICv5 cpuif: Tag ICC_PPI_PRIORITYR<n> regs as
>      ARM_CP_NO_RAW
>    target/arm: GICv5 cpuif: Remove ICC_HAPR_EL1
>    hw/intc/gicv5: Define and use GICV5_PENDING_IRQ_NONE



Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~