[v3] target/riscv: Fix no-TCG build

[PATCH v3 0/6] target/riscv: Fix no-TCG build

Zephyr Li posted 6 patches 5 days, 16 hours ago

Diff against v1 v2
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260602091753.3209261-1-fritchleybohrer@gmail.com

Maintainers: "Alex Bennée" <alex.bennee@linaro.org>, Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>

.gitlab-ci.d/crossbuilds.yml |   8 +
target/riscv/cpu-validate.c  | 630 ++++++++++++++++++++++++++++++++++
target/riscv/cpu.c           |  13 +-
target/riscv/cpu.h           |   7 -
target/riscv/cpu_helper.c    |  53 +++
target/riscv/csr.c           |  12 +-
target/riscv/debug.c         |   1 +
target/riscv/fpu_helper.c    |  27 --
target/riscv/internals.h     |  26 ++
target/riscv/meson.build     |  10 +-
target/riscv/op_helper.c     |  15 -
target/riscv/tcg/tcg-cpu.c   | 637 ++---------------------------------
target/riscv/tcg/tcg-cpu.h   |   1 -
target/riscv/zce_helper.c    |   1 +
14 files changed, 769 insertions(+), 672 deletions(-)
create mode 100644 target/riscv/cpu-validate.c

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[PATCH v3 0/6] target/riscv: Fix no-TCG build

Posted by Zephyr Li 5 days, 16 hours ago

This series fixes the riscv64-softmmu --disable-tcg build by keeping
TCG-only code out of no-TCG builds while preserving common RISC-V CPU
helpers for non-TCG configurations.

Compared with v2, this version replaces the no-TCG stub for
riscv_cpu_validate_set_extensions() with a common cpu-validate.c split.
The validator is used by common CSR code and should not live in TCG-only
code.

Changes in v3:
- Replace the no-TCG stub with a new cpu-validate.c common source file.
- Move common RISC-V extension validation and user-option tracking out of
  target/riscv/tcg/tcg-cpu.c.
- Move fflags and exception helpers out of TCG-only helper files.
- Reject x-misa-w outside TCG.
- Build RISC-V TCG-only sources only when CONFIG_TCG is enabled.
- Add GitLab CI coverage for riscv64 KVM-only --disable-tcg builds.

Testing:
- ../configure --target-list=riscv64-softmmu --enable-kvm --disable-tcg \
      --enable-debug
  ninja

- ../configure --target-list=riscv64-softmmu,riscv64-linux-user \
      --enable-debug
  ninja

- In the no-TCG build:
  qemu-system-riscv64 -M virt,accel=qtest -cpu rv64,x-misa-w=true \
      -nographic -S
  reports "x-misa-w requires TCG".

- In the TCG build:
  qemu-system-riscv64 -M virt -accel tcg -cpu rv64,x-misa-w=true \
      -nographic -S
  starts without reporting "x-misa-w requires TCG".

Zephyr Li (6):
  target/riscv: move extension validation out of TCG-only code
  target/riscv: move fflags helpers to common code
  target/riscv: move riscv_raise_exception() out of op_helper.c
  target/riscv: reject x-misa-w outside TCG
  target/riscv: build TCG-only sources only with TCG
  gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job

 .gitlab-ci.d/crossbuilds.yml |   8 +
 target/riscv/cpu-validate.c  | 630 ++++++++++++++++++++++++++++++++++
 target/riscv/cpu.c           |  13 +-
 target/riscv/cpu.h           |   7 -
 target/riscv/cpu_helper.c    |  53 +++
 target/riscv/csr.c           |  12 +-
 target/riscv/debug.c         |   1 +
 target/riscv/fpu_helper.c    |  27 --
 target/riscv/internals.h     |  26 ++
 target/riscv/meson.build     |  10 +-
 target/riscv/op_helper.c     |  15 -
 target/riscv/tcg/tcg-cpu.c   | 637 ++---------------------------------
 target/riscv/tcg/tcg-cpu.h   |   1 -
 target/riscv/zce_helper.c    |   1 +
 14 files changed, 769 insertions(+), 672 deletions(-)
 create mode 100644 target/riscv/cpu-validate.c


base-commit: 5611a9268dae7b7ff99d478ed134052a9fc7e9f7
-- 
2.43.0