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However, it currently lives in target/riscv/tcg/tcg-cpu.c, which is not built when TCG is disabled. Move the extension validation code and its user-option tracking helpers to a new cpu-validate.c file. Keep TCG-specific finalize and TB state handling in tcg-cpu.c, and expose the validator through internals.h for target/riscv internal users. Keep riscv_cpu_validate_misa_priv() and riscv_cpu_update_cfg() as separate internal helpers so TCG feature finalization preserves its original order and CSR write_misa() continues to run only extension consistency checks. The move also gives the helpers used by tcg-cpu.c a riscv_cpu_ prefix and adds lazy initialization/NULL guards for the user-option hash tables, so the validator can be linked from non-TCG builds without relying on TCG CPU instance initialization. Signed-off-by: Zephyr Li --- target/riscv/cpu-validate.c | 630 +++++++++++++++++++++++++++++++++++ target/riscv/csr.c | 1 - target/riscv/internals.h | 19 ++ target/riscv/meson.build | 1 + target/riscv/tcg/tcg-cpu.c | 637 ++---------------------------------- target/riscv/tcg/tcg-cpu.h | 1 - 6 files changed, 672 insertions(+), 617 deletions(-) create mode 100644 target/riscv/cpu-validate.c diff --git a/target/riscv/cpu-validate.c b/target/riscv/cpu-validate.c new file mode 100644 index 0000000000..2a92c94cdc --- /dev/null +++ b/target/riscv/cpu-validate.c @@ -0,0 +1,630 @@ +/* + * RISC-V CPU extension validation + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "qapi/error.h" +#include "qemu/error-report.h" + +/* Hash that stores user set extensions */ +static GHashTable *multi_ext_user_opts; +static GHashTable *misa_ext_user_opts; + +void riscv_cpu_ext_user_opts_init(void) +{ + g_clear_pointer(&multi_ext_user_opts, g_hash_table_unref); + g_clear_pointer(&misa_ext_user_opts, g_hash_table_unref); + + multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); +} + +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +{ + if (!multi_ext_user_opts) { + return false; + } + + return g_hash_table_contains(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset)); +} + +bool riscv_cpu_misa_ext_is_user_set(uint32_t misa_bit) +{ + if (!misa_ext_user_opts) { + return false; + } + + return g_hash_table_contains(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit)); +} + +void riscv_cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) +{ + if (!multi_ext_user_opts) { + riscv_cpu_ext_user_opts_init(); + } + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset), + (gpointer)value); +} + +void riscv_cpu_misa_ext_add_user_opt(uint32_t bit, bool value) +{ + if (!misa_ext_user_opts) { + riscv_cpu_ext_user_opts_init(); + } + + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(bit), + (gpointer)value); +} + +void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, + bool enabled) +{ + CPURISCVState *env =3D &cpu->env; + + if (enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } +} + +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +{ + const RISCVIsaExtData *edata; + + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset !=3D ext_offset) { + continue; + } + + return edata->min_version; + } + + g_assert_not_reached(); +} + +const char *riscv_cpu_cfg_ext_get_name(uint32_t ext_offset) +{ + const RISCVIsaExtData *edata; + + for (edata =3D isa_edata_arr; edata->name !=3D NULL; edata++) { + if (edata->ext_enable_offset =3D=3D ext_offset) { + return edata->name; + } + } + + g_assert_not_reached(); +} + +void riscv_cpu_bump_multi_ext_priv_ver(CPURISCVState *env, + uint32_t ext_offset) +{ + int ext_priv_ver; + + if (env->priv_ver =3D=3D PRIV_VERSION_LATEST) { + return; + } + + ext_priv_ver =3D cpu_cfg_ext_get_min_version(ext_offset); + + if (env->priv_ver < ext_priv_ver) { + /* + * Note: the 'priv_spec' command line option, if present, + * will take precedence over this priv_ver bump. + */ + env->priv_ver =3D ext_priv_ver; + } +} + +void riscv_cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, + bool value) +{ + CPURISCVState *env =3D &cpu->env; + bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); + int min_version; + + if (prev_val =3D=3D value) { + return; + } + + if (cpu_cfg_ext_is_user_set(ext_offset)) { + return; + } + + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { + /* Do not enable it if priv_ver is older than min_version */ + min_version =3D cpu_cfg_ext_get_min_version(ext_offset); + if (env->priv_ver < min_version) { + return; + } + } + + isa_ext_update_enabled(cpu, ext_offset, value); +} + +void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) +{ + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { + error_setg(errp, "H extension requires priv spec 1.12.0"); + return; + } +} + +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + uint32_t min_vlen; + uint32_t vlen =3D cfg->vlenb << 3; + + if (riscv_has_ext(env, RVV)) { + min_vlen =3D 128; + } else if (cfg->ext_zve64x) { + min_vlen =3D 64; + } else if (cfg->ext_zve32x) { + min_vlen =3D 32; + } else { + return; + } + + if (vlen > RV_VLEN_MAX || vlen < min_vlen) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [%d, %d]", min_vlen, RV_VLEN_MAX); + return; + } + + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + + if (vlen < cfg->elen) { + error_setg(errp, "Vector extension implementation requires VLEN " + "to be greater than or equal to ELEN"); + return; + } +} + +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + const RISCVIsaExtData *edata; + + /* Force disable extensions if priv spec version does not match */ + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && + (env->priv_ver < edata->min_version)) { + /* + * These two extensions are always enabled as they were suppor= ted + * by QEMU before they were added as extensions in the ISA. + */ + if (!strcmp(edata->name, "zicntr") || + !strcmp(edata->name, "zihpm")) { + continue; + } + + /* + * cpu.debug =3D true is marked as 'sdtrig', priv spec 1.12. + * Skip this warning since existing CPUs with older priv + * spec and debug =3D true will be impacted. + */ + if (!strcmp(edata->name, "sdtrig")) { + continue; + } + + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x%" PRIx64 + " because privilege spec version does not match", + edata->name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + edata->name); +#endif + } + } +} + +void riscv_cpu_update_cfg(RISCVCPU *cpu) +{ + if (cpu->env.priv_ver >=3D PRIV_VERSION_1_11_0) { + cpu->cfg.has_priv_1_11 =3D true; + } + + if (cpu->env.priv_ver >=3D PRIV_VERSION_1_12_0) { + cpu->cfg.has_priv_1_12 =3D true; + } + + if (cpu->env.priv_ver >=3D PRIV_VERSION_1_13_0) { + cpu->cfg.has_priv_1_13 =3D true; + } + + /* zic64b is 1.12 or later */ + cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && + cpu->cfg.cbop_blocksize =3D=3D 64 && + cpu->cfg.cboz_blocksize =3D=3D 64 && + cpu->cfg.has_priv_1_12; + + cpu->cfg.ext_ssstateen =3D cpu->cfg.ext_smstateen; + + cpu->cfg.ext_sha =3D riscv_has_ext(&cpu->env, RVH) && + cpu->cfg.ext_ssstateen; + + cpu->cfg.ext_ziccrse =3D cpu->cfg.has_priv_1_11; +} + +static void riscv_cpu_validate_g(RISCVCPU *cpu) +{ + const char *warn_msg =3D "RVG mandates disabled extension %s"; + uint32_t g_misa_bits[] =3D {RVI, RVM, RVA, RVF, RVD}; + bool send_warn =3D riscv_cpu_misa_ext_is_user_set(RVG); + + for (int i =3D 0; i < ARRAY_SIZE(g_misa_bits); i++) { + uint32_t bit =3D g_misa_bits[i]; + + if (riscv_has_ext(&cpu->env, bit)) { + continue; + } + + if (!riscv_cpu_misa_ext_is_user_set(bit)) { + riscv_cpu_write_misa_bit(cpu, bit, true); + continue; + } + + if (send_warn) { + warn_report(warn_msg, riscv_get_misa_ext_name(bit)); + } + } + + if (!cpu->cfg.ext_zicsr) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { + cpu->cfg.ext_zicsr =3D true; + } else if (send_warn) { + warn_report(warn_msg, "zicsr"); + } + } + + if (!cpu->cfg.ext_zifencei) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { + cpu->cfg.ext_zifencei =3D true; + } else if (send_warn) { + warn_report(warn_msg, "zifencei"); + } + } +} + +static void riscv_cpu_validate_b(RISCVCPU *cpu) +{ + const char *warn_msg =3D "RVB mandates disabled extension %s"; + + if (!cpu->cfg.ext_zba) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { + cpu->cfg.ext_zba =3D true; + } else { + warn_report(warn_msg, "zba"); + } + } + + if (!cpu->cfg.ext_zbb) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { + cpu->cfg.ext_zbb =3D true; + } else { + warn_report(warn_msg, "zbb"); + } + } + + if (!cpu->cfg.ext_zbs) { + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { + cpu->cfg.ext_zbs =3D true; + } else { + warn_report(warn_msg, "zbs"); + } + } +} + +/* + * Check consistency between chosen extensions while setting + * cpu->cfg accordingly. + */ +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; + + if (riscv_has_ext(env, RVG)) { + riscv_cpu_validate_g(cpu); + } + + if (riscv_has_ext(env, RVB)) { + riscv_cpu_validate_b(cpu); + } + + if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers= "); + return; + } + + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { + error_setg(errp, "Zacas extension requires A extension"); + return; + } + + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + + if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfa extension requires F extension"); + return; + } + + if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfbfmin extension depends on F extension"); + return; + } + + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { + error_setg(errp, "D extension requires F extension"); + return; + } + + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + /* The Zve64d extension depends on the Zve64f extension */ + if (cpu->cfg.ext_zve64d) { + if (!riscv_has_ext(env, RVD)) { + error_setg(errp, "Zve64d/V extensions require D extension"); + return; + } + } + + /* The Zve32f extension depends on the Zve32x extension */ + if (cpu->cfg.ext_zve32f) { + if (!riscv_has_ext(env, RVF)) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension= "); + return; + } + } + + if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension= "); + return; + } + + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { + error_setg(errp, "Zvfh extensions requires Zfhmin extension"); + return; + } + + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); + return; + } + + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension= "); + return; + } + + if (cpu->cfg.ext_zvfbfa) { + if (!cpu->cfg.ext_zve32f || !cpu->cfg.ext_zfbfmin) { + error_setg(errp, "Zvfbfa extension requires Zve32f extension " + "and Zfbfmin extension"); + return; + } + } + + if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { + error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); + return; + } + + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_zicsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (riscv_has_ext(env, RVF)) { + error_setg(errp, + "Zfinx cannot be supported together with F extensio= n"); + return; + } + } + + if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcmop extensions require Zca"); + return; + } + + if (mcc->def->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension is only relevant to RV32"); + return; + } + + if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension requires F extension"); + return; + } + + if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { + error_setg(errp, "Zcd extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " + "extension"); + return; + } + + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " + "Zcd extension"); + return; + } + + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { + error_setg(errp, "Zcmt extension requires Zicsr extension"); + return; + } + + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || + cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed= || + cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { + error_setg(errp, + "Vector crypto extensions require V or Zve* extensions"= ); + return; + } + + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x= ) { + error_setg( + errp, + "Zvbc and Zvknhb extensions require V or Zve64x extensions"); + return; + } + + if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { + error_setg(errp, "zicntr requires zicsr"); + return; + } + cpu->cfg.ext_zicntr =3D false; + } + + if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { + error_setg(errp, "zihpm requires zicsr"); + return; + } + cpu->cfg.ext_zihpm =3D false; + } + + if (cpu->cfg.ext_zicfiss) { + if (!cpu->cfg.ext_zicsr) { + error_setg(errp, "zicfiss extension requires zicsr extension"); + return; + } + if (!riscv_has_ext(env, RVA)) { + error_setg(errp, "zicfiss extension requires A extension"); + return; + } + if (!riscv_has_ext(env, RVS)) { + error_setg(errp, "zicfiss extension requires S"); + return; + } + if (!cpu->cfg.ext_zimop) { + error_setg(errp, "zicfiss extension requires zimop extension"); + return; + } + if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { + error_setg(errp, "zicfiss with zca requires zcmop extension"); + return; + } + } + + if (!cpu->cfg.ext_zihpm) { + cpu->cfg.pmu_mask =3D 0; + cpu->pmu_avail_ctrs =3D 0; + } + + if (cpu->cfg.ext_zclsd) { + if (riscv_has_ext(env, RVC) && riscv_has_ext(env, RVF)) { + error_setg(errp, + "Zclsd cannot be supported together with C and F exten= sion"); + return; + } + if (cpu->cfg.ext_zcf) { + error_setg(errp, + "Zclsd cannot be supported together with Zcf extension= "); + return; + } + } + + if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { + error_setg(errp, "zicfilp extension requires zicsr extension"); + return; + } + + if (mcc->def->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) { + error_setg(errp, "svukte is not supported for RV32"); + return; + } + + if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && + (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || + cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { + error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind"= ); + return; + } + cpu->cfg.ext_smctr =3D false; + cpu->cfg.ext_ssctr =3D false; + } + + if (cpu->cfg.ext_svrsw60t59b && + (!cpu->cfg.mmu || mcc->def->misa_mxl_max =3D=3D MXL_RV32)) { + error_setg(errp, "svrsw60t59b is not supported on RV32 and MMU-les= s platforms"); + return; + } + + /* + * Disable isa extensions based on priv spec after we + * validated and set everything we need. + */ + riscv_cpu_disable_priv_spec_isa_exts(cpu); +} diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5514e0f455..186d32fca8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -21,7 +21,6 @@ #include "qemu/log.h" #include "qemu/timer.h" #include "cpu.h" -#include "tcg/tcg-cpu.h" #include "pmu.h" #include "time_helper.h" #include "exec/cputlb.h" diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 8c24af0d85..4e1bb8849a 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -193,6 +193,25 @@ static inline target_ulong get_xepc_mask(CPURISCVState= *env) bool riscv_cpu_has_work(CPUState *cs); #endif =20 +void riscv_cpu_ext_user_opts_init(void); +void riscv_cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value); +void riscv_cpu_misa_ext_add_user_opt(uint32_t bit, bool value); +bool riscv_cpu_misa_ext_is_user_set(uint32_t bit); + +void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, bool enabled); + +void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp); +void riscv_cpu_update_cfg(RISCVCPU *cpu); + +void riscv_cpu_bump_multi_ext_priv_ver(CPURISCVState *env, + uint32_t ext_offset); +void riscv_cpu_cfg_ext_auto_update(RISCVCPU *cpu, + uint32_t ext_offset, + bool value); +const char *riscv_cpu_cfg_ext_get_name(uint32_t ext_offset); + +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); + /* Zjpm addr masking routine */ static inline target_ulong adjust_addr_body(CPURISCVState *env, target_ulong addr, diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 79f36abd63..4c99f2b802 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -16,6 +16,7 @@ riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', =20 riscv_ss.add(files( 'cpu.c', + 'cpu-validate.c', 'cpu_helper.c', 'csr.c', 'fpu_helper.c', diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 3e22e7ed53..13810f303d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -39,51 +39,9 @@ #include "exec/icount.h" #endif =20 -/* Hash that stores user set extensions */ -static GHashTable *multi_ext_user_opts; -static GHashTable *misa_ext_user_opts; - static GHashTable *multi_ext_implied_rules; static GHashTable *misa_ext_implied_rules; =20 -static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) -{ - return g_hash_table_contains(multi_ext_user_opts, - GUINT_TO_POINTER(ext_offset)); -} - -static bool cpu_misa_ext_is_user_set(uint32_t misa_bit) -{ - return g_hash_table_contains(misa_ext_user_opts, - GUINT_TO_POINTER(misa_bit)); -} - -static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value) -{ - g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset), - (gpointer)value); -} - -static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value) -{ - g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit), - (gpointer)value); -} - -static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, - bool enabled) -{ - CPURISCVState *env =3D &cpu->env; - - if (enabled) { - env->misa_ext |=3D bit; - env->misa_ext_mask |=3D bit; - } else { - env->misa_ext &=3D ~bit; - env->misa_ext_mask &=3D ~bit; - } -} - static const char *cpu_priv_ver_to_str(int priv_ver) { const char *priv_spec_str =3D priv_spec_to_str(priv_ver); @@ -294,556 +252,6 @@ const TCGCPUOps riscv_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 -static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) -{ - const RISCVIsaExtData *edata; - - for (edata =3D isa_edata_arr; edata && edata->name; edata++) { - if (edata->ext_enable_offset !=3D ext_offset) { - continue; - } - - return edata->min_version; - } - - g_assert_not_reached(); -} - -static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) -{ - const RISCVIsaExtData *edata; - - for (edata =3D isa_edata_arr; edata->name !=3D NULL; edata++) { - if (edata->ext_enable_offset =3D=3D ext_offset) { - return edata->name; - } - } - - g_assert_not_reached(); -} - -static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, - uint32_t ext_offset) -{ - int ext_priv_ver; - - if (env->priv_ver =3D=3D PRIV_VERSION_LATEST) { - return; - } - - ext_priv_ver =3D cpu_cfg_ext_get_min_version(ext_offset); - - if (env->priv_ver < ext_priv_ver) { - /* - * Note: the 'priv_spec' command line option, if present, - * will take precedence over this priv_ver bump. - */ - env->priv_ver =3D ext_priv_ver; - } -} - -static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, - bool value) -{ - CPURISCVState *env =3D &cpu->env; - bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); - int min_version; - - if (prev_val =3D=3D value) { - return; - } - - if (cpu_cfg_ext_is_user_set(ext_offset)) { - return; - } - - if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { - /* Do not enable it if priv_ver is older than min_version */ - min_version =3D cpu_cfg_ext_get_min_version(ext_offset); - if (env->priv_ver < min_version) { - return; - } - } - - isa_ext_update_enabled(cpu, ext_offset, value); -} - -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) -{ - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { - error_setg(errp, "H extension requires priv spec 1.12.0"); - return; - } -} - -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, - Error **errp) -{ - uint32_t min_vlen; - uint32_t vlen =3D cfg->vlenb << 3; - - if (riscv_has_ext(env, RVV)) { - min_vlen =3D 128; - } else if (cfg->ext_zve64x) { - min_vlen =3D 64; - } else if (cfg->ext_zve32x) { - min_vlen =3D 32; - } else { - return; - } - - if (vlen > RV_VLEN_MAX || vlen < min_vlen) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [%d, %d]", min_vlen, RV_VLEN_MAX); - return; - } - - if (cfg->elen > 64 || cfg->elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - - if (vlen < cfg->elen) { - error_setg(errp, "Vector extension implementation requires VLEN " - "to be greater than or equal to ELEN"); - return; - } -} - -static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) -{ - CPURISCVState *env =3D &cpu->env; - const RISCVIsaExtData *edata; - - /* Force disable extensions if priv spec version does not match */ - for (edata =3D isa_edata_arr; edata && edata->name; edata++) { - if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && - (env->priv_ver < edata->min_version)) { - /* - * These two extensions are always enabled as they were suppor= ted - * by QEMU before they were added as extensions in the ISA. - */ - if (!strcmp(edata->name, "zicntr") || - !strcmp(edata->name, "zihpm")) { - continue; - } - - /* - * cpu.debug =3D true is marked as 'sdtrig', priv spec 1.12. - * Skip this warning since existing CPUs with older priv - * spec and debug =3D true will be impacted. - */ - if (!strcmp(edata->name, "sdtrig")) { - continue; - } - - isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x%" PRIx64 - " because privilege spec version does not match", - edata->name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - edata->name); -#endif - } - } -} - -static void riscv_cpu_update_cfg(RISCVCPU *cpu) -{ - if (cpu->env.priv_ver >=3D PRIV_VERSION_1_11_0) { - cpu->cfg.has_priv_1_11 =3D true; - } - - if (cpu->env.priv_ver >=3D PRIV_VERSION_1_12_0) { - cpu->cfg.has_priv_1_12 =3D true; - } - - if (cpu->env.priv_ver >=3D PRIV_VERSION_1_13_0) { - cpu->cfg.has_priv_1_13 =3D true; - } - - /* zic64b is 1.12 or later */ - cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && - cpu->cfg.cbop_blocksize =3D=3D 64 && - cpu->cfg.cboz_blocksize =3D=3D 64 && - cpu->cfg.has_priv_1_12; - - cpu->cfg.ext_ssstateen =3D cpu->cfg.ext_smstateen; - - cpu->cfg.ext_sha =3D riscv_has_ext(&cpu->env, RVH) && - cpu->cfg.ext_ssstateen; - - cpu->cfg.ext_ziccrse =3D cpu->cfg.has_priv_1_11; -} - -static void riscv_cpu_validate_g(RISCVCPU *cpu) -{ - const char *warn_msg =3D "RVG mandates disabled extension %s"; - uint32_t g_misa_bits[] =3D {RVI, RVM, RVA, RVF, RVD}; - bool send_warn =3D cpu_misa_ext_is_user_set(RVG); - - for (int i =3D 0; i < ARRAY_SIZE(g_misa_bits); i++) { - uint32_t bit =3D g_misa_bits[i]; - - if (riscv_has_ext(&cpu->env, bit)) { - continue; - } - - if (!cpu_misa_ext_is_user_set(bit)) { - riscv_cpu_write_misa_bit(cpu, bit, true); - continue; - } - - if (send_warn) { - warn_report(warn_msg, riscv_get_misa_ext_name(bit)); - } - } - - if (!cpu->cfg.ext_zicsr) { - if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) { - cpu->cfg.ext_zicsr =3D true; - } else if (send_warn) { - warn_report(warn_msg, "zicsr"); - } - } - - if (!cpu->cfg.ext_zifencei) { - if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) { - cpu->cfg.ext_zifencei =3D true; - } else if (send_warn) { - warn_report(warn_msg, "zifencei"); - } - } -} - -static void riscv_cpu_validate_b(RISCVCPU *cpu) -{ - const char *warn_msg =3D "RVB mandates disabled extension %s"; - - if (!cpu->cfg.ext_zba) { - if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { - cpu->cfg.ext_zba =3D true; - } else { - warn_report(warn_msg, "zba"); - } - } - - if (!cpu->cfg.ext_zbb) { - if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { - cpu->cfg.ext_zbb =3D true; - } else { - warn_report(warn_msg, "zbb"); - } - } - - if (!cpu->cfg.ext_zbs) { - if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { - cpu->cfg.ext_zbs =3D true; - } else { - warn_report(warn_msg, "zbs"); - } - } -} - -/* - * Check consistency between chosen extensions while setting - * cpu->cfg accordingly. - */ -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - CPURISCVState *env =3D &cpu->env; - Error *local_err =3D NULL; - - if (riscv_has_ext(env, RVG)) { - riscv_cpu_validate_g(cpu); - } - - if (riscv_has_ext(env, RVB)) { - riscv_cpu_validate_b(cpu); - } - - if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { - error_setg(errp, - "Setting S extension without U extension is illegal"); - return; - } - - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x registers= "); - return; - } - - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - - if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } - - if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { - error_setg(errp, "Zacas extension requires A extension"); - return; - } - - if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { - error_setg(errp, "Zawrs extension requires A extension"); - return; - } - - if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfa extension requires F extension"); - return; - } - - if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } - - if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfbfmin extension depends on F extension"); - return; - } - - if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { - error_setg(errp, "D extension requires F extension"); - return; - } - - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - /* The Zve64d extension depends on the Zve64f extension */ - if (cpu->cfg.ext_zve64d) { - if (!riscv_has_ext(env, RVD)) { - error_setg(errp, "Zve64d/V extensions require D extension"); - return; - } - } - - /* The Zve32f extension depends on the Zve32x extension */ - if (cpu->cfg.ext_zve32f) { - if (!riscv_has_ext(env, RVF)) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension= "); - return; - } - } - - if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { - error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension= "); - return; - } - - if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { - error_setg(errp, "Zvfh extensions requires Zfhmin extension"); - return; - } - - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { - error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); - return; - } - - if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { - error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension= "); - return; - } - - if (cpu->cfg.ext_zvfbfa) { - if (!cpu->cfg.ext_zve32f || !cpu->cfg.ext_zfbfmin) { - error_setg(errp, "Zvfbfa extension requires Zve32f extension " - "and Zfbfmin extension"); - return; - } - } - - if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { - error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); - return; - } - - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_zicsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (riscv_has_ext(env, RVF)) { - error_setg(errp, - "Zfinx cannot be supported together with F extensio= n"); - return; - } - } - - if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { - error_setg(errp, "Zcmop extensions require Zca"); - return; - } - - if (mcc->def->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension is only relevant to RV32"); - return; - } - - if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension requires F extension"); - return; - } - - if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { - error_setg(errp, "Zcd extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || - cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { - error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " - "extension"); - return; - } - - if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { - error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " - "Zcd extension"); - return; - } - - if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { - error_setg(errp, "Zcmt extension requires Zicsr extension"); - return; - } - - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || - cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed= || - cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { - error_setg(errp, - "Vector crypto extensions require V or Zve* extensions"= ); - return; - } - - if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x= ) { - error_setg( - errp, - "Zvbc and Zvknhb extensions require V or Zve64x extensions"); - return; - } - - if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) { - error_setg(errp, "zicntr requires zicsr"); - return; - } - cpu->cfg.ext_zicntr =3D false; - } - - if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { - error_setg(errp, "zihpm requires zicsr"); - return; - } - cpu->cfg.ext_zihpm =3D false; - } - - if (cpu->cfg.ext_zicfiss) { - if (!cpu->cfg.ext_zicsr) { - error_setg(errp, "zicfiss extension requires zicsr extension"); - return; - } - if (!riscv_has_ext(env, RVA)) { - error_setg(errp, "zicfiss extension requires A extension"); - return; - } - if (!riscv_has_ext(env, RVS)) { - error_setg(errp, "zicfiss extension requires S"); - return; - } - if (!cpu->cfg.ext_zimop) { - error_setg(errp, "zicfiss extension requires zimop extension"); - return; - } - if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { - error_setg(errp, "zicfiss with zca requires zcmop extension"); - return; - } - } - - if (!cpu->cfg.ext_zihpm) { - cpu->cfg.pmu_mask =3D 0; - cpu->pmu_avail_ctrs =3D 0; - } - - if (cpu->cfg.ext_zclsd) { - if (riscv_has_ext(env, RVC) && riscv_has_ext(env, RVF)) { - error_setg(errp, - "Zclsd cannot be supported together with C and F exten= sion"); - return; - } - if (cpu->cfg.ext_zcf) { - error_setg(errp, - "Zclsd cannot be supported together with Zcf extension= "); - return; - } - } - - if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { - error_setg(errp, "zicfilp extension requires zicsr extension"); - return; - } - - if (mcc->def->misa_mxl_max =3D=3D MXL_RV32 && cpu->cfg.ext_svukte) { - error_setg(errp, "svukte is not supported for RV32"); - return; - } - - if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && - (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_smctr)) || - cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ssctr))) { - error_setg(errp, "Smctr and Ssctr require S-mode and Sscsrind"= ); - return; - } - cpu->cfg.ext_smctr =3D false; - cpu->cfg.ext_ssctr =3D false; - } - - if (cpu->cfg.ext_svrsw60t59b && - (!cpu->cfg.mmu || mcc->def->misa_mxl_max =3D=3D MXL_RV32)) { - error_setg(errp, "svrsw60t59b is not supported on RV32 and MMU-les= s platforms"); - return; - } - - /* - * Disable isa extensions based on priv spec after we - * validated and set everything we need. - */ - riscv_cpu_disable_priv_spec_isa_exts(cpu); -} - #ifndef CONFIG_USER_ONLY static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, RISCVCPUProfile *profile, @@ -934,7 +342,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu, =20 if (send_warn) { warn_report(warn_msg, profile->name, - cpu_cfg_ext_get_name(ext_offset)); + riscv_cpu_cfg_ext_get_name(ext_offset)); } } } @@ -1006,7 +414,7 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu, * If the user disabled the misa_bit do not re-enable = it * and do not apply any implied rules related to it. */ - if (cpu_misa_ext_is_user_set(misa_bits[i]) && + if (riscv_cpu_misa_ext_is_user_set(misa_bits[i]) && !(env->misa_ext & misa_bits[i])) { continue; } @@ -1025,7 +433,7 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu, /* Enable the implied extensions. */ for (i =3D 0; rule->implied_multi_exts[i] !=3D RISCV_IMPLIED_EXTS_RULE_END;= i++) { - cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true= ); + riscv_cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i]= , true); =20 ir =3D g_hash_table_lookup(multi_ext_implied_rules, GUINT_TO_POINTER( @@ -1049,26 +457,26 @@ static void cpu_enable_zc_implied_rules(RISCVCPU *cp= u) CPURISCVState *env =3D &cpu->env; =20 if (cpu->cfg.ext_zce) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); =20 if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max =3D=3D MXL_R= V32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), tr= ue); } } =20 /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); =20 if (riscv_has_ext(env, RVF) && mcc->def->misa_mxl_max =3D=3D MXL_R= V32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), tr= ue); } =20 if (riscv_has_ext(env, RVD)) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), tr= ue); } } } @@ -1078,12 +486,12 @@ static void cpu_enable_zilsd_implied_rules(RISCVCPU = *cpu) CPURISCVState *env =3D &cpu->env; =20 if (cpu->cfg.ext_zilsd && riscv_has_ext(env, RVC)) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zclsd), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zclsd), true= ); } =20 if (cpu->cfg.ext_zclsd) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zilsd), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + riscv_cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zilsd), true= ); } } =20 @@ -1142,7 +550,7 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu) } =20 if (set_misa_c) { - if (cpu_misa_ext_is_user_set(RVC)) { + if (riscv_cpu_misa_ext_is_user_set(RVC)) { warn_report("RVC mandated by Zca/Zcf/Zcd extensions"); return; } @@ -1284,7 +692,7 @@ static void riscv_cpu_set_profile(RISCVCPU *cpu, continue; } =20 - cpu_misa_ext_add_user_opt(bit, profile->enabled); + riscv_cpu_misa_ext_add_user_opt(bit, profile->enabled); riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); } =20 @@ -1292,10 +700,10 @@ static void riscv_cpu_set_profile(RISCVCPU *cpu, ext_offset =3D profile->ext_offsets[i]; =20 if (profile->enabled) { - cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); + riscv_cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); } =20 - cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); + riscv_cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled); isa_ext_update_enabled(cpu, ext_offset, profile->enabled); } } @@ -1355,7 +763,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 - cpu_misa_ext_add_user_opt(misa_bit, value); + riscv_cpu_misa_ext_add_user_opt(misa_bit, value); =20 prev_val =3D env->misa_ext & misa_bit; =20 @@ -1519,7 +927,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor= *v, const char *name, return; } =20 - cpu_cfg_ext_add_user_opt(cfg_offset, value); + riscv_cpu_cfg_ext_add_user_opt(cfg_offset, value); =20 prev_val =3D isa_ext_is_enabled(cpu, cfg_offset); =20 @@ -1535,7 +943,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor= *v, const char *name, } =20 if (value) { - cpu_bump_multi_ext_priv_ver(&cpu->env, cfg_offset); + riscv_cpu_bump_multi_ext_priv_ver(&cpu->env, cfg_offset); } =20 isa_ext_update_enabled(cpu, cfg_offset, value); @@ -1656,8 +1064,7 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); =20 - misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); - multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + riscv_cpu_ext_user_opts_init(); =20 if (!misa_ext_implied_rules) { misa_ext_implied_rules =3D g_hash_table_new(NULL, g_direct_equal); diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h index a23716a5ac..ceef3c4df2 100644 --- a/target/riscv/tcg/tcg-cpu.h +++ b/target/riscv/tcg/tcg-cpu.h @@ -22,7 +22,6 @@ =20 #include "cpu.h" =20 -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp); bool riscv_cpu_tcg_compatible(RISCVCPU *cpu); =20 --=20 2.43.0 From nobody Mon Jun 8 03:20:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Move them out of fpu_helper.c so fpu_helper.c can be built only when TCG is enabled. Signed-off-by: Zephyr Li --- target/riscv/cpu.h | 3 --- target/riscv/cpu_helper.c | 28 ++++++++++++++++++++++++++++ target/riscv/fpu_helper.c | 27 --------------------------- target/riscv/internals.h | 3 +++ 4 files changed, 31 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d79c7a5a7..2273567139 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -666,9 +666,6 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *en= v, RISCVException exception, uintptr_t pc); =20 -target_ulong riscv_cpu_get_fflags(CPURISCVState *env); -void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); - #ifndef CONFIG_USER_ONLY void cpu_set_exception_base(int vp_index, target_ulong address); #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 17305e1bb7..678c106ae5 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "fpu/softfloat.h" #include "internals.h" #include "pmu.h" #include "exec/cputlb.h" @@ -38,6 +39,33 @@ #include "pmp.h" #include "qemu/plugin.h" =20 +target_ulong riscv_cpu_get_fflags(CPURISCVState *env) +{ + int soft =3D get_float_exception_flags(&env->fp_status); + target_ulong hard =3D 0; + + hard |=3D (soft & float_flag_inexact) ? FPEXC_NX : 0; + hard |=3D (soft & float_flag_underflow) ? FPEXC_UF : 0; + hard |=3D (soft & float_flag_overflow) ? FPEXC_OF : 0; + hard |=3D (soft & float_flag_divbyzero) ? FPEXC_DZ : 0; + hard |=3D (soft & float_flag_invalid) ? FPEXC_NV : 0; + + return hard; +} + +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) +{ + int soft =3D 0; + + soft |=3D (hard & FPEXC_NX) ? float_flag_inexact : 0; + soft |=3D (hard & FPEXC_UF) ? float_flag_underflow : 0; + soft |=3D (hard & FPEXC_OF) ? float_flag_overflow : 0; + soft |=3D (hard & FPEXC_DZ) ? float_flag_divbyzero : 0; + soft |=3D (hard & FPEXC_NV) ? float_flag_invalid : 0; + + set_float_exception_flags(soft, &env->fp_status); +} + int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index af40561b31..eec6328281 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -23,33 +23,6 @@ #include "fpu/softfloat.h" #include "internals.h" =20 -target_ulong riscv_cpu_get_fflags(CPURISCVState *env) -{ - int soft =3D get_float_exception_flags(&env->fp_status); - target_ulong hard =3D 0; - - hard |=3D (soft & float_flag_inexact) ? FPEXC_NX : 0; - hard |=3D (soft & float_flag_underflow) ? FPEXC_UF : 0; - hard |=3D (soft & float_flag_overflow) ? FPEXC_OF : 0; - hard |=3D (soft & float_flag_divbyzero) ? FPEXC_DZ : 0; - hard |=3D (soft & float_flag_invalid) ? FPEXC_NV : 0; - - return hard; -} - -void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) -{ - int soft =3D 0; - - soft |=3D (hard & FPEXC_NX) ? float_flag_inexact : 0; - soft |=3D (hard & FPEXC_UF) ? float_flag_underflow : 0; - soft |=3D (hard & FPEXC_OF) ? float_flag_overflow : 0; - soft |=3D (hard & FPEXC_DZ) ? float_flag_divbyzero : 0; - soft |=3D (hard & FPEXC_NV) ? float_flag_invalid : 0; - - set_float_exception_flags(soft, &env->fp_status); -} - void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) { int softrm; diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 4e1bb8849a..7f28190c29 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -193,6 +193,9 @@ static inline target_ulong get_xepc_mask(CPURISCVState = *env) bool riscv_cpu_has_work(CPUState *cs); #endif =20 +target_ulong riscv_cpu_get_fflags(CPURISCVState *env); +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong val); + void riscv_cpu_ext_user_opts_init(void); void riscv_cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value); void riscv_cpu_misa_ext_add_user_opt(uint32_t bit, bool value); --=20 2.43.0 From nobody Mon Jun 8 03:20:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1780391998; cv=none; d=zohomail.com; s=zohoarc; b=Z1ZSrbx3IoV9Rt/uz0QFXVuJMbUJJCX88n386iG0bQZNS6CwPo8cqECzZZV98GTMVogA+mxiNAEPA83k/nfdRkvSE5s41E826Q7j2EzoWv91b27aOUJdetnTnx3nhjtOMxKdRpmqIs4Za8b5vYpdb5c3/iWzBd6l8MFKMjYgTQ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780391998; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8WxnG1ZaVTxzKCs44ZH++uO0YK7iL7fr4U5+9la7l0s=; b=KB3Jn4B/ZN2bp93sguDbROcs0MWFmmJr97IzvOOqHbcwDpi3iNRTvpu+JJ5KrXCGHz2425NZmxYT0dufSfU3Zn/WA2w2BwxPIkByQcmXWeBoN0dzuAGNlujGHyrSRPgXNR97OiNcEeMfbIyCzxjcudjX+IUOrtdeAh/Dkl7e79Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1780391998363364.1171905533283; Tue, 2 Jun 2026 02:19:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wULH3-0000nl-53; Tue, 02 Jun 2026 05:19:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wULGm-0000Yq-GP for qemu-devel@nongnu.org; Tue, 02 Jun 2026 05:18:49 -0400 Received: from mail-dy1-x1341.google.com ([2607:f8b0:4864:20::1341]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wULGh-0007YG-HL for qemu-devel@nongnu.org; Tue, 02 Jun 2026 05:18:42 -0400 Received: by mail-dy1-x1341.google.com with SMTP id 5a478bee46e88-304d7f31215so4950162eec.1 for ; Tue, 02 Jun 2026 02:18:35 -0700 (PDT) Received: from openkylin.. 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[54.176.108.193]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304ed2c3121sm11419146eec.5.2026.06.02.02.18.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:18:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1780391914; x=1780996714; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8WxnG1ZaVTxzKCs44ZH++uO0YK7iL7fr4U5+9la7l0s=; b=nQw3AdRAVZyZHrjCr3Z3dZ/x8jx1i0QiHI6WFMqUHKqnacfh3BcHHSsIkm8UUjpR7T EeCVOcNOTlqBHb5qOw1LdCBz5s5MCmd1vx4ZLrQyBxZ0LylSEO/kBOngb+2ks6/4jgf5 AMTxOVg48E8AVHsLFD6SYB/z5/67uIb8wGMloWRneXP98SpxzRISuBD2blZMqXD3ScrX iSnUZeubIyrZF1Vuh5ngUFcgGMaF3BfW34NR63VHbstg9ZmW2CKBFwoqajQHKKGragGD NUYHMQ03wJumKGyPtfNjSbaY5j1op3HKD4MGmWyDCDURylbyS1Dg7SWVtW6AQFbVXq37 tZxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391915; x=1780996715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=8WxnG1ZaVTxzKCs44ZH++uO0YK7iL7fr4U5+9la7l0s=; b=PY1A01igVMMd4Jt0QrOijeS1LCqpKKDBb6xovqu11eUNg37te1AEHMn9rIHOBbBk2h G4YPpVmKcjD3TYf6vFaNCaRWUyg1HiBmyVq2WotMqlUcZBmLa98RraQ8eYcUN5+/Kebv KWPBLvevcJuGjvoWzEVl9hrM8NZGY6i2s9CrLYu9/ljiRb8WVtxzfazsJYGCp5Vfj/nW LKIA9WMW0yxEvfIUMs79LTDPef1NqdgNWWfbwLTlEM3+xDPNHIRLIaL3G/8I73bUHEJQ +LZcVsEZseUQSs16HZhWWfUVgwOrkYjWMVbzGvCraYpUX27wykC/mGw6SaWGaExEHJFz G0fQ== X-Gm-Message-State: AOJu0YxoNGUWbTDGtpFHs75Hjq6O4kJvlTbNUdfKj1LpMarUXMXGvKLC x6YGu5Q7y8lF60OCocjYfIfFvsM4e/m09qZRiVvmET2BidERFN2AulsZX0SOOqVuBl1KOw== X-Gm-Gg: Acq92OE4Fcp549xcKyZuCED14a5P8ppGo78bu7G4V1cMZ5Rbm+XnKCktxOYAcfWtVaj qOq0yTOS+R99vxcPPCaXE7E7stvweBiw2X9/CgOxwXKMy25k4lJif0hsot+8jnzPFNHkHu2wLk5 WH4SSJkyYlLlK2jNO6rXxwVt7KPp22stcUlq6OMlJTekW4lhGlqvRosL809UloJAc/ppO7Vo15R s76BAS1wI0m8+yvUKop7R2AnghoBJa1mvCLqJm37ISsgW0X2qcZkhnv1VA04BZceFNfs3X8X1Fn MmRSMVRbh7QoNF44UHP8XWBmd0/ijB/YsJTzsJkxqIl1LE1APsyAnN0k4+YWEvBK7cOvnfiVOBD o1NtO3ZO+DM6wey6ad9M9xQVuSS6eassNfxTDSzfxsmGtAbtfclRa7iQko5I4sNo7+azzCKWUq9 sSCAUY4LRWeF2/7wVeS9ACTk1MFDXLCyy7kXAby0bl8sJL6dXMVLacl9vWaG9RCfYv38HkEz7rP idZqnmBp0zx78G5P1qPYzMJsLY= X-Received: by 2002:a05:7300:f18f:b0:303:f26f:df30 with SMTP id 5a478bee46e88-304fa632e0dmr6146120eec.23.1780391914520; Tue, 02 Jun 2026 02:18:34 -0700 (PDT) From: Zephyr Li To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, alex.bennee@linaro.org, pierrick.bouvier@oss.qualcomm.com, philmd@linaro.org, Zephyr Li Subject: [PATCH v3 3/6] target/riscv: move riscv_raise_exception() out of op_helper.c Date: Tue, 2 Jun 2026 17:17:50 +0800 Message-ID: <20260602091753.3209261-4-fritchleybohrer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602091753.3209261-1-fritchleybohrer@gmail.com> References: <20260602091753.3209261-1-fritchleybohrer@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1341; envelope-from=fritchleybohrer@gmail.com; helo=mail-dy1-x1341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1780392000307154100 Content-Type: text/plain; charset="utf-8" riscv_raise_exception() is referenced by RISC-V internal code, but its current implementation relies on TCG's cpu_loop_exit_restore(). Move it to cpu_helper.c so op_helper.c can become TCG-only. The actual exception unwind still relies on TCG's cpu_loop_exit_restore(), so the non-TCG path remains unreachable. Signed-off-by: Zephyr Li --- target/riscv/cpu.h | 4 ---- target/riscv/cpu_helper.c | 19 +++++++++++++++++++ target/riscv/debug.c | 1 + target/riscv/internals.h | 4 ++++ target/riscv/op_helper.c | 15 --------------- target/riscv/zce_helper.c | 1 + 6 files changed, 25 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2273567139..98bda189e6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -662,10 +662,6 @@ void riscv_translate_init(void); void riscv_translate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, vaddr pc, void *host_pc); =20 -G_NORETURN void riscv_raise_exception(CPURISCVState *env, - RISCVException exception, - uintptr_t pc); - #ifndef CONFIG_USER_ONLY void cpu_set_exception_base(int vp_index, target_ulong address); #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 678c106ae5..752752d520 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -39,6 +39,25 @@ #include "pmp.h" #include "qemu/plugin.h" =20 +/* Exceptions processing helpers */ +G_NORETURN void riscv_raise_exception(CPURISCVState *env, + RISCVException exception, + uintptr_t pc) +{ + CPUState *cs =3D env_cpu(env); + + trace_riscv_exception(exception, + riscv_cpu_get_trap_name(exception, false), + env->pc); + + cs->exception_index =3D exception; +#ifdef CONFIG_TCG + cpu_loop_exit_restore(cs, pc); +#else + qemu_build_not_reached(); +#endif +} + target_ulong riscv_cpu_get_fflags(CPURISCVState *env) { int soft =3D get_float_exception_flags(&env->fp_status); diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 5664466749..1a74aedeab 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "cpu.h" +#include "internals.h" #include "trace.h" #include "exec/helper-proto.h" #include "exec/watchpoint.h" diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 7f28190c29..1863012807 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -193,6 +193,10 @@ static inline target_ulong get_xepc_mask(CPURISCVState= *env) bool riscv_cpu_has_work(CPUState *cs); #endif =20 +G_NORETURN void riscv_raise_exception(CPURISCVState *env, + RISCVException exception, + uintptr_t pc); + target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong val); =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 81873014cb..d17a8bbf10 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -28,21 +28,6 @@ #include "exec/tlb-flags.h" #include "trace.h" =20 -/* Exceptions processing helpers */ -G_NORETURN void riscv_raise_exception(CPURISCVState *env, - RISCVException exception, - uintptr_t pc) -{ - CPUState *cs =3D env_cpu(env); - - trace_riscv_exception(exception, - riscv_cpu_get_trap_name(exception, false), - env->pc); - - cs->exception_index =3D exception; - cpu_loop_exit_restore(cs, pc); -} - void helper_raise_exception(CPURISCVState *env, uint32_t exception) { riscv_raise_exception(env, exception, 0); diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c index 15bf0a99c8..152a7a63ef 100644 --- a/target/riscv/zce_helper.c +++ b/target/riscv/zce_helper.c @@ -18,6 +18,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" =20 --=20 2.43.0 From nobody Mon Jun 8 03:20:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[54.176.108.193]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304ed2c3121sm11419146eec.5.2026.06.02.02.18.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:18:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1780391920; x=1780996720; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PCLumQ0UyNQHKa/ypfifej8V3OAD6FODRX9ywAOjyVA=; b=M2ntlYJf1Azh56TrvgvL5KtpTsGwa1xJVatQ+Ldh8cufU+7al30A5VnHitJq7mhjWJ 8dyAK5G3itKmkJvoAAdBTfjwsrvgrey9UmK0TXo/DWwNTm+/THR7Vays94I/S47TreRG guQoV/jKSuKi0c4XW/QT3AaLVnU8TbIDblcLM9EvcfiOThviHadnAXbGgdGx9xH89f0w Za5SJSzNXnzJ1B6bXBsuCMK4Un5/nL8q3SavesRCAP6jBQ5iiOuhKxKwJRavLVLRA2P+ vKBAmHV6XlyISmjhZVvF/u3c6abz30nV80TbsaJ2/ynPEyCWgNhG4ZYPDhJSd4MSlzar rj4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391920; x=1780996720; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=PCLumQ0UyNQHKa/ypfifej8V3OAD6FODRX9ywAOjyVA=; b=NvdLNdSezYCsf+OkdHH7kONc6YdFbuyChQOZunq/Xkj5SPYegr/N2ARqvtIDNraJcI qm6DKfPQXPk7s0F9IA8hiL0S7+6NgHDj4gVwpVDB7Lk7vBcB27iJeHJ4XWmYoV8reKgE jx5i7ogM0E8oJEAm6a7hh4wocAcjvukZbPlEKf5TOXAslstYaGoM1Cl46ONkciT8douD gyRyF8HvG1UVlyESwd8qQggLmGT9yyziYqAdrGPFMIkhJQgVbuh+8tzZFBuoyjiWpAWe T1TL9tIZwupUA4xDYnb9k+3Tv8mRU0Sz+2wnDdtNOfOZ2AdrRlxv99ictYNfAZB4DrIK S40w== X-Gm-Message-State: AOJu0YwUDY1w7ZFNS2MYZfX5SXbaHRIA2dnV0AgbrzdA3FH4sNCaedFU rd+XhuGlxS3AJN/eI9uP7tZpXSHtiQwu4OKR6nBfyN7nmhBnc1FbBJ3ISu+iygsl+qtVyw== X-Gm-Gg: Acq92OE5NoV4wuUCJvL6yngbwB1C8ykjQ/bkmpLaVQpkf6NHVJRnFKumyuwvveCAJmJ HtpckcRTqP5QbLKWibYhmFwFaZvCDAyvaWtFmJjiw3Dx1NHnVlCxCtlSX8MaA3RmiXhJZtfJxhL wSYinkL2FbVuudr95BBL5P9YDCw2HenFEKndcIsQIfTPahL9JkRTOIp7dFw+pXaBM37I3xmi4Y5 u34iuUJX9LwF/463M/JiaLrz3jItBW5r3qWify5JUDFVbHxozhuVyIrC68hFFUZc5cJ/5m4apgf mOJ7wLQ70FQPNsjkGMbzcv7v6w8NtKRtEw4TpitVQRMI6+X2KtQEnbzdFheKMmWTfxRYP2d2vcr 7Gkfczn6oV8ZDuHkBOXSljmZLBgpAj0SyPVhMIoCOVzQNRsPIqh/6pcRxo7ObpTOJkW2Nvp6pWE I1TuU2/weUThcAlk0u3mmGBYcKZZGJJdG+o8REXjWe306pwtKO0dPqmsRnV/sfnZzvXCUIaDOgq ennV4PmPJxIpS4cX2RPLk4Fo4FkNzkPCt4JeA== X-Received: by 2002:a05:693c:300c:b0:2ca:8099:ffc0 with SMTP id 5a478bee46e88-304fa4a90c6mr7077827eec.7.1780391920436; Tue, 02 Jun 2026 02:18:40 -0700 (PDT) From: Zephyr Li To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, alex.bennee@linaro.org, pierrick.bouvier@oss.qualcomm.com, philmd@linaro.org, Zephyr Li Subject: [PATCH v3 4/6] target/riscv: reject x-misa-w outside TCG Date: Tue, 2 Jun 2026 17:17:51 +0800 Message-ID: <20260602091753.3209261-5-fritchleybohrer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602091753.3209261-1-fritchleybohrer@gmail.com> References: <20260602091753.3209261-1-fritchleybohrer@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1242; envelope-from=fritchleybohrer@gmail.com; helo=mail-dl1-x1242.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1780392020583154100 Content-Type: text/plain; charset="utf-8" x-misa-w controls dynamic writes to misa in the emulated CPU path and is only meaningful when TCG is available. Reject it explicitly outside TCG instead of relying on TCG-only finalize code. This also covers CONFIG_TCG builds that are running with a non-TCG accelerator. It also rejects CPU models that require writable misa by default when the selected accelerator is not TCG. Signed-off-by: Zephyr Li --- target/riscv/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 862834b480..8ef72a88b1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -956,6 +956,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 + if (cpu->cfg.misa_w) { +#ifdef CONFIG_TCG + if (!tcg_enabled()) { + error_setg(errp, "x-misa-w requires TCG"); + return; + } +#else + error_setg(errp, "x-misa-w requires TCG"); + return; +#endif + } + cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.43.0 From nobody Mon Jun 8 03:20:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1780392043; cv=none; d=zohomail.com; s=zohoarc; b=V653Gk8hqz6Bv/02nG3DHdsQPVRQ1rpTWsiOegmOa+nimTXeGPRuxz6feaemE8/JS3Gj6r2ZUH6sZ69cZDNBBTfnLKN9PNAr76F3728qZq6TgZFvywanXcn/P/J7GLhk/tRZc8ONBwwOSQfIj5HkW7ezy0LWA9uimNv9ZYP6bhE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1780392043; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HcOVA7z761sRU6mzSlK4g0qMB5qPdXRWmaIP73uflqw=; b=at6f89KPwCUJr8f+8utWYBz0tUvyaTeAlEE9AaBXE4Vk27v+qoHWn6TjnXCjjpfDW/5yuacOTYf6UlhfX9hxp3+sBD/YLkZEIahMt1+Pd0edXi5Ic8Raxkqr+tNtNG8Q6SuLHg5hbfM46rUVK8CBAXj8wyR7WneNS/hb2Tc84pk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 178039204323884.28085393137553; Tue, 2 Jun 2026 02:20:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wULH5-0000vw-HM; Tue, 02 Jun 2026 05:19:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wULGu-0000cY-Kk for qemu-devel@nongnu.org; Tue, 02 Jun 2026 05:18:54 -0400 Received: from mail-dy1-x1341.google.com ([2607:f8b0:4864:20::1341]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wULGp-0007k3-UQ for qemu-devel@nongnu.org; Tue, 02 Jun 2026 05:18:51 -0400 Received: by mail-dy1-x1341.google.com with SMTP id 5a478bee46e88-304e83724bfso5376192eec.0 for ; Tue, 02 Jun 2026 02:18:47 -0700 (PDT) Received: from openkylin.. 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[54.176.108.193]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-304ed2c3121sm11419146eec.5.2026.06.02.02.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 02:18:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1780391926; x=1780996726; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HcOVA7z761sRU6mzSlK4g0qMB5qPdXRWmaIP73uflqw=; b=V1N7agQXjFvn7TxbMUM5oQwRRdCuJ13e2gYM36xkXCT1moUR8wwatkwUs6h7KwzTr5 x55pUPtzJcxeC3BLotT0cJvWW3pbTnCyR3vg6tsPHmj6OmMVhEP9Sh3izmCbTocl42HD 36vD72V+EiYd8XoMwiJZVbjU65mbyQ7x0Pn6Nu/Ly0HB779y9kuv/Be0CwH3K8JB43Lm McQeame5kzwDC2Wml5ZIifSkF5a3vM5oP0JZw9aJ5dH/BYe0ph1eRHz3nC9QBH+mNbEm fEG8gjOIAAyA4mwr+BZOkNgHfXOpUFKf6EVnHLjrgjn+w5itQQo31aVTQiVXDCKnuAsO Un5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780391926; x=1780996726; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=HcOVA7z761sRU6mzSlK4g0qMB5qPdXRWmaIP73uflqw=; b=X2RXld0AxK24cfAjXUyeiFd5zUwHf78Ncb1r5YRPr6dIqSwYl5wO0dTaOC81UuUPcK ymweAXyWbIz6MJL3oLIpF3nJggIuTcvQo3jYhLnIupoppIyEmE5urL2Z4IAWZlRUyQr6 oWJNbhSKzgV30khmktYqiyQQUarpX8HFxYtnbTWMMPcr4n8uih3cA4V9UAJCt5eOLI7V tjCbnn7ue6piU465rBKhfD9bh+A3d6kuV9nlGksUTQzl95h/dyMsCx2s3Qt1Kynte9nW kwbqG2DlUFV2nNXLNmmDshTBV5Rxw5fPNC7ZFwgLfbBeOztH7fZIyx+50UNXpWYOdbDv v2iw== X-Gm-Message-State: AOJu0Yx2L11zYF03k/K/1cOzqLHWToYB9vtgYA0QBfv0pCCDfWbXhaIp Etf5QeswGvQi6oX+kV/GLnViHIKkxydI0OxpCbyobWSuHsge4TIUsV5rj+kTkRzK15D3zw== X-Gm-Gg: Acq92OFIPOY3Nyu9i8WIkntATLCgZez21HXw1p5YUWtBX9/mIB98y4OG7NDYfQzINj9 inbv8wKYYOpS/nFdQEEuUH3kZsYKdCmlrsuU3PEfaRDkCJHd+TUwfoxvxdMKtWv1fieJGnMhxva QIAFR50/bWTqFUUYMIZ9hUgc7+PMupuQykLEwX76KJ4sv3fHA5hD8OCZMwZg1mELxkJyKLfcTPk iEIIppLlY+bxEvh7isN3o/FkprFaq/5MLxpc3EeZ0RcIjYAZCzZLzWf2NsgQNMxQmUyt3XhWgWK AmWGD17KGVeNcWPm4mNNGFHtr2eKb9O73A45x1ea0h3+GKAqG0yGr/6yQ5+fo6C8EFPT2CQcFB+ 5Mdgpv3jZSpvOKPVvwTx8Y4H9lpK2coHzSlzcySBSKPK7DsmDDP8YZN/WxCDAJ5pAcegC0cXmBl u+KaMrtEQ/LDcjLxCblUMc6xRDk806BFMIz4a+QfTUHBNiaqU8HFmLLa8kgfu4DzT1fiAWKZVe/ hdtEUJwuYURZvZHc/9V06y1F8w= X-Received: by 2002:a05:7300:6c84:b0:2ea:ed70:3ea8 with SMTP id 5a478bee46e88-304fa6939demr7209201eec.29.1780391926221; Tue, 02 Jun 2026 02:18:46 -0700 (PDT) From: Zephyr Li To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com, alex.bennee@linaro.org, pierrick.bouvier@oss.qualcomm.com, philmd@linaro.org, Zephyr Li Subject: [PATCH v3 5/6] target/riscv: build TCG-only sources only with TCG Date: Tue, 2 Jun 2026 17:17:52 +0800 Message-ID: <20260602091753.3209261-6-fritchleybohrer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260602091753.3209261-1-fritchleybohrer@gmail.com> References: <20260602091753.3209261-1-fritchleybohrer@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1341; envelope-from=fritchleybohrer@gmail.com; helo=mail-dy1-x1341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1780392044986154100 Content-Type: text/plain; charset="utf-8" Several RISC-V source files contain translated-code helpers, decoders, or TCG-only instruction implementations, but are currently part of the common RISC-V source set. This breaks --disable-tcg builds once TCG headers and helpers are unavailable. After moving common helpers out of TCG-only files, build the remaining TCG-only RISC-V sources only when CONFIG_TCG is enabled. Keep common CSR misa handling from relying on TCG unwind state in no-TCG builds by falling back to env->pc. Drop the stale tcg/tcg.h include from common CPU code so no-TCG builds do not include a TCG-private header. Signed-off-by: Zephyr Li --- target/riscv/cpu.c | 1 - target/riscv/cpu_helper.c | 6 ++++++ target/riscv/csr.c | 11 +++++++++-- target/riscv/meson.build | 9 ++++++--- 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ef72a88b1..459e32f4ac 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -36,7 +36,6 @@ #include "system/tcg.h" #include "kvm/kvm_riscv.h" #include "tcg/tcg-cpu.h" -#include "tcg/tcg.h" =20 /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] =3D "IEMAFDQCBPVH"; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 752752d520..e53a5d567d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -29,8 +29,10 @@ #include "exec/target_page.h" #include "system/memory.h" #include "instmap.h" +#ifdef CONFIG_TCG #include "tcg/tcg-op.h" #include "accel/tcg/cpu-ops.h" +#endif #include "trace.h" #include "semihosting/common-semi.h" #include "exec/icount.h" @@ -1714,6 +1716,7 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, return TRANSLATE_SUCCESS; } =20 +#ifdef CONFIG_TCG static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violat= ion, bool first_stage, bool two_stage, @@ -1756,6 +1759,7 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, env->two_stage_lookup =3D two_stage; env->two_stage_indirect_lookup =3D two_stage_indirect; } +#endif =20 hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr) { @@ -1780,6 +1784,7 @@ hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, va= ddr addr) return phys_addr; } =20 +#ifdef CONFIG_TCG void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -2004,6 +2009,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 return true; } +#endif =20 static target_ulong riscv_transformed_insn(CPURISCVState *env, target_ulong insn, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 186d32fca8..9a9a148bfe 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2134,15 +2134,22 @@ static RISCVException read_misa(CPURISCVState *env,= int csrno, =20 static target_ulong get_next_pc(CPURISCVState *env, uintptr_t ra) { + /* Outside of a running cpu, env contains the next pc. */ + if (ra =3D=3D 0) { + return env->pc; + } +#ifdef CONFIG_TCG uint64_t data[INSN_START_WORDS]; =20 - /* Outside of a running cpu, env contains the next pc. */ - if (ra =3D=3D 0 || !cpu_unwind_state_data(env_cpu(env), ra, data)) { + if (!cpu_unwind_state_data(env_cpu(env), ra, data)) { return env->pc; } =20 /* Within unwind data, [0] is pc and [1] is the opcode. */ return data[0] + insn_len(data[1]); +#else + return env->pc; +#endif } =20 static RISCVException write_misa(CPURISCVState *env, int csrno, diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 4c99f2b802..2f86dbd5bf 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -9,7 +9,7 @@ gen =3D [ ] =20 riscv_ss =3D ss.source_set() -riscv_ss.add(gen) +riscv_ss.add(when: 'CONFIG_TCG', if_true: gen) =20 riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('common-semi-target.c')) @@ -19,11 +19,14 @@ riscv_ss.add(files( 'cpu-validate.c', 'cpu_helper.c', 'csr.c', - 'fpu_helper.c', 'gdbstub.c', + 'vector_internals.c', +)) + +riscv_ss.add(when: 'CONFIG_TCG', if_true: files( + 'fpu_helper.c', 'op_helper.c', 'vector_helper.c', - 'vector_internals.c', 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', --=20 2.43.0 From nobody Mon Jun 8 03:20:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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This ensures that RISC-V no-TCG/KVM-only builds keep working and prevents TCG-only code from being accidentally pulled into common RISC-V sources again. The cross_accel_build_job template enables KVM by default via --enable-${ACCEL:-kvm}, so the extra options only need to disable TCG. Signed-off-by: Zephyr Li --- .gitlab-ci.d/crossbuilds.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index eaeeb533ce..a823aaaa21 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -59,6 +59,14 @@ cross-riscv64-user: variables: IMAGE: debian-riscv64-cross =20 +cross-riscv64-kvm-only: + extends: .cross_accel_build_job + needs: + - job: riscv64-debian-cross-container + variables: + IMAGE: debian-riscv64-cross + EXTRA_CONFIGURE_OPTS: --disable-tcg --without-default-features + cross-s390x-system: extends: .cross_system_build_job needs: --=20 2.43.0