This series introduces the initial ASPEED AST1040 support for QEMU.

AST1040 is the next-generation bridge/BIC controller platform
following AST1030 and is based on an ARM Cortex-M4F CPU core.
Since QEMU currently does not provide Cortex-M4F support, the
existing Cortex-M4 CPU model is used temporarily.

The current implementation provides enough functionality to boot
basic firmware environments with UART console support, SDRAM/SRAM
mapping, and NVIC interrupt handling.

At the moment, AST1040 firmware has not been publicly released
yet, so this series is mainly intended to provide an evaluation
platform for users interested in AST1040 development.

Documentation updates and functional test coverage will be added
after the firmware release becomes available.

Currently this series is able to boot Zephyr successfully to the
shell prompt:

  uart:~$

Example command line:

  ./build/qemu-system-arm \
      -machine ast1040-evb \
      -kernel <zephyr.elf> \
      -serial mon:stdio \
      -snapshot \
      -nographic

v1:
  - AST1040 silicon revision ID
  - SDRAM support in the Aspeed SoC framework
  - Initial AST1040 SoC model
  - AST1040 EVB machine model
  
Jamin Lin (4):
  hw/misc/aspeed_scu: Add AST1040 A0 silicon revision ID
  hw/arm/aspeed: Introduce SDRAM memory region support
  hw/arm/aspeed: Introduce AST1040 A0 SoC model
  hw/arm/aspeed: Add AST1040 EVB machine model

 include/hw/arm/aspeed_soc.h  |   2 +
 include/hw/misc/aspeed_scu.h |   1 +
 hw/arm/aspeed_ast1040.c      | 246 +++++++++++++++++++++++++++++++++++
 hw/arm/aspeed_ast1040_evb.c  |  72 ++++++++++
 hw/misc/aspeed_scu.c         |   1 +
 hw/arm/meson.build           |   4 +-
 6 files changed, 325 insertions(+), 1 deletion(-)
 create mode 100644 hw/arm/aspeed_ast1040.c
 create mode 100644 hw/arm/aspeed_ast1040_evb.c

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2.43.0