AST1040 platforms require dedicated SDRAM handling in addition to
the existing SRAM support. Add an SDRAM MemoryRegion to
AspeedSoCState and introduce an sdram_size field in
AspeedSoCClass for SoC-specific SDRAM configuration.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 include/hw/arm/aspeed_soc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index d7b3647ca1..ce431be940 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -67,6 +67,7 @@ struct AspeedSoCState {
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
+    MemoryRegion sdram;
     MemoryRegion sram;
     MemoryRegion spi_boot_container;
     MemoryRegion spi_boot;
@@ -171,6 +172,7 @@ struct AspeedSoCClass {
     /** valid_cpu_types: NULL terminated array of a single CPU type. */
     const char * const *valid_cpu_types;
     uint32_t silicon_rev;
+    uint64_t sdram_size;
     uint64_t sram_size;
     uint64_t secsram_size;
     int pcie_num;
-- 
2.43.0