On Wed, 2026-05-20 at 15:12 +0200, Anton Johansson wrote:
Also please send patches to all people listed under the RISC-V
maintainers, otherwise not everyone ends up seeing the messages.
Alistair
> Compiles hw/riscv a single time for both qemu-system-riscv32 and
> qemu-system-riscv64 by adopting the TargetInfo API and by moving
> machine definitions to generic QOM interfaces. This is the same
> approach
> as taken by Philippe in
>
> "single-binary: Make hw/arm/ common"
> (20251021205741.57109-1-philmd@linaro.org).
>
> All in all, the number of compilation when building both
> riscv[32|64]-softmmu is reduced by 11, and the binary size of
> qemu-system-riscv[32|64] is increased by 0.11% and 0.026%
> respectively
> (corresponding to 65k and 14k bytes).
>
> This patchset is based on:
>
> "single-binary: Make riscv cpu.h target independent"
> (20260520125406.28693-1-anjo@rev.ng).
>
> Branch passing CI can be found here:
>
> https://gitlab.com/AntonJohansson/qemu/-/pipelines/2215536778
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> Changes in v3:
> - Dropped merged prequisite patchsets.
> - patch 5/14 "configs/target: Implement per-binary TargetInfo
> structure
> for riscv": Use new target_info_init() TargetInfo registration.
> - patch 7/14 "target/riscv: Replace TYPE_RISCV_CPU_BASE": Rename
> virt_default_cpu_type() -> riscv_default_cpu_type() and define in
> machines-qom.h.
> - Dropped patch "[PATCH v2 11/14] target/riscv: Make pmu.h target-
> agnostic":
> This patch replaced target_ulongs with privilege_mode_t and has
> been folded
> into the prerequisite patchset introducing the typedef.
> - Added patch 12/14 "target/riscv: Move target_long.h inclusion
> away from cpu.h": Moves target_long.h inclusion to target specific
> header.
> - Link to v2:
> https://lore.kernel.org/qemu-devel/20251221-hw-riscv-cpu-int-v2-0-eb49d72c5b2f@rev.ng
>
> Changes in v2:
> - Inlined sifive_cpu.h runtime functions and removed header
> (Philippe);
> - Moved IRQ_LOCAL_GUEST_MAX macro to field in RISCVCPUDef (Philippe);
> - Added reviewed-bys;
> - Link to v1:
> https://lore.kernel.org/qemu-devel/20251217-hw-riscv-cpu-int-v1-0-d24a4048d3aa@rev.ng
> .
>
> ---
> Anton Johansson (14):
> hw/riscv: Register generic riscv[32|64] QOM interfaces
> hw/riscv: Add macros and globals for simplifying machine
> definitions
> hw/riscv: Filter machine types for qemu-system-riscv32/64
> binaries
> hw/core: Add riscv[32|64] to "none" machine
> configs/target: Implement per-binary TargetInfo structure for
> riscv
> target-info: Add target_riscv64()
> target/riscv: Replace TYPE_RISCV_CPU_BASE
> target/riscv: Remove ifdefs in cpu.h
> target/riscv: Replace TARGET_LONG_BITS in header exposed to
> common code
> target/riscv: Move riscv_pmu_read_ctr() to internal csr.h
> header
> target/riscv: Stub out kvm functions
> target/riscv: Move target_long.h inclusion away from cpu.h
> hw/riscv: Define SiFive E/U CPUs using runtime conditions
> hw/riscv: Compile once
>
> include/hw/riscv/machines-qom.h | 58
> +++++++++++++++++++++++++++++++++++++++
> include/hw/riscv/sifive_cpu.h | 31 ---------------------
> include/hw/riscv/sifive_e.h | 1 -
> include/hw/riscv/sifive_u.h | 1 -
> include/qemu/target-info.h | 7 +++++
> target/riscv/cpu.h | 44 ++++++-----------------------
> target/riscv/cpu_bits.h | 2 --
> target/riscv/csr.h | 3 ++
> target/riscv/internals.h | 1 +
> target/riscv/pmu.h | 2 --
> configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++
> configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++
> hw/core/null-machine.c | 3 ++
> hw/intc/riscv_imsic.c | 4 ++-
> hw/riscv/boston-aia.c | 3 +-
> hw/riscv/microblaze-v-generic.c | 5 ++--
> hw/riscv/microchip_pfsoc.c | 2 ++
> hw/riscv/opentitan.c | 2 ++
> hw/riscv/shakti_c.c | 2 ++
> hw/riscv/sifive_e.c | 5 +++-
> hw/riscv/sifive_u.c | 9 ++++--
> hw/riscv/spike.c | 4 ++-
> hw/riscv/virt.c | 5 +++-
> hw/riscv/xiangshan_kmh.c | 2 ++
> target-info-qom.c | 9 ++++++
> target-info.c | 5 ++++
> target/riscv/cpu.c | 14 ++++++++--
> target/riscv/kvm/kvm-stub.c | 23 ++++++++++++++++
> target/riscv/machine.c | 17 ++++++++++++
> target/riscv/pmu.c | 1 +
> configs/targets/meson.build | 1 +
> hw/riscv/meson.build | 36 ++++++++++++------------
> target/riscv/kvm/meson.build | 1 +
> 33 files changed, 254 insertions(+), 101 deletions(-)