From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1779282634; cv=none; d=zohomail.com; s=zohoarc; b=EwFonbX6kQ3AL7Glv91VV9b5kysCJsqyhWv7kxJn8j2DTu1IfT7MQVQF6Ce92tCfBamOE6LC9w9rwBqqzUEMZlg4qc33rEyl0G1CPlaW0CQBHFL3VMD+uUJKwGzI3HzMdjjfy4xqrgNeu9g3l3NtbAoRbnrXJK3IHn+cj3f/rZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779282634; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=uCAo6aeIllRIO0o13tM+9c0nxO907s4Ph2ZcsNmbCKM=; b=lg90Vhsz6OCZ0cjxfZUE9dh0qDePDoStmeYwsEg3wERqcXEJJfQeBraXeUMJqgjEVcGVdo8qsfzEZ7XVLGuQOM7EI41CGVIQQmklmhlCsguzNHWgNTLCGuoQbMXstSZqk/iN9EHW9b+SKlObkmVg8qdQ4IAhPAIqFTsqSKH88Dg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779282634545390.7732821127538; Wed, 20 May 2026 06:10:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wPgf0-0004jY-9t; Wed, 20 May 2026 09:08:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPgey-0004iS-8r; Wed, 20 May 2026 09:08:28 -0400 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wPgew-000134-FC; Wed, 20 May 2026 09:08:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=uCAo6aeIllRIO0o13tM+9c0nxO907s4Ph2ZcsNmbCKM=; b=VqkjMngeMu6oUrD vw+1pGLdpIU4S5FmO5PCacntv08Ag4Jn9JXJ2ssRGkDHvq0dBOdehC+zBXZRvwlM4n/PeWzRtZNXQ OQK5INqTKVsXXINqHs6SFKt59/0TjTat9ptWpheYThBe1fE9dnDWdkurMvllRUVKwXmDVp2aebV64 pI=; Date: Wed, 20 May 2026 15:12:53 +0200 Subject: [PATCH v3 01/14] hw/riscv: Register generic riscv[32|64] QOM interfaces MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260520-hw-riscv-cpu-int-v3-1-d1123ea63d9c@rev.ng> References: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> In-Reply-To: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, philmd@linaro.org, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1779282793; l=1825; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=BxMLYt102hTRhZu2+M/TJdxxfMk7L7ES4lUtOC8++7k=; b=XoNLmENxnYG9CzOVSWcRU7ELr2nCmAyGkYp6pwf21Uk9N/DrLRs7tb2jFpLtGs7pUJVxsc3V/ bOsgPClXvyLBuDakis7WNIRGnYrJz/z7y75v67Lc/iTZ42pkZFzd1Z2 X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282635875158501 Defines generic 32- and 64-bit riscv machine interfaces for machines to implement. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- include/hw/riscv/machines-qom.h | 20 ++++++++++++++++++++ target-info-qom.c | 9 +++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qo= m.h new file mode 100644 index 0000000000..69fcf61fd7 --- /dev/null +++ b/include/hw/riscv/machines-qom.h @@ -0,0 +1,20 @@ +/* + * QOM type definitions for riscv32 / riscv64 machines + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_RISCV_MACHINES_QOM_H +#define HW_RISCV_MACHINES_QOM_H + +#include "hw/core/boards.h" + +#define TYPE_TARGET_RISCV32_MACHINE \ + "target-info-riscv32-machine" + +#define TYPE_TARGET_RISCV64_MACHINE \ + "target-info-riscv64-machine" + +#endif diff --git a/target-info-qom.c b/target-info-qom.c index b48714cc77..7958a5cc68 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -13,6 +13,7 @@ #include "qemu/target-info-init.h" #include "qemu/target-info-qom.h" #include "hw/arm/machines-qom.h" +#include "hw/riscv/machines-qom.h" =20 static const TypeInfo target_info_types[] =3D { { @@ -23,6 +24,14 @@ static const TypeInfo target_info_types[] =3D { .name =3D TYPE_TARGET_AARCH64_MACHINE, .parent =3D TYPE_INTERFACE, }, + { + .name =3D TYPE_TARGET_RISCV32_MACHINE, + .parent =3D TYPE_INTERFACE, + }, + { + .name =3D TYPE_TARGET_RISCV64_MACHINE, + .parent =3D TYPE_INTERFACE, + }, }; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- include/hw/riscv/machines-qom.h | 26 ++++++++++++++++++++++++++ target/riscv/machine.c | 17 +++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qo= m.h index 69fcf61fd7..3459437d84 100644 --- a/include/hw/riscv/machines-qom.h +++ b/include/hw/riscv/machines-qom.h @@ -17,4 +17,30 @@ #define TYPE_TARGET_RISCV64_MACHINE \ "target-info-riscv64-machine" =20 +/* + * Interfaces specifying whether a given QOM object is available in + * qemu-system-riscv32, qemu-system-riscv64, or both. + */ + +extern InterfaceInfo riscv32_machine_interfaces[]; +extern InterfaceInfo riscv64_machine_interfaces[]; +extern InterfaceInfo riscv32_64_machine_interfaces[]; + +/* + * Helper macros for defining machines available in qemu-system-riscv32, + * qemu-system-riscv64, or both. + */ + +#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv32_machine_interfaces) + +#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv64_machine_interfaces) + +#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \ + DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ + riscv32_64_machine_interfaces) + #endif diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 13eb292c4a..3d2e3968fd 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -23,6 +23,7 @@ #include "migration/cpu.h" #include "exec/icount.h" #include "target/riscv/debug.h" +#include "hw/riscv/machines-qom.h" =20 static bool pmp_needed(void *opaque) { @@ -503,3 +504,19 @@ const VMStateDescription vmstate_riscv_cpu =3D { NULL } }; + +InterfaceInfo riscv32_machine_interfaces[] =3D { + { TYPE_TARGET_RISCV32_MACHINE }, + { } +}; + +InterfaceInfo riscv64_machine_interfaces[] =3D { + { TYPE_TARGET_RISCV64_MACHINE }, + { } +}; + +InterfaceInfo riscv32_64_machine_interfaces[] =3D { + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, + { } +}; --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1779282534; cv=none; d=zohomail.com; s=zohoarc; b=Y9lKrKOYK9pACwotw0lpoIYx/83eE/jP7c+vPS/QBMaDRR92Ow+Jo6IlzDhwttkhrGNkmE4oD1wz897wBRqVY+q1O3xO466rPxOx4EH1TLfHjY1/pQ38in8tRLlXvK7sk+KpcPjf3Iq/K54fUazkIV8RqTwOMKHvTZ5igEG5nDs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Date: Wed, 20 May 2026 15:12:55 +0200 Subject: [PATCH v3 03/14] hw/riscv: Filter machine types for qemu-system-riscv32/64 binaries MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260520-hw-riscv-cpu-int-v3-3-d1123ea63d9c@rev.ng> References: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> In-Reply-To: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, philmd@linaro.org, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1779282793; l=7890; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=10wGtVHLTsRtNTOAyjXk6VckFcGfrPUL5eVx6i+8dV0=; b=VAZw7mej+C0o6Hi8LmKqHrz3cSpdcYv92CPxBn+hSPxLbZDchGEp69ETW+ghkQ7MMTNwF8QWT AlVX6sXPwOcClIvC3XqyhgwHx226ydlM7YnXem6Rqe18tPUUA7uSTVn X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282536557158500 Register machines able to run in qemu-system-riscv32, qemu-system-riscv64, or both. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis --- hw/riscv/boston-aia.c | 3 ++- hw/riscv/microblaze-v-generic.c | 3 ++- hw/riscv/microchip_pfsoc.c | 2 ++ hw/riscv/opentitan.c | 2 ++ hw/riscv/shakti_c.c | 2 ++ hw/riscv/sifive_e.c | 2 ++ hw/riscv/sifive_u.c | 2 ++ hw/riscv/spike.c | 2 ++ hw/riscv/virt.c | 3 +++ hw/riscv/xiangshan_kmh.c | 2 ++ 10 files changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c index b90da096ea..965d0f5699 100644 --- a/hw/riscv/boston-aia.c +++ b/hw/riscv/boston-aia.c @@ -18,6 +18,7 @@ #include "hw/ide/ahci-pci.h" #include "hw/core/loader.h" #include "hw/riscv/cps.h" +#include "hw/riscv/machines-qom.h" #include "hw/pci-host/xilinx-pcie.h" #include "hw/core/qdev-properties.h" #include "qapi/error.h" @@ -473,4 +474,4 @@ static void boston_mach_class_init(MachineClass *mc) mc->default_cpu_type =3D TYPE_RISCV_CPU_MIPS_P8700; } =20 -DEFINE_MACHINE("boston-aia", boston_mach_class_init) +DEFINE_MACHINE_RISCV64("boston-aia", boston_mach_class_init) diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index b0494b1ac5..d33ac39a68 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -25,6 +25,7 @@ #include "system/address-spaces.h" #include "hw/char/xilinx_uartlite.h" #include "hw/misc/unimp.h" +#include "hw/riscv/machines-qom.h" =20 #define LMB_BRAM_SIZE (128 * KiB) #define MEMORY_BASEADDR 0x80000000 @@ -186,4 +187,4 @@ static void mb_v_generic_machine_init(MachineClass *mc) mc->default_cpus =3D 1; } =20 -DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init) +DEFINE_MACHINE_RISCV32_64("amd-microblaze-v-generic", mb_v_generic_machine= _init) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 743f31f005..5e48a29708 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -49,6 +49,7 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/machines-qom.h" #include "hw/riscv/microchip_pfsoc.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -751,6 +752,7 @@ static const TypeInfo microchip_icicle_kit_machine_type= info =3D { .class_init =3D microchip_icicle_kit_machine_class_init, .instance_init =3D microchip_icicle_kit_machine_instance_init, .instance_size =3D sizeof(MicrochipIcicleKitState), + .interfaces =3D riscv64_machine_interfaces, }; =20 static void microchip_icicle_kit_machine_init_register_types(void) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 309125e854..c8b2f028f2 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -26,6 +26,7 @@ #include "hw/core/boards.h" #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "qemu/units.h" #include "system/system.h" #include "system/address-spaces.h" @@ -335,6 +336,7 @@ static const TypeInfo open_titan_types[] =3D { .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(OpenTitanState), .class_init =3D opentitan_machine_class_init, + .interfaces =3D riscv32_machine_interfaces, } }; =20 diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 49a39b3021..64207c8d00 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "hw/core/boards.h" #include "hw/riscv/shakti_c.h" +#include "hw/riscv/machines-qom.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/intc/sifive_plic.h" @@ -92,6 +93,7 @@ static const TypeInfo shakti_c_machine_type_info =3D { .class_init =3D shakti_c_machine_class_init, .instance_init =3D shakti_c_machine_instance_init, .instance_size =3D sizeof(ShaktiCMachineState), + .interfaces =3D riscv64_machine_interfaces, }; =20 static void shakti_c_machine_type_info_register(void) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1acfea4966..71925583bd 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -40,6 +40,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -167,6 +168,7 @@ static const TypeInfo sifive_e_machine_typeinfo =3D { .class_init =3D sifive_e_machine_class_init, .instance_init =3D sifive_e_machine_instance_init, .instance_size =3D sizeof(SiFiveEState), + .interfaces =3D riscv32_64_machine_interfaces, }; =20 static void sifive_e_machine_init_register_types(void) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7ec67b2565..6a637e3b86 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -51,6 +51,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" @@ -742,6 +743,7 @@ static const TypeInfo sifive_u_machine_typeinfo =3D { .class_init =3D sifive_u_machine_class_init, .instance_init =3D sifive_u_machine_instance_init, .instance_size =3D sizeof(SiFiveUState), + .interfaces =3D riscv32_64_machine_interfaces, }; =20 static void sifive_u_machine_init_register_types(void) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 35c696f891..08ef291b6b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -33,6 +33,7 @@ #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/riscv/machines-qom.h" #include "hw/char/riscv_htif.h" #include "hw/intc/riscv_aclint.h" #include "chardev/char.h" @@ -366,6 +367,7 @@ static const TypeInfo spike_machine_typeinfo =3D { .class_init =3D spike_machine_class_init, .instance_init =3D spike_machine_instance_init, .instance_size =3D sizeof(SpikeState), + .interfaces =3D riscv32_64_machine_interfaces, }; =20 static void spike_machine_init_register_types(void) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 315049bc86..39caf37c01 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -36,6 +36,7 @@ #include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" +#include "hw/riscv/machines-qom.h" #include "hw/riscv/numa.h" #include "kvm/kvm_riscv.h" #include "hw/firmware/smbios.h" @@ -2001,6 +2002,8 @@ static const TypeInfo virt_machine_typeinfo =3D { .instance_size =3D sizeof(RISCVVirtState), .interfaces =3D (const InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, { } }, }; diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 436e51c1c5..76417ba7ab 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -41,6 +41,7 @@ #include "hw/riscv/boot.h" #include "hw/riscv/xiangshan_kmh.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/machines-qom.h" #include "system/system.h" =20 static const MemMapEntry xiangshan_kmh_memmap[] =3D { @@ -211,6 +212,7 @@ static const TypeInfo xiangshan_kmh_machine_info =3D { .parent =3D TYPE_MACHINE, .instance_size =3D sizeof(XiangshanKmhState), .class_init =3D xiangshan_kmh_machine_class_init, + .interfaces =3D riscv64_machine_interfaces, }; =20 static void xiangshan_kmh_machine_register_types(void) --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1779282573; cv=none; d=zohomail.com; s=zohoarc; b=QzT47bBqtgaM70t7AyIKSKhTbSRaWkUzKr3hi980+qgjqftJL4mz5hbYV4xvz10jLblKNh/TknfRkY9K0OaPcvoFkaINrcbrLTqxrpFmCCIv5SXTjcRTczHZ2OyBmPRtXCDOWn1pPRkoRCBfFCMotOWlPJITdT5sSuvQq/GP4hw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779282573; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282575765154100 Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- hw/core/null-machine.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index c52b022d3a..f132a7b89b 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -17,6 +17,7 @@ #include "system/address-spaces.h" #include "hw/core/cpu.h" #include "hw/arm/machines-qom.h" +#include "hw/riscv/machines-qom.h" =20 static void machine_none_init(MachineState *mch) { @@ -59,4 +60,6 @@ static void machine_none_machine_init(MachineClass *mc) DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init, { TYPE_TARGET_AARCH64_MACHINE }, { TYPE_TARGET_ARM_MACHINE }, + { TYPE_TARGET_RISCV32_MACHINE }, + { TYPE_TARGET_RISCV64_MACHINE }, { }) --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; t=1779282793; l=2712; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=+2x91c/ot0C95ECpKcincB2R1tj+hcOjCJaTZEr9mQ8=; b=+gB9xGHErQjW3nT4kXi7FUDdrluQNd93+RMc5J4DEjJhQ8WDIMsN7IISwoTxw0v8AkNGvx3UF wWQM+wrp/uPCvN3Vw8RWoweWAnkLko6bUxXpWjOkreyDmmlQl+NQW2v X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282616780154100 Defines TargetInfo for 32- and 64-bit riscv binaries. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- configs/targets/riscv32-softmmu.c | 26 ++++++++++++++++++++++++++ configs/targets/riscv64-softmmu.c | 26 ++++++++++++++++++++++++++ configs/targets/meson.build | 1 + 3 files changed, 53 insertions(+) diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-so= ftmmu.c new file mode 100644 index 0000000000..752c813077 --- /dev/null +++ b/configs/targets/riscv32-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv32) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "qemu/target-info-init.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" +#include "target/riscv/cpu-param.h" + +static const TargetInfo target_info_riscv32_system =3D { + .target_name =3D "riscv32", + .target_arch =3D SYS_EMU_TARGET_RISCV32, + .long_bits =3D 32, + .cpu_type =3D TYPE_RISCV_CPU, + .machine_typename =3D TYPE_TARGET_RISCV32_MACHINE, + .endianness =3D ENDIAN_MODE_LITTLE, + .page_bits_init =3D TARGET_PAGE_BITS, +}; + +target_info_init(target_info_riscv32_system) diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-so= ftmmu.c new file mode 100644 index 0000000000..5150f0fe9d --- /dev/null +++ b/configs/targets/riscv64-softmmu.c @@ -0,0 +1,26 @@ +/* + * QEMU binary/target API (qemu-system-riscv64) + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/target-info-impl.h" +#include "qemu/target-info-init.h" +#include "hw/riscv/machines-qom.h" +#include "target/riscv/cpu-qom.h" +#include "target/riscv/cpu-param.h" + +static const TargetInfo target_info_riscv64_system =3D { + .target_name =3D "riscv64", + .target_arch =3D SYS_EMU_TARGET_RISCV64, + .long_bits =3D 64, + .cpu_type =3D TYPE_RISCV_CPU, + .machine_typename =3D TYPE_TARGET_RISCV64_MACHINE, + .endianness =3D ENDIAN_MODE_LITTLE, + .page_bits_init =3D TARGET_PAGE_BITS, +}; + +target_info_init(target_info_riscv64_system) diff --git a/configs/targets/meson.build b/configs/targets/meson.build index cca2514eb5..2ab4d27eaf 100644 --- a/configs/targets/meson.build +++ b/configs/targets/meson.build @@ -1,5 +1,6 @@ foreach target : [ 'arm-softmmu', 'aarch64-softmmu', + 'riscv32-softmmu', 'riscv64-softmmu' ] config_target_info +=3D {target : files(target + '.c')} endforeach --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Chao Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/target-info.h | 7 +++++++ target-info.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h index 23c997de54..6c5b714288 100644 --- a/include/qemu/target-info.h +++ b/include/qemu/target-info.h @@ -99,4 +99,11 @@ bool target_ppc64(void); */ bool target_s390x(void); =20 +/** + * target_riscv64: + * + * Returns whether the target architecture is riscv64 + */ +bool target_riscv64(void); + #endif diff --git a/target-info.c b/target-info.c index 28c458fc7a..04c69c41f8 100644 --- a/target-info.c +++ b/target-info.c @@ -93,3 +93,8 @@ bool target_s390x(void) { return target_arch() =3D=3D SYS_EMU_TARGET_S390X; } + +bool target_riscv64(void) +{ + return target_arch() =3D=3D SYS_EMU_TARGET_RISCV64; +} --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=dDcP07ZN1+P+qyXkxHKmye37sUEokR3lgbJbdEcaicE=; b=dvACLaj0zcREaol 1wYePj2rhEUU+LH1zVxHD2GZyyaYbdN3aua5WJ+a5sc0q+it311hrdDXMp6KXWybEMzag9gTXVCKb ijzEI/VY4Iw5vtCH7kDeRMWyKmoq/ZAuc34MXdQXMIQsVly1MvR/NT0dRMKfCwyqeh9kLh4ZOiyOH JI=; Date: Wed, 20 May 2026 15:12:59 +0200 Subject: [PATCH v3 07/14] target/riscv: Replace TYPE_RISCV_CPU_BASE MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260520-hw-riscv-cpu-int-v3-7-d1123ea63d9c@rev.ng> References: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> In-Reply-To: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, philmd@linaro.org, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; 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Replace it with a runtime check. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Chao Liu --- include/hw/riscv/machines-qom.h | 12 ++++++++++++ target/riscv/cpu.h | 6 ------ hw/riscv/microblaze-v-generic.c | 2 +- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- 5 files changed, 15 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qo= m.h index 3459437d84..8396155373 100644 --- a/include/hw/riscv/machines-qom.h +++ b/include/hw/riscv/machines-qom.h @@ -9,7 +9,9 @@ #ifndef HW_RISCV_MACHINES_QOM_H #define HW_RISCV_MACHINES_QOM_H =20 +#include "qemu/target-info.h" #include "hw/core/boards.h" +#include "target/riscv/cpu-qom.h" =20 #define TYPE_TARGET_RISCV32_MACHINE \ "target-info-riscv32-machine" @@ -43,4 +45,14 @@ extern InterfaceInfo riscv32_64_machine_interfaces[]; DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ riscv32_64_machine_interfaces) =20 +/* Default CPU type inferred from target info */ +static inline const char *riscv_default_cpu_type(void) +{ + if (target_riscv64()) { + return TYPE_RISCV_CPU_BASE64; + } else { + return TYPE_RISCV_CPU_BASE32; + } +} + #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fb44f0485d..f521686c43 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -39,12 +39,6 @@ typedef struct CPUArchState CPURISCVState; =20 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU =20 -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - /* * b0: Whether a instruction always raise a store AMO or not. */ diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index d33ac39a68..386c5dce9c 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -183,7 +183,7 @@ static void mb_v_generic_machine_init(MachineClass *mc) mc->init =3D mb_v_generic_init; mc->min_cpus =3D 1; mc->max_cpus =3D 1; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D riscv_default_cpu_type(); mc->default_cpus =3D 1; } =20 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 08ef291b6b..b937cf0fa6 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -343,7 +343,7 @@ static void spike_machine_class_init(ObjectClass *oc, c= onst void *data) mc->init =3D spike_board_init; mc->max_cpus =3D SPIKE_CPUS_MAX; mc->is_default =3D true; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D riscv_default_cpu_type(); mc->possible_cpu_arch_ids =3D riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 39caf37c01..e108e29f63 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1933,7 +1933,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->desc =3D "RISC-V VirtIO board"; mc->init =3D virt_machine_init; mc->max_cpus =3D VIRT_CPUS_MAX; - mc->default_cpu_type =3D TYPE_RISCV_CPU_BASE; + mc->default_cpu_type =3D riscv_default_cpu_type(); mc->block_default_type =3D IF_VIRTIO; mc->no_cdrom =3D 1; mc->pci_allow_0_address =3D true; --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1779282597; cv=none; d=zohomail.com; s=zohoarc; b=ZsrZqvXf7EKWGbmX5B4CqQxjpyGTi4Pas0QRowj8gUwuJK02fEODJGCWLa5wsGxJKBBeBFmxG1t1jvjs8D3KbgDwNrcjp0qeYOQl/Dn6CQ3OyLQ4QmwjPi5YVSrLqOQk8qcFS1/CUtd2QctRO7IIwcB2w9725oMg7IQshloT+KE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779282597; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260520-hw-riscv-cpu-int-v3-8-d1123ea63d9c@rev.ng> References: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> In-Reply-To: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, philmd@linaro.org, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1779282793; l=3280; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=QrxpqMnDo2J81ZPudJyrgp1ZyZwaRixwpojN0+zzb/E=; b=NdNjyy7KVqZUIeirIeuyJCZKuM0XiwUQbYJi+uFT77EYBreoL+vFQd5L7yuFRmynx635KMaiS zAobOEhRmaXB9gACJAMtFQCEDlCO9dCRUK6twvyrwND389J8hq2QIiZ X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282599371158500 KVM fields of CPURISCVState are now always exposed as CONFIG_KVM cannot be used in common code. riscv_cpu_mxl() is changed to return CPURISCVState::misa_mxl unconditionally, as use of target_riscv64() would result in an extra load and compare with TargetInfo::target_arch. We might as well just perform a single load. Likewise, for cpu_recompute_xl(), cpu_address_xl(), and riscv_cpu_sxl(), we opt for returning the corresponding CPURISCVState field with ifdefs for system mode adding extra conditions. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis --- target/riscv/cpu.h | 36 ++++++++---------------------------- 1 file changed, 8 insertions(+), 28 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f521686c43..5dc76f07bf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -493,14 +493,12 @@ struct CPUArchState { hwaddr kernel_addr; hwaddr fdt_addr; =20 -#ifdef CONFIG_KVM /* kvm timer */ bool kvm_timer_dirty; uint64_t kvm_timer_time; uint64_t kvm_timer_compare; uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; -#endif /* CONFIG_KVM */ =20 /* RNMI */ uint64_t mnscratch; @@ -706,14 +704,10 @@ FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32) FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) =20 -#ifdef TARGET_RISCV32 -#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) { return env->misa_mxl; } -#endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) @@ -757,9 +751,6 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, p= rivilege_mode_t mode) } #endif =20 -#if defined(TARGET_RISCV32) -#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) { #if !defined(CONFIG_USER_ONLY) @@ -768,43 +759,32 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState= *env) return env->misa_mxl; #endif } -#endif =20 -#if defined(TARGET_RISCV32) -#define cpu_address_xl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL cpu_address_xl(CPURISCVState *env) { -#ifdef CONFIG_USER_ONLY - return env->xl; -#else - privilege_mode_t mode =3D cpu_address_mode(env); - - return cpu_get_xl(env, mode); +#ifndef CONFIG_USER_ONLY + if (target_riscv64()) { + privilege_mode_t mode =3D cpu_address_mode(env); + return cpu_get_xl(env, mode); + } #endif + return env->xl; } -#endif =20 static inline uint16_t riscv_cpu_xlen(CPURISCVState *env) { return 16 << env->xl; } =20 -#ifdef TARGET_RISCV32 -#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) -#else static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) { -#ifdef CONFIG_USER_ONLY - return env->misa_mxl; -#else +#ifndef CONFIG_USER_ONLY if (env->misa_mxl !=3D MXL_RV32) { return get_field(env->mstatus, MSTATUS64_SXL); } #endif - return MXL_RV32; + return env->misa_mxl; } -#endif =20 /* * Returns the current effective privilege mode. --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=tQzK3CC7C+ww1sRPdg3ltXtkDiLC9xFD8LQ3K03UIEM=; b=xMN4OHbAIxaIQD9 bbdb5i06TUEVbbznGJKvDxOnFrqRcdxw+rC3XXS0aP3wswzKk+1dSBT3nlu9cG12mBzNwo5SHiFu8 x6uVYZ9ebwYEDbVE/+F9H/kq/6B6M2SCXRX6QdHv0vKrA+XI2Ro58/93hEurpM7tdc/qEtMf6qB/J 1s=; Date: Wed, 20 May 2026 15:13:01 +0200 Subject: [PATCH v3 09/14] target/riscv: Replace TARGET_LONG_BITS in header exposed to common code MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260520-hw-riscv-cpu-int-v3-9-d1123ea63d9c@rev.ng> References: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> In-Reply-To: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, philmd@linaro.org, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1779282793; l=4096; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=tlQakTWoAu4ly03jZ5ipYJPIWyGpEaqQOJpXORJwIm0=; b=POJG2Np9xzceXHRELTv/kQi+egBk+22yHXEVb3A1nb6NK+RHy72z2N8C/smNWzMOWgUoDyPdK e6Q3527RM+YALRMW3Hu1hgvWyM5sCmLkuUYM/fl0VlT+t6+bNsjdTu8 X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282573695154100 IRQ_LOCAL_GUEST_MAX depends on TARGET_LONG_BITS and is used in hw/intc/riscv_imsic.c. The macro is replaced by a field in RISCVCPUDef initialized in riscv_cpu_class_base_init(). Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 2 -- hw/intc/riscv_imsic.c | 4 +++- target/riscv/cpu.c | 14 ++++++++++++-- 4 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5dc76f07bf..78b4f47d2d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -559,6 +559,7 @@ typedef struct RISCVCPUDef { int32_t vext_spec; RISCVCPUConfig cfg; bool bare; + uint8_t irq_local_guest_max; const RISCVCSR *custom_csrs; } RISCVCPUDef; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b62dd82fe7..13e052bce2 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -809,8 +809,6 @@ typedef enum RISCVException { #define IRQ_S_GEXT 12 #define IRQ_PMU_OVF 13 #define IRQ_LOCAL_MAX 64 -/* -1 is due to bit zero of hgeip and hgeie being ROZ. */ -#define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 /* RNMI causes */ #define RNMI_MAX 16 diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 3ce9f146c0..d4f57549b1 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -453,13 +453,15 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t= hartid, bool mmode, { DeviceState *dev =3D qdev_new(TYPE_RISCV_IMSIC); CPUState *cpu =3D cpu_by_arch_id(hartid); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(RISCV_CPU(cpu)); uint32_t i; =20 assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1))); if (mmode) { assert(num_pages =3D=3D 1); } else { - assert(num_pages >=3D 1 && num_pages <=3D (IRQ_LOCAL_GUEST_MAX + 1= )); + assert(num_pages >=3D 1 && + num_pages <=3D (mcc->def->irq_local_guest_max + 1)); } assert(IMSIC_MIN_ID <=3D num_ids); assert(num_ids <=3D IMSIC_MAX_ID); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 36f9570f2d..08445cb1d5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1021,6 +1021,7 @@ void riscv_add_satp_mode_properties(Object *obj) =20 static void riscv_cpu_set_irq(void *opaque, int irq, int level) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(opaque); RISCVCPU *cpu =3D RISCV_CPU(opaque); CPURISCVState *env =3D &cpu->env; =20 @@ -1055,7 +1056,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) default: g_assert_not_reached(); } - } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { + } else if (irq < (IRQ_LOCAL_MAX + mcc->def->irq_local_guest_max)) { /* Require H-extension for handling guest local interrupts */ if (!riscv_has_ext(env, RVH)) { g_assert_not_reached(); @@ -1102,7 +1103,7 @@ static void riscv_cpu_init(Object *obj) =20 #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, - IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); + IRQ_LOCAL_MAX + mcc->def->irq_local_guest_max); qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, "riscv.cpu.rnmi", RNMI_MAX); #endif /* CONFIG_USER_ONLY */ @@ -2818,6 +2819,15 @@ static void riscv_cpu_class_base_init(ObjectClass *c= , const void *data) mcc->def =3D g_new0(RISCVCPUDef, 1); } =20 + /* + * RISCVCPUDef::irq_local_guest_max is initialized to + * `target_long_bits()-1` due to bit zero of hgeip and hgeie + * being ROZ. + * + * This value does not vary between CPU types. + */ + mcc->def->irq_local_guest_max =3D target_long_bits() - 1; + if (data) { const RISCVCPUDef *def =3D data; mcc->def->bare |=3D def->bare; --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282572931158500 The function depends on target_ulong and is via the pmu.h header exposed to hw/riscv, this function is only used internally in pmu.c and csr.c, so move it to the internal csr.h header. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis --- target/riscv/csr.h | 3 +++ target/riscv/pmu.h | 2 -- target/riscv/pmu.c | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.h b/target/riscv/csr.h index c791260f83..0454898bb7 100644 --- a/target/riscv/csr.h +++ b/target/riscv/csr.h @@ -99,4 +99,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_= index, target_ulong val); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); =20 +/* PMU CSRs */ +RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, + bool upper_half, uint32_t ctr_idx); #endif /* RISCV_CSR_H */ diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index b4f1e469a2..273d8f3f94 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -36,7 +36,5 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t va= lue, uint32_t ctr_idx); void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, privilege_mode_t newp= riv, bool new_virt); -RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, - bool upper_half, uint32_t ctr_idx); =20 #endif /* RISCV_PMU_H */ diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 3444400bd2..4b7be6164e 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -22,6 +22,7 @@ #include "qemu/timer.h" #include "cpu.h" #include "pmu.h" +#include "target/riscv/csr.h" #include "exec/icount.h" #include "system/device_tree.h" =20 --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1779282613; cv=none; d=zohomail.com; s=zohoarc; b=XpAsUvBajkbtgTuar0dVd5BNoZAkE1O7dURSV2ZHTQRhDa/CuR5RQgpW42Q0s9paVNooCVW6rCEpWjeAcpnb2oAqnSQYi+BP3n/IOALVXUmdnpozV+ZcxCeXwiE2cpM+OAaU+JLEujULTpeKPpm/2hAtmzo6FLEevs6XeQR6kOw= ARC-Message-Signature: i=1; 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Date: Wed, 20 May 2026 15:13:03 +0200 Subject: [PATCH v3 11/14] target/riscv: Stub out kvm functions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260520-hw-riscv-cpu-int-v3-11-d1123ea63d9c@rev.ng> References: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> In-Reply-To: <20260520-hw-riscv-cpu-int-v3-0-d1123ea63d9c@rev.ng> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, philmd@linaro.org, pierrick.bouvier@oss.qualcomm.com, palmer@dabbelt.com, alistair.francis@wdc.com X-Developer-Signature: v=1; a=ed25519-sha256; t=1779282793; l=1527; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=GpfNmK0ODkxi2G+VC/KRFKwa2B0IWnVNhBfX6455AEQ=; b=Yyl5hCDq0Z4dMDn0e8MYvRd0GeZhCcVxdEtozgoUTOtr/J+L6mL0KE3l4iQmjiIv9FEfhC9Cs BTQ0HwJMGTEDin0tpSaiPSG1Knlybv8Lcdnpj+bnLGepEldVEbVSWoI X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282614526154100 Functions used externally by hw/riscv are stubbed out for non-kvm configurations, allowing a single compilation of hw/riscv. Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis --- target/riscv/kvm/kvm-stub.c | 23 +++++++++++++++++++++++ target/riscv/kvm/meson.build | 1 + 2 files changed, 24 insertions(+) diff --git a/target/riscv/kvm/kvm-stub.c b/target/riscv/kvm/kvm-stub.c new file mode 100644 index 0000000000..64e39c96d8 --- /dev/null +++ b/target/riscv/kvm/kvm-stub.c @@ -0,0 +1,23 @@ +/* + * QEMU RISCV specific KVM stubs + * + * Copyright (c) rev.ng Labs Srl. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "target/riscv/kvm/kvm_riscv.h" + +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num) +{ + g_assert_not_reached(); +} + +uint64_t kvm_riscv_get_timebase_frequency(RISCVCPU *cpu) +{ + g_assert_not_reached(); +} diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build index 7e92415091..d3f395f431 100644 --- a/target/riscv/kvm/meson.build +++ b/target/riscv/kvm/meson.build @@ -1 +1,2 @@ +riscv_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c')) --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; t=1779282793; l=947; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=WNPVJcGZF9fEBox/zQpjXcWF3BpmjENPAtKaUoqTTLY=; b=HlCioW3nikMMMXOCaknk2MsXdOgACokTRR/Kpj5aROuej61kZMwTByD+9n5IqIeHjP3v3o9zD GRboYptnP8wBtC/6o229XTwYDqP+K5j1PR5zQUGw4lEWx6L9s1IyQ1K X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282585085158500 Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Pierrick Bouvier --- target/riscv/cpu.h | 1 - target/riscv/internals.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 78b4f47d2d..0c96bb73da 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -26,7 +26,6 @@ #include "exec/cpu-common.h" #include "exec/cpu-interrupt.h" #include "exec/gdbstub.h" -#include "exec/target_long.h" #include "qemu/cpu-float.h" #include "qom/object.h" #include "qemu/int128.h" diff --git a/target/riscv/internals.h b/target/riscv/internals.h index e143a86f97..f2644eb3b6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -20,6 +20,7 @@ #define RISCV_CPU_INTERNALS_H =20 #include "exec/cpu-common.h" +#include "exec/target_long.h" #include "hw/core/registerfields.h" #include "fpu/softfloat-types.h" #include "target/riscv/cpu_bits.h" --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; t=1779282793; l=5218; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=AiIfgMohxCq0zitxwTvSxZavzS40J+AWxrjt2jbb4aA=; b=BwALLlanutVTqEKFjhn5+x+H2ae7hv6/aDlISTHJKl+yo6K0f7wu3jME8XMVsgkSvJ53m66m7 53BBIsHm7IICINIoKbdX61uL8SiIhf5KoIcSVLk24T07HgSGW4AkB5c X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282616748154100 Macros are removed and replaced with inlined ternary statements. The now empty sifive_cpu.h header is then removed. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis Reviewed-by: Chao Liu --- include/hw/riscv/sifive_cpu.h | 31 ------------------------------- include/hw/riscv/sifive_e.h | 1 - include/hw/riscv/sifive_u.h | 1 - hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 7 +++++-- 5 files changed, 7 insertions(+), 36 deletions(-) diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h deleted file mode 100644 index 136799633a..0000000000 --- a/include/hw/riscv/sifive_cpu.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * SiFive CPU types - * - * Copyright (c) 2017 SiFive, Inc. - * Copyright (c) 2019 Bin Meng - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ - -#ifndef HW_SIFIVE_CPU_H -#define HW_SIFIVE_CPU_H - -#if defined(TARGET_RISCV32) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif - -#endif /* HW_SIFIVE_CPU_H */ diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 4cf902ebc0..0f0d407d5d 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -20,7 +20,6 @@ #define HW_SIFIVE_E_H =20 #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_cpu.h" #include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_e_aon.h" #include "hw/core/boards.h" diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e4c9860d50..bfaaf254af 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -24,7 +24,6 @@ #include "hw/dma/sifive_pdma.h" #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_cpu.h" #include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 71925583bd..76505fdc4d 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -151,7 +151,8 @@ static void sifive_e_machine_class_init(ObjectClass *oc= , const void *data) mc->desc =3D "RISC-V Board compatible with SiFive E SDK"; mc->init =3D sifive_e_machine_init; mc->max_cpus =3D 1; - mc->default_cpu_type =3D SIFIVE_E_CPU; + mc->default_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_E51 + : TYPE_RISCV_CPU_SIFIVE_E31; mc->default_ram_id =3D "riscv.sifive.e.ram"; mc->default_ram_size =3D sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6a637e3b86..b1f5bad8aa 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -723,7 +723,8 @@ static void sifive_u_machine_class_init(ObjectClass *oc= , const void *data) mc->init =3D sifive_u_machine_init; mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpu_type =3D SIFIVE_U_CPU; + mc->default_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_U54 + : TYPE_RISCV_CPU_SIFIVE_U34; mc->default_cpus =3D mc->min_cpus; mc->default_ram_id =3D "riscv.sifive.u.ram"; mc->auto_create_sdcard =3D true; @@ -756,6 +757,8 @@ type_init(sifive_u_machine_init_register_types) static void sifive_u_soc_instance_init(Object *obj) { SiFiveUSoCState *s =3D RISCV_U_SOC(obj); + const char *e_cpu_type =3D (target_riscv64()) ? TYPE_RISCV_CPU_SIFIVE_= E51 + : TYPE_RISCV_CPU_SIFIVE_E3= 1; =20 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUS= TER); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); @@ -764,7 +767,7 @@ static void sifive_u_soc_instance_init(Object *obj) TYPE_RISCV_HART_ARRAY); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); - qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); + qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", e_cpu_type); qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); =20 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUS= TER); --=20 2.52.0 From nobody Thu May 28 00:45:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779282577058158500 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Anton Johansson Acked-by: Alistair Francis --- hw/riscv/meson.build | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 533472e22a..8ea5b098eb 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -1,21 +1,21 @@ -riscv_ss =3D ss.source_set() -riscv_ss.add(files('boot.c')) -riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) -riscv_ss.add(files('riscv_hart.c')) -riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) -riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) -riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) -riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( +riscv_common_ss =3D ss.source_set() +riscv_common_ss.add(files('boot.c')) +riscv_common_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c')) +riscv_common_ss.add(files('riscv_hart.c')) +riscv_common_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'= )) +riscv_common_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_common_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c')) +riscv_common_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) +riscv_common_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) +riscv_common_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) +riscv_common_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microc= hip_pfsoc.c')) +riscv_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c= ')) +riscv_common_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( 'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-h= pm.c')) -riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-gen= eric.c')) -riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan= _kmh.c')) +riscv_common_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaz= e-v-generic.c')) +riscv_common_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xi= angshan_kmh.c')) =20 -riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) -riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'= )) +riscv_common_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) +riscv_common_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston= -aia.c')) =20 -hw_arch +=3D {'riscv': riscv_ss} +hw_common_arch +=3D {'riscv': riscv_common_ss} --=20 2.52.0