From: Corvin Köhne <c.koehne@beckhoff.com>

Hi,

Beckhoff has build a board, called CX7200, based on the Xilinx Zynq A9
platform. This commit series adds the Beckhoff CX7200 as new board variant to
QEMU.

The emulation is able to successfully boot an CX7200 image. The image includes
some self tests executed on every boot. Only the cache self test fails due to
QEMU emulating the cache as always being coherent. The self tests include f.e.:

* Network
* Flash
* CCAT DMA + EEPROM [1]
* TwinCAT (Beckhoff's automation control software [2])

[1] https://github.com/beckhoff/ccat
[2] https://www.beckhoff.com/en-us/products/automation/

YannickV (16):
  hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff
  hw/arm/zynq-devcfg: Prevent unintended unlock during initialization
  hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in
    user mode
  hw/dma/zynq-devcfg: Simulate dummy PL reset
  hw/dma/zynq-devcfg: Indicate power-up status of PL
  hw/misc: Add dummy ZYNQ DDR controller
  hw/misc/zynq_slcr: Add logic for DCI configuration
  hw/misc: Add Beckhoff CCAT device
  hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d
  hw/arm/xilinx_zynq: Split xilinx_zynq into header and implementation
    files
  hw/arm/xilinx_zynq: Add flash type as machine class property
  hw/misc/zynq_slcr: Add CPU clock outputs and ratios
  hw/timer,cpu: Add Clock API support to A9MPCore timers
  hw/arm/xilinx_zynq: Make PS frequency configurable
  hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200
  docs/system/arm: Add support for Beckhoff CX7200

 MAINTAINERS                         |  11 +
 docs/system/arm/beckhoff-cx7200.rst |  62 ++++
 docs/system/target-arm.rst          |   1 +
 hw/arm/Kconfig                      |   8 +
 hw/arm/beckhoff_CX7200.c            |  80 ++++++
 hw/arm/meson.build                  |   1 +
 hw/arm/xilinx_zynq.c                |  54 ++--
 hw/block/m25p80.c                   |   3 +-
 hw/cpu/a9mpcore.c                   |  12 +
 hw/dma/xlnx-zynq-devcfg.c           |  27 +-
 hw/misc/Kconfig                     |   6 +
 hw/misc/beckhoff_ccat.c             | 339 ++++++++++++++++++++++
 hw/misc/meson.build                 |   2 +
 hw/misc/xlnx-zynq-ddrc.c            | 421 ++++++++++++++++++++++++++++
 hw/misc/zynq_slcr.c                 |  71 +++++
 hw/timer/a9gtimer.c                 |  18 +-
 hw/timer/arm_mptimer.c              |  20 +-
 include/hw/arm/xilinx_zynq.h        |  38 +++
 include/hw/cpu/a9mpcore.h           |   1 +
 include/hw/misc/xlnx-zynq-ddrc.h    | 147 ++++++++++
 include/hw/timer/a9gtimer.h         |   1 +
 include/hw/timer/arm_mptimer.h      |   2 +
 22 files changed, 1292 insertions(+), 33 deletions(-)
 create mode 100644 docs/system/arm/beckhoff-cx7200.rst
 create mode 100644 hw/arm/beckhoff_CX7200.c
 create mode 100644 hw/misc/beckhoff_ccat.c
 create mode 100644 hw/misc/xlnx-zynq-ddrc.c
 create mode 100644 include/hw/arm/xilinx_zynq.h
 create mode 100644 include/hw/misc/xlnx-zynq-ddrc.h

-- 
2.47.3

On Mon, 18 May 2026 at 08:34, Corvin Köhne <corvin.koehne@gmail.com> wrote:
>
> From: Corvin Köhne <c.koehne@beckhoff.com>
>
> Hi,
>
> Beckhoff has build a board, called CX7200, based on the Xilinx Zynq A9
> platform. This commit series adds the Beckhoff CX7200 as new board variant to
> QEMU.
>
> The emulation is able to successfully boot an CX7200 image. The image includes
> some self tests executed on every boot. Only the cache self test fails due to
> QEMU emulating the cache as always being coherent. The self tests include f.e.:
>
> * Network
> * Flash
> * CCAT DMA + EEPROM [1]
> * TwinCAT (Beckhoff's automation control software [2])
>
> [1] https://github.com/beckhoff/ccat
> [2] https://www.beckhoff.com/en-us/products/automation/
>
> YannickV (16):
>   hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff
>   hw/arm/zynq-devcfg: Prevent unintended unlock during initialization
>   hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in
>     user mode
>   hw/dma/zynq-devcfg: Simulate dummy PL reset
>   hw/dma/zynq-devcfg: Indicate power-up status of PL
>   hw/misc: Add dummy ZYNQ DDR controller
>   hw/misc/zynq_slcr: Add logic for DCI configuration

>   hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d
>   hw/arm/xilinx_zynq: Split xilinx_zynq into header and implementation
>    files

I'm taking these patches into target-arm.next, since they've been
reviewed and most of them are bugfixes to the existing zynq code.
That should make this patchseries a bit smaller for the next round.

I've left code review comments on the others.

thanks
-- PMM