From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779089912; cv=none; d=zohomail.com; s=zohoarc; b=bweV7OWwzcUzEb7YRjgY+mv4oPEHH+Rbx8B0lRwaTqUnw7r9LXJt38aKywfCg3u6krgiApuU9pi92k+3rY4oFQG9SootsSeGVL2JLdNJx805f0MXQGOdsDgeMs1Y5gxsiaPO7xI3CHJqQRLUxIPSStD5fv3Q39qPdHzpXXMXb6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779089912; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bGVucTk00lHJOoHDxhxqBmDjYYXRIxmmMPGfNidYBio=; b=ajm6OfXMLLLxtV/9X30LNGl/5/rUEhavKsIChshXbH7AnWoFUt+RmWt/gkDo8d6peGOL3mG8xeZVh0mQFxC4mdNwzISIGi63U0EPFaywm/8EGVXm/A1tooYQrQqUtfRUoWJTd9KPres1V9HflNER7mB8dFQdHPFKM86Arp5C4Kg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779089912825337.66519782413286; Mon, 18 May 2026 00:38:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wOsUl-0000oR-PJ; Mon, 18 May 2026 03:34:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wOsUL-0000fp-DV for qemu-devel@nongnu.org; Mon, 18 May 2026 03:34:15 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wOsUI-0000C6-42 for qemu-devel@nongnu.org; Mon, 18 May 2026 03:34:08 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-448528f4e69so1068968f8f.3 for ; Mon, 18 May 2026 00:34:05 -0700 (PDT) Received: from PC-DA2D10.beckhoff.com ([2001:9e8:dc08:b284:85e6:f7f4:1a4a:4dfe]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45d9ec3b18fsm32590222f8f.11.2026.05.18.00.34.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 00:34:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1779089644; x=1779694444; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bGVucTk00lHJOoHDxhxqBmDjYYXRIxmmMPGfNidYBio=; b=OGp15DdJIajhT17FkUUlRwq90s2TT+g3whcpl+RXB7+Z5Gq8EeIC6Es5bJKgXGzRLO yUZuFEpG+U7ruuUaYS7dYcTrzYymuABxbzBy6P6+GWNDjQp+GPx/rT9JhCV5q8gnDjoi QTTIaA5+GDque0Y8G+24dTvr7LFjsUKx/17U6MIP2Grp1l7Bv3CBksRWwEM/ryuZlioD iWTzM2QVHmyi5ywyG8Mp6PpPwt63aVFCQRBHLRwqBgh6E3fgNtQXeFtO8ijC9Dgi3b/L 0tRa+6aYwDVPPs6NTIPTh0kWANRrCJujy8hpxp7XHC0lPJQ/ZUf4yAHFYhF8mG63kG54 7JJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779089644; x=1779694444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=bGVucTk00lHJOoHDxhxqBmDjYYXRIxmmMPGfNidYBio=; b=Lwl9leZDbdPW+aVOR2FsxvJwJ6jbDbA64B7hAxSi3mHMEtZ0H9viK3NsRbB2VVHMM7 KCcNShT0MaD6mOpK4JXCPSLJyZs7YpVs8nzKP1RvgOyQNYiyaupQDSGDU8ajQ9XGWQxK NrHafqaZxEqTD+TLlM8yp/pwbVSEDaOyOJrgxH//bw+SVibQLjn2AzYjq957NQ54Npzn 5q5wkXKdSXYgWf9NhZ14jhIUnTNdOMp4KZvO9UMxaP6x5/YBzbIheeoF4Sv8AxLQHGJu NJMpjiTzWG4RkmfjbVxz9f5BXvJ5Dq5iJIdDpHaTGh2p1Co0leLkHNfE9JB8bpLbh4C+ 0cUw== X-Gm-Message-State: AOJu0YyM71whpN5jXKUopQgMzb1PIrEoPan4kSUEb6LpxTF+UhIytWs/ jEuQPrQmizX0gTnLnT+v718Xdd88ZlfX1YQChNagsk7We49hU/upSdEC11Ki2I8j X-Gm-Gg: Acq92OEF5pOdMlfhX7q0VsgPLBjz3Ko7Db8IjB6kRjwWey1OX/sTd3GKvhK0EQpWk9a dN2tkMDKKFLF9gEkizNb4b+DjmqNAvzI8seVr7XehGEkVowOrNuzJNzZoNQAaYN/cKWDL5ulmtw fY4vYJSKqx77UTaz62lIySIhO8hVqC1C9nuEF9ZWm8+hb4CfbN07HoYLmaNBlmJ5ItnKfXwwnCo SGjxghcv+zJLL0mcLRTerZSqhgaokyJQz7SVDz6L5BALkNmJDFmtfXkGBLkUvdGMTkVSyFb+9R9 Mw8Frz/XDTFan+1RRgFMtf4+wSblYONWTrq0rKEsp3EaMIjyIZq/K7nUFeaAnMl2M8Dj7Zw6+Ve 69D+jJPAbQzHWN4DEbqoZn5b20A9aR8to4Z1Eoko0zrTfvs2syUJxEfcxrv3MoDtlKOsGiIkr8m 7swmtDRtS+NQ4F7UVDkV6mguaP0BU36a+bdHQFmqlNn44sAw== X-Received: by 2002:a05:6000:4205:b0:455:7c9f:a49e with SMTP id ffacd0b85a97d-45e5c5bfbc8mr21150969f8f.25.1779089644346; Mon, 18 May 2026 00:34:04 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org, "Edgar E. Iglesias" Subject: [PATCH v7 01/16] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff Date: Mon, 18 May 2026 09:33:46 +0200 Message-ID: <20260518073401.11279-2-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=corvin.koehne@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089915243154100 Content-Type: text/plain; charset="utf-8" From: YannickV A DMA transfer to destination address `0xffffffff` should trigger a bitstream load via the PCAP interface. Currently, this case is not intercepted, causing loaders to enter an infinite loop when polling the status register. This commit adds a check for `0xffffffff` as the destination address. If detected, the relevant status register bits (`DMA_DONE`, `DMA_P_DONE`, and `PCFG_DONE`) are set to indicate a successful bitstream load. If the address is different, the DMA transfer proceeds as usual. A successful load is indicated but nothing is actually done. Guests relying on FPGA functions are still known to fail. This feature is required for the integration of the Beckhoff CX7200 model. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index cf00aa863d..9708200760 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -247,7 +247,14 @@ static uint64_t r_lock_pre_write(RegisterInfo *reg, ui= nt64_t val) static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(reg->opaque); - + if ((s->regs[R_DMA_DST_ADDR]) =3D=3D 0xffffffff) { + DB_PRINT("bitstream loading detected\n"); + s->regs[R_INT_STS] |=3D R_INT_STS_DMA_DONE_MASK | + R_INT_STS_DMA_P_DONE_MASK | + R_INT_STS_PCFG_DONE_MASK; + xlnx_zynq_devcfg_update_ixr(s); + return; + } s->dma_cmd_fifo[s->dma_cmd_fifo_num] =3D (XlnxZynqDevcfgDMACmd) { .src_addr =3D s->regs[R_DMA_SRC_ADDR] & ~0x3UL, .dest_addr =3D s->regs[R_DMA_DST_ADDR] & ~0x3UL, --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 18 May 2026 00:34:05 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org, "Edgar E. Iglesias" Subject: [PATCH v7 02/16] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization Date: Mon, 18 May 2026 09:33:47 +0200 Message-ID: <20260518073401.11279-3-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=corvin.koehne@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089714176154100 Content-Type: text/plain; charset="utf-8" From: YannickV During the emulation startup, all registers are reset, which triggers the `r_unlock_post_write` function with a value of 0. This led to an unintended memory access disable, making the devcfg unusable. During startup, the memory space no longer gets locked. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 9708200760..afe6ffd326 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -221,7 +221,9 @@ static void r_unlock_post_write(RegisterInfo *reg, uint= 64_t val) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(reg->opaque); const char *device_prefix =3D object_get_typename(OBJECT(s)); - + if (device_is_in_reset(DEVICE(s))) { + return; + } if (val =3D=3D R_UNLOCK_MAGIC) { DB_PRINT("successful unlock\n"); s->regs[R_CTRL] |=3D R_CTRL_PCAP_PR_MASK; --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779089843; 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Mon, 18 May 2026 00:34:06 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org, "Edgar E. Iglesias" Subject: [PATCH v7 03/16] hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode Date: Mon, 18 May 2026 09:33:48 +0200 Message-ID: <20260518073401.11279-4-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=corvin.koehne@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089845528158500 Content-Type: text/plain; charset="utf-8" From: YannickV All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Since we can assume that programming is always done, the `PCFG_DONE` flag is always set to 1, so it will not never be cleared. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index afe6ffd326..7370ab941f 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -188,6 +188,8 @@ static void r_ixr_post_write(RegisterInfo *reg, uint64_= t val) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(reg->opaque); =20 + s->regs[R_INT_STS] |=3D R_INT_STS_PCFG_DONE_MASK; + xlnx_zynq_devcfg_update_ixr(s); } =20 --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779089774; cv=none; d=zohomail.com; s=zohoarc; b=FRvexrMc7EAHmKzGUuQyuRksPa3mswabDj/XKkdJkn50a8FTjN9scmCiMs4Lf8AgLhyMSzdRP4W3wjHqGD8TKnjC6iMeL5nRYzklrFAj4V7zQ+9YtjKvUxx8VB06jfSdp2OG1i7ERupNxsWOzK3hnaF/jivvGOGhrTk2BONCiRo= ARC-Message-Signature: i=1; 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Mon, 18 May 2026 00:34:07 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org, "Edgar E. Iglesias" Subject: [PATCH v7 04/16] hw/dma/zynq-devcfg: Simulate dummy PL reset Date: Mon, 18 May 2026 09:33:49 +0200 Message-ID: <20260518073401.11279-5-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=corvin.koehne@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089776885158500 Content-Type: text/plain; charset="utf-8" From: YannickV Setting PCFG_PROG_B should reset the PL. After a reset PCFG_INIT should indicate that the reset is finished successfully. In order to add a MMIO-Device as part of the PL in the Zynq, the reset logic must succeed. The PCFG_INIT flag is now set when the PL reset is triggered by PCFG_PROG_B. Indicating the reset was successful. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 7370ab941f..6b1d96ff80 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -49,6 +49,7 @@ =20 REG32(CTRL, 0x00) FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignor= ed */ + FIELD(CTRL, PCFG_PROG_B, 30, 1) FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlo= ck */ FIELD(CTRL, PCAP_MODE, 26, 1) FIELD(CTRL, MULTIBOOT_EN, 24, 1) @@ -116,6 +117,7 @@ REG32(STATUS, 0x14) FIELD(STATUS, PSS_GTS_USR_B, 11, 1) FIELD(STATUS, PSS_FST_CFG_B, 10, 1) FIELD(STATUS, PSS_CFG_RESET_B, 5, 1) + FIELD(STATUS, PCFG_INIT, 4, 1) =20 REG32(DMA_SRC_ADDR, 0x18) REG32(DMA_DST_ADDR, 0x1C) @@ -204,6 +206,13 @@ static uint64_t r_ctrl_pre_write(RegisterInfo *reg, ui= nt64_t val) val |=3D lock_ctrl_map[i] & s->regs[R_CTRL]; } } + + if (FIELD_EX32(val, CTRL, PCFG_PROG_B)) { + s->regs[R_STATUS] |=3D R_STATUS_PCFG_INIT_MASK; + } else { + s->regs[R_STATUS] &=3D ~R_STATUS_PCFG_INIT_MASK; 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Mon, 18 May 2026 00:34:08 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org, "Edgar E. Iglesias" Subject: [PATCH v7 05/16] hw/dma/zynq-devcfg: Indicate power-up status of PL Date: Mon, 18 May 2026 09:33:50 +0200 Message-ID: <20260518073401.11279-6-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=corvin.koehne@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089938580158500 Content-Type: text/plain; charset="utf-8" From: YannickV It is assumed, that the programmable logic (PL) is always powered during emulation. Therefor the PCFG_POR_B bit in the MCTRL register is set. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 6b1d96ff80..5608460dc7 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -333,7 +333,8 @@ static const RegisterAccessInfo xlnx_zynq_devcfg_regs_i= nfo[] =3D { /* Silicon 3.0 for version field, the mysterious reserved bit 23 * and QEMU platform identifier. */ - .reset =3D 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU= _MASK, + .reset =3D 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | + R_MCTRL_PCFG_POR_B_MASK | R_MCTRL_QEMU_MASK, .ro =3D ~R_MCTRL_INT_PCAP_LPBK_MASK, .rsvd =3D 0x00f00303, }, --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Mon, 18 May 2026 00:34:09 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org Subject: [PATCH v7 06/16] hw/misc: Add dummy ZYNQ DDR controller Date: Mon, 18 May 2026 09:33:51 +0200 Message-ID: <20260518073401.11279-7-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=corvin.koehne@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089936681158500 Content-Type: text/plain; charset="utf-8" From: YannickV A dummy DDR controller for ZYNQ has been added. While all registers are pre= sent, not all are functional. Read and write access is validated, and the user mo= de can be set. This provides a basic DDR controller initialization, preventing system hangs due to endless polling or similar issues. Signed-off-by: YannickV Reviewed-by: Peter Maydell --- MAINTAINERS | 2 + hw/arm/Kconfig | 1 + hw/arm/xilinx_zynq.c | 16 +- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/xlnx-zynq-ddrc.c | 421 +++++++++++++++++++++++++++++++ include/hw/misc/xlnx-zynq-ddrc.h | 147 +++++++++++ 7 files changed, 588 insertions(+), 3 deletions(-) create mode 100644 hw/misc/xlnx-zynq-ddrc.c create mode 100644 include/hw/misc/xlnx-zynq-ddrc.h diff --git a/MAINTAINERS b/MAINTAINERS index 80d28e618d..788b815501 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1150,8 +1150,10 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/*/xilinx_* F: hw/*/cadence_* +F: hw/misc/xlnx-zynq-ddrc.c F: hw/misc/zynq_slcr.c F: hw/adc/zynq-xadc.c +F: include/hw/misc/xlnx-zynq-ddrc.h F: include/hw/misc/zynq_slcr.h F: include/hw/adc/zynq-xadc.h X: hw/ssi/xilinx_* diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 5b198402d5..fb798ccbee 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -289,6 +289,7 @@ config ZYNQ select XILINX_AXI select XILINX_SPI select XILINX_SPIPS + select XLNX_ZYNQ_DDRC select ZYNQ_DEVCFG =20 config ARM_V7M diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 9dcded9219..66a4480cc8 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -201,6 +201,17 @@ static void zynq_set_boot_mode(Object *obj, const char= *str, m->boot_mode =3D mode; } =20 +static void ddr_ctrl_init(uint32_t base) +{ + DeviceState *dev; + SysBusDevice *busdev; + + dev =3D qdev_new("zynq.ddr-ctlr"); + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); +} + static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); @@ -312,6 +323,8 @@ static void zynq_init(MachineState *machine) sysbus_create_varargs("cadence_ttc", 0xF8002000, pic[69-GIC_INTERNAL], pic[70-GIC_INTERNAL], pic[71-GIC_INTERNA= L], NULL); =20 + ddr_ctrl_init(0xF8006000); + gem_init(0xE000B000, pic[54 - GIC_INTERNAL]); gem_init(0xE000C000, pic[77 - GIC_INTERNAL]); =20 @@ -393,9 +406,6 @@ static void zynq_init(MachineState *machine) /* System Watchdog Timer Registers */ create_unimplemented_device("zynq.swdt", 0xF8005000, 4 * KiB); =20 - /* DDR memory controller */ - create_unimplemented_device("zynq.ddrc", 0xF8006000, 4 * KiB); - /* AXI_HP Interface (AFI) */ create_unimplemented_device("zynq.axi_hp0", 0xF8008000, 0x28); create_unimplemented_device("zynq.axi_hp1", 0xF8009000, 0x28); diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 99bdf09219..1543ee6653 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -254,4 +254,7 @@ config IOSB config XLNX_VERSAL_TRNG bool =20 +config XLNX_ZYNQ_DDRC + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index fa6a961ac9..23265f6035 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -97,6 +97,7 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( )) system_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) +system_ss.add(when: 'CONFIG_XLNX_ZYNQ_DDRC', if_true: files('xlnx-zynq-ddr= c.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-= crf.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-= apu-ctrl.c')) system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( diff --git a/hw/misc/xlnx-zynq-ddrc.c b/hw/misc/xlnx-zynq-ddrc.c new file mode 100644 index 0000000000..9e4f2f37a8 --- /dev/null +++ b/hw/misc/xlnx-zynq-ddrc.c @@ -0,0 +1,421 @@ +/* + * QEMU model of the Xilinx Zynq Double Data Rate Controller + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/sysbus.h" +#include "hw/core/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/core/registerfields.h" +#include "system/block-backend.h" +#include "system/address-spaces.h" +#include "system/memory.h" +#include "system/dma.h" +#include "hw/misc/xlnx-zynq-ddrc.h" +#include "migration/vmstate.h" + +#ifndef DDRCTRL_ERR_DEBUG +#define DDRCTRL_ERR_DEBUG 0 +#endif + +static void zynq_ddrctrl_post_write(RegisterInfo *reg, uint64_t val) +{ + DDRCTRLState *s =3D DDRCTRL(reg->opaque); + if (reg->access->addr =3D=3D A_DDRC_CTRL) { + if (val & 0x1) { + s->reg[R_MODE_STS_REG] |=3D + (R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK & 0x1); + } else { + s->reg[R_MODE_STS_REG] &=3D + ~R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK; + } + } +} + +static const RegisterAccessInfo xlnx_zynq_ddrc_regs_info[] =3D { + /* 0x00 - 0x3C: Basic DDRC control and config */ + { .name =3D "DDRC_CTRL", + .addr =3D A_DDRC_CTRL, + .reset =3D 0x00000200, + .post_write =3D zynq_ddrctrl_post_write }, + { .name =3D "TWO_RANK_CFG", + .addr =3D A_TWO_RANK_CFG, + .reset =3D 0x000C1076 }, + { .name =3D "HPR_REG", + .addr =3D A_HPR_REG, + .reset =3D 0x03C0780F }, + { .name =3D "LPR_REG", + .addr =3D A_LPR_REG, + .reset =3D 0x03C0780F }, + { .name =3D "WR_REG", + .addr =3D A_WR_REG, + .reset =3D 0x0007F80F }, + { .name =3D "DRAM_PARAM_REG0", + .addr =3D A_DRAM_PARAM_REG0, + .reset =3D 0x00041016 }, + { .name =3D "DRAM_PARAM_REG1", + .addr =3D A_DRAM_PARAM_REG1, + .reset =3D 0x351B48D9 }, + { .name =3D "DRAM_PARAM_REG2", + .addr =3D A_DRAM_PARAM_REG2, + .reset =3D 0x83015904 }, + { .name =3D "DRAM_PARAM_REG3", + .addr =3D A_DRAM_PARAM_REG3, + .reset =3D 0x250882D0 }, + { .name =3D "DRAM_PARAM_REG4", + .addr =3D A_DRAM_PARAM_REG4, + .reset =3D 0x0000003C }, + { .name =3D "DRAM_INIT_PARAM", + .addr =3D A_DRAM_INIT_PARAM, + .reset =3D 0x00002007 }, + { .name =3D "DRAM_EMR_REG", + .addr =3D A_DRAM_EMR_REG, + .reset =3D 0x00000008 }, + { .name =3D "DRAM_EMR_MR_REG", + .addr =3D A_DRAM_EMR_MR_REG, + .reset =3D 0x00000940 }, + { .name =3D "DRAM_BURST8_RDWR", + .addr =3D A_DRAM_BURST8_RDWR, + .reset =3D 0x00020034 }, + { .name =3D "DRAM_DISABLE_DQ", + .addr =3D A_DRAM_DISABLE_DQ }, + { .name =3D "DRAM_ADDR_MAP_BANK", + .addr =3D A_DRAM_ADDR_MAP_BANK, + .reset =3D 0x00000F77 }, + { .name =3D "DRAM_ADDR_MAP_COL", + .addr =3D A_DRAM_ADDR_MAP_COL, + .reset =3D 0xFFF00000 }, + { .name =3D "DRAM_ADDR_MAP_ROW", + .addr =3D A_DRAM_ADDR_MAP_ROW, + .reset =3D 0x0FF55555 }, + { .name =3D "DRAM_ODT_REG", + .addr =3D A_DRAM_ODT_REG, + .reset =3D 0x00000249 }, + + /* 0x4C - 0x5C: PHY and DLL */ + { .name =3D "PHY_DBG_REG", + .addr =3D A_PHY_DBG_REG }, + { .name =3D "PHY_CMD_TIMEOUT_RDDATA_CPT", + .addr =3D A_PHY_CMD_TIMEOUT_RDDATA_CPT, + .reset =3D 0x00010200 }, + { .name =3D "MODE_STS_REG", + .addr =3D A_MODE_STS_REG }, + { .name =3D "DLL_CALIB", + .addr =3D A_DLL_CALIB, + .reset =3D 0x00000101 }, + { .name =3D "ODT_DELAY_HOLD", + .addr =3D A_ODT_DELAY_HOLD, + .reset =3D 0x00000023 }, + + /* 0x60 - 0x7C: Control registers */ + { .name =3D "CTRL_REG1", + .addr =3D A_CTRL_REG1, + .reset =3D 0x0000003E }, + { .name =3D "CTRL_REG2", + .addr =3D A_CTRL_REG2, + .reset =3D 0x00020000 }, + { .name =3D "CTRL_REG3", + .addr =3D A_CTRL_REG3, + .reset =3D 0x00284027 }, + { .name =3D "CTRL_REG4", + .addr =3D A_CTRL_REG4, + .reset =3D 0x00001610 }, + { .name =3D "CTRL_REG5", + .addr =3D A_CTRL_REG5, + .reset =3D 0x00455111 }, + { .name =3D "CTRL_REG6", + .addr =3D A_CTRL_REG6, + .reset =3D 0x00032222 }, + + /* 0xA0 - 0xB4: Refresh, ZQ, powerdown, misc */ + { .name =3D "CHE_REFRESH_TIMER0", + .addr =3D A_CHE_REFRESH_TIMER0, + .reset =3D 0x00008000 }, + { .name =3D "CHE_T_ZQ", + .addr =3D A_CHE_T_ZQ, + .reset =3D 0x10300802 }, + { .name =3D "CHE_T_ZQ_SHORT_INTERVAL_REG", + .addr =3D A_CHE_T_ZQ_SHORT_INTERVAL_REG, + .reset =3D 0x0020003A }, + { .name =3D "DEEP_PWRDWN_REG", + .addr =3D A_DEEP_PWRDWN_REG }, + { .name =3D "REG_2C", + .addr =3D A_REG_2C }, + { .name =3D "REG_2D", + .addr =3D A_REG_2D, + .reset =3D 0x00000200 }, + + /* 0xB8 - 0xF8: ECC, DFI, etc. */ + { .name =3D "DFI_TIMING", + .addr =3D A_DFI_TIMING, + .reset =3D 0x00200067 }, + { .name =3D "CHE_ECC_CONTROL_REG_OFFSET", + .addr =3D A_CHE_ECC_CONTROL_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_LOG_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_LOG_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_ADDR_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_ADDR_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_DATA_31_0_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_DATA_31_0_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_DATA_63_32_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_DATA_63_32_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_DATA_71_64_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_DATA_71_64_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_LOG_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_LOG_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_ADDR_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_ADDR_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET }, + { .name =3D "CHE_ECC_STATS_REG_OFFSET", + .addr =3D A_CHE_ECC_STATS_REG_OFFSET }, + { .name =3D "ECC_SCRUB", + .addr =3D A_ECC_SCRUB, + .reset =3D 0x00000008 }, + { .name =3D "CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET", + .addr =3D A_CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET }, + { .name =3D "CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET", + .addr =3D A_CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET }, + + /* 0x114 - 0x174: PHY config, ratios, DQS, WE */ + { .name =3D "PHY_RCVER_ENABLE", + .addr =3D A_PHY_RCVER_ENABLE }, + { .name =3D "PHY_CONFIG0", + .addr =3D A_PHY_CONFIG0, + .reset =3D 0x40000001 }, + { .name =3D "PHY_CONFIG1", + .addr =3D A_PHY_CONFIG1, + .reset =3D 0x40000001 }, + { .name =3D "PHY_CONFIG2", + .addr =3D A_PHY_CONFIG2, + .reset =3D 0x40000001 }, + { .name =3D "PHY_CONFIG3", + .addr =3D A_PHY_CONFIG3, + .reset =3D 0x40000001 }, + { .name =3D "PHY_INIT_RATIO0", + .addr =3D A_PHY_INIT_RATIO0 }, + { .name =3D "PHY_INIT_RATIO1", + .addr =3D A_PHY_INIT_RATIO1 }, + { .name =3D "PHY_INIT_RATIO2", + .addr =3D A_PHY_INIT_RATIO2 }, + { .name =3D "PHY_INIT_RATIO3", + .addr =3D A_PHY_INIT_RATIO3 }, + { .name =3D "PHY_RD_DQS_CFG0", + .addr =3D A_PHY_RD_DQS_CFG0, + .reset =3D 0x00000040 }, + { .name =3D "PHY_RD_DQS_CFG1", + .addr =3D A_PHY_RD_DQS_CFG1, + .reset =3D 0x00000040 }, + { .name =3D "PHY_RD_DQS_CFG2", + .addr =3D A_PHY_RD_DQS_CFG2, + .reset =3D 0x00000040 }, + { .name =3D "PHY_RD_DQS_CFG3", + .addr =3D A_PHY_RD_DQS_CFG3, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WR_DQS_CFG0", + .addr =3D A_PHY_WR_DQS_CFG0 }, + { .name =3D "PHY_WR_DQS_CFG1", + .addr =3D A_PHY_WR_DQS_CFG1 }, + { .name =3D "PHY_WR_DQS_CFG2", + .addr =3D A_PHY_WR_DQS_CFG2 }, + { .name =3D "PHY_WR_DQS_CFG3", + .addr =3D A_PHY_WR_DQS_CFG3 }, + { .name =3D "PHY_WE_CFG0", + .addr =3D A_PHY_WE_CFG0, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WE_CFG1", + .addr =3D A_PHY_WE_CFG1, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WE_CFG2", + .addr =3D A_PHY_WE_CFG2, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WE_CFG3", + .addr =3D A_PHY_WE_CFG3, + .reset =3D 0x00000040 }, + + /* 0x17C - 0x194: Write data slaves, misc */ + { .name =3D "WR_DATA_SLV0", + .addr =3D A_WR_DATA_SLV0, + .reset =3D 0x00000080 }, + { .name =3D "WR_DATA_SLV1", + .addr =3D A_WR_DATA_SLV1, + .reset =3D 0x00000080 }, + { .name =3D "WR_DATA_SLV2", + .addr =3D A_WR_DATA_SLV2, + .reset =3D 0x00000080 }, + { .name =3D "WR_DATA_SLV3", + .addr =3D A_WR_DATA_SLV3, + .reset =3D 0x00000080 }, + { .name =3D "REG_64", + .addr =3D A_REG_64, + .reset =3D 0x10020000 }, + { .name =3D "REG_65", + .addr =3D A_REG_65 }, + + /* 0x1A4 - 0x1C4: Misc registers */ + { .name =3D "REG69_6A0", + .addr =3D A_REG69_6A0 }, + { .name =3D "REG69_6A1", + .addr =3D A_REG69_6A1 }, + { .name =3D "REG6C_6D2", + .addr =3D A_REG6C_6D2 }, + { .name =3D "REG6C_6D3", + .addr =3D A_REG6C_6D3 }, + { .name =3D "REG6E_710", + .addr =3D A_REG6E_710 }, + { .name =3D "REG6E_711", + .addr =3D A_REG6E_711 }, + { .name =3D "REG6E_712", + .addr =3D A_REG6E_712 }, + { .name =3D "REG6E_713", + .addr =3D A_REG6E_713 }, + + /* 0x1CC - 0x1E8: DLL, PHY status */ + { .name =3D "PHY_DLL_STS0", + .addr =3D A_PHY_DLL_STS0 }, + { .name =3D "PHY_DLL_STS1", + .addr =3D A_PHY_DLL_STS1 }, + { .name =3D "PHY_DLL_STS2", + .addr =3D A_PHY_DLL_STS2 }, + { .name =3D "PHY_DLL_STS3", + .addr =3D A_PHY_DLL_STS3 }, + { .name =3D "DLL_LOCK_STS", + .addr =3D A_DLL_LOCK_STS }, + { .name =3D "PHY_CTRL_STS", + .addr =3D A_PHY_CTRL_STS }, + { .name =3D "PHY_CTRL_STS_REG2", + .addr =3D A_PHY_CTRL_STS_REG2 }, + + /* 0x200 - 0x2B4: AXI, LPDDR, misc */ + { .name =3D "AXI_ID", + .addr =3D A_AXI_ID }, + { .name =3D "PAGE_MASK", + .addr =3D A_PAGE_MASK }, + { .name =3D "AXI_PRIORITY_WR_PORT0", + .addr =3D A_AXI_PRIORITY_WR_PORT0, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_WR_PORT1", + .addr =3D A_AXI_PRIORITY_WR_PORT1, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_WR_PORT2", + .addr =3D A_AXI_PRIORITY_WR_PORT2, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_WR_PORT3", + .addr =3D A_AXI_PRIORITY_WR_PORT3, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_RD_PORT0", + .addr =3D A_AXI_PRIORITY_RD_PORT0, + .reset =3D 0x000003FF }, + { .name =3D "AXI_PRIORITY_RD_PORT1", + .addr =3D A_AXI_PRIORITY_RD_PORT1, + .reset =3D 0x000003FF }, + { .name =3D "AXI_PRIORITY_RD_PORT2", + .addr =3D A_AXI_PRIORITY_RD_PORT2, + .reset =3D 0x000003FF }, + { .name =3D "AXI_PRIORITY_RD_PORT3", + .addr =3D A_AXI_PRIORITY_RD_PORT3, + .reset =3D 0x000003FF }, + { .name =3D "EXCL_ACCESS_CFG0", + .addr =3D A_EXCL_ACCESS_CFG0 }, + { .name =3D "EXCL_ACCESS_CFG1", + .addr =3D A_EXCL_ACCESS_CFG1 }, + { .name =3D "EXCL_ACCESS_CFG2", + .addr =3D A_EXCL_ACCESS_CFG2 }, + { .name =3D "EXCL_ACCESS_CFG3", + .addr =3D A_EXCL_ACCESS_CFG3 }, + { .name =3D "MODE_REG_READ", + .addr =3D A_MODE_REG_READ }, + { .name =3D "LPDDR_CTRL0", + .addr =3D A_LPDDR_CTRL0 }, + { .name =3D "LPDDR_CTRL1", + .addr =3D A_LPDDR_CTRL1 }, + { .name =3D "LPDDR_CTRL2", + .addr =3D A_LPDDR_CTRL2, + .reset =3D 0x003C0015 }, + { .name =3D "LPDDR_CTRL3", + .addr =3D A_LPDDR_CTRL3, + .reset =3D 0x00000601 }, +}; + +static void zynq_ddrctrl_reset(DeviceState *dev) +{ + DDRCTRLState *s =3D DDRCTRL(dev); + int i; + + for (i =3D 0; i < ZYNQ_DDRCTRL_NUM_REG; ++i) { + register_reset(&s->regs_info[i]); + } +} + +static const MemoryRegionOps ddrctrl_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static const VMStateDescription vmstate_zynq_ddrctrl =3D { + .name =3D "zynq_ddrc", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(reg, DDRCTRLState, ZYNQ_DDRCTRL_NUM_REG), + VMSTATE_END_OF_LIST() + } +}; + +static void zynq_ddrctrl_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + DDRCTRLState *s =3D DDRCTRL(obj); + + s->reg_array =3D + register_init_block32(DEVICE(obj), xlnx_zynq_ddrc_regs_info, + ARRAY_SIZE(xlnx_zynq_ddrc_regs_info), + s->regs_info, s->reg, + &ddrctrl_ops, + DDRCTRL_ERR_DEBUG, + ZYNQ_DDRCTRL_MMIO_SIZE); + + sysbus_init_mmio(sbd, &s->reg_array->mem); +} + +static void zynq_ddrctrl_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_legacy_reset(dc, zynq_ddrctrl_reset); + dc->vmsd =3D &vmstate_zynq_ddrctrl; +} + +static const TypeInfo ddrctrl_info =3D { + .name =3D TYPE_DDRCTRL, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(DDRCTRLState), + .instance_init =3D zynq_ddrctrl_init, + .class_init =3D zynq_ddrctrl_class_init, +}; + +static void ddrctrl_register_types(void) +{ + type_register_static(&ddrctrl_info); +} + +type_init(ddrctrl_register_types) diff --git a/include/hw/misc/xlnx-zynq-ddrc.h b/include/hw/misc/xlnx-zynq-d= drc.h new file mode 100644 index 0000000000..124bff27ac --- /dev/null +++ b/include/hw/misc/xlnx-zynq-ddrc.h @@ -0,0 +1,147 @@ +/* + * QEMU model of the Xilinx Zynq Double Data Rate Controller + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef XLNX_ZYNQ_DDRC_H +#define XLNX_ZYNQ_DDRC_H + +#include "hw/core/sysbus.h" +#include "hw/core/register.h" + +#define TYPE_DDRCTRL "zynq.ddr-ctlr" +OBJECT_DECLARE_SIMPLE_TYPE(DDRCTRLState, DDRCTRL) + +REG32(DDRC_CTRL, 0x00) +REG32(TWO_RANK_CFG, 0x04) +REG32(HPR_REG, 0x08) +REG32(LPR_REG, 0x0C) +REG32(WR_REG, 0x10) +REG32(DRAM_PARAM_REG0, 0x14) +REG32(DRAM_PARAM_REG1, 0x18) +REG32(DRAM_PARAM_REG2, 0x1C) +REG32(DRAM_PARAM_REG3, 0x20) +REG32(DRAM_PARAM_REG4, 0x24) +REG32(DRAM_INIT_PARAM, 0x28) +REG32(DRAM_EMR_REG, 0x2C) +REG32(DRAM_EMR_MR_REG, 0x30) +REG32(DRAM_BURST8_RDWR, 0x34) +REG32(DRAM_DISABLE_DQ, 0x38) +REG32(DRAM_ADDR_MAP_BANK, 0x3C) +REG32(DRAM_ADDR_MAP_COL, 0x40) +REG32(DRAM_ADDR_MAP_ROW, 0x44) +REG32(DRAM_ODT_REG, 0x48) +REG32(PHY_DBG_REG, 0x4C) +REG32(PHY_CMD_TIMEOUT_RDDATA_CPT, 0x50) +REG32(MODE_STS_REG, 0x54) + FIELD(MODE_STS_REG, DDR_REG_DBG_STALL, 3, 3) + FIELD(MODE_STS_REG, DDR_REG_OPERATING_MODE, 0, 2) +REG32(DLL_CALIB, 0x58) +REG32(ODT_DELAY_HOLD, 0x5C) +REG32(CTRL_REG1, 0x60) +REG32(CTRL_REG2, 0x64) +REG32(CTRL_REG3, 0x68) +REG32(CTRL_REG4, 0x6C) +REG32(CTRL_REG5, 0x78) +REG32(CTRL_REG6, 0x7C) +REG32(CHE_REFRESH_TIMER0, 0xA0) +REG32(CHE_T_ZQ, 0xA4) +REG32(CHE_T_ZQ_SHORT_INTERVAL_REG, 0xA8) +REG32(DEEP_PWRDWN_REG, 0xAC) +REG32(REG_2C, 0xB0) +REG32(REG_2D, 0xB4) +REG32(DFI_TIMING, 0xB8) +REG32(CHE_ECC_CONTROL_REG_OFFSET, 0xC4) +REG32(CHE_CORR_ECC_LOG_REG_OFFSET, 0xC8) +REG32(CHE_CORR_ECC_ADDR_REG_OFFSET, 0xCC) +REG32(CHE_CORR_ECC_DATA_31_0_REG_OFFSET, 0xD0) +REG32(CHE_CORR_ECC_DATA_63_32_REG_OFFSET, 0xD4) +REG32(CHE_CORR_ECC_DATA_71_64_REG_OFFSET, 0xD8) +REG32(CHE_UNCORR_ECC_LOG_REG_OFFSET, 0xDC) +REG32(CHE_UNCORR_ECC_ADDR_REG_OFFSET, 0xE0) +REG32(CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, 0xE4) +REG32(CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, 0xE8) +REG32(CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, 0xEC) +REG32(CHE_ECC_STATS_REG_OFFSET, 0xF0) +REG32(ECC_SCRUB, 0xF4) +REG32(CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, 0xF8) +REG32(CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, 0xFC) +REG32(PHY_RCVER_ENABLE, 0x114) +REG32(PHY_CONFIG0, 0x118) +REG32(PHY_CONFIG1, 0x11C) +REG32(PHY_CONFIG2, 0x120) +REG32(PHY_CONFIG3, 0x124) +REG32(PHY_INIT_RATIO0, 0x12C) +REG32(PHY_INIT_RATIO1, 0x130) +REG32(PHY_INIT_RATIO2, 0x134) +REG32(PHY_INIT_RATIO3, 0x138) +REG32(PHY_RD_DQS_CFG0, 0x140) +REG32(PHY_RD_DQS_CFG1, 0x144) +REG32(PHY_RD_DQS_CFG2, 0x148) +REG32(PHY_RD_DQS_CFG3, 0x14C) +REG32(PHY_WR_DQS_CFG0, 0x154) +REG32(PHY_WR_DQS_CFG1, 0x158) +REG32(PHY_WR_DQS_CFG2, 0x15C) +REG32(PHY_WR_DQS_CFG3, 0x160) +REG32(PHY_WE_CFG0, 0x168) +REG32(PHY_WE_CFG1, 0x16C) +REG32(PHY_WE_CFG2, 0x170) +REG32(PHY_WE_CFG3, 0x174) +REG32(WR_DATA_SLV0, 0x17C) +REG32(WR_DATA_SLV1, 0x180) +REG32(WR_DATA_SLV2, 0x184) +REG32(WR_DATA_SLV3, 0x188) +REG32(REG_64, 0x190) +REG32(REG_65, 0x194) +REG32(REG69_6A0, 0x1A4) +REG32(REG69_6A1, 0x1A8) +REG32(REG6C_6D2, 0x1B0) +REG32(REG6C_6D3, 0x1B4) +REG32(REG6E_710, 0x1B8) +REG32(REG6E_711, 0x1BC) +REG32(REG6E_712, 0x1C0) +REG32(REG6E_713, 0x1C4) +REG32(PHY_DLL_STS0, 0x1CC) +REG32(PHY_DLL_STS1, 0x1D0) +REG32(PHY_DLL_STS2, 0x1D4) +REG32(PHY_DLL_STS3, 0x1D8) +REG32(DLL_LOCK_STS, 0x1E0) +REG32(PHY_CTRL_STS, 0x1E4) +REG32(PHY_CTRL_STS_REG2, 0x1E8) +REG32(AXI_ID, 0x200) +REG32(PAGE_MASK, 0x204) +REG32(AXI_PRIORITY_WR_PORT0, 0x208) +REG32(AXI_PRIORITY_WR_PORT1, 0x20C) +REG32(AXI_PRIORITY_WR_PORT2, 0x210) +REG32(AXI_PRIORITY_WR_PORT3, 0x214) +REG32(AXI_PRIORITY_RD_PORT0, 0x218) +REG32(AXI_PRIORITY_RD_PORT1, 0x21C) +REG32(AXI_PRIORITY_RD_PORT2, 0x220) +REG32(AXI_PRIORITY_RD_PORT3, 0x224) +REG32(EXCL_ACCESS_CFG0, 0x294) +REG32(EXCL_ACCESS_CFG1, 0x298) +REG32(EXCL_ACCESS_CFG2, 0x29C) +REG32(EXCL_ACCESS_CFG3, 0x2A0) +REG32(MODE_REG_READ, 0x2A4) +REG32(LPDDR_CTRL0, 0x2A8) +REG32(LPDDR_CTRL1, 0x2AC) +REG32(LPDDR_CTRL2, 0x2B0) +REG32(LPDDR_CTRL3, 0x2B4) + + +#define ZYNQ_DDRCTRL_MMIO_SIZE 0x400 +#define ZYNQ_DDRCTRL_NUM_REG (ZYNQ_DDRCTRL_MMIO_SIZE / 4) + +typedef struct DDRCTRLState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + RegisterInfoArray *reg_array; + uint32_t reg[ZYNQ_DDRCTRL_NUM_REG]; + RegisterInfo regs_info[ZYNQ_DDRCTRL_NUM_REG]; +} DDRCTRLState; +#endif --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779089918; cv=none; d=zohomail.com; s=zohoarc; b=fjJaF9AmRHP4KHDp8OLfnKOT33x6DmAIcYzCQfzCBSC/x/creqbnUQO15pTJLL+mUUjjGcVka4FuaQziCUl96Zow41MsW64lqDXov5e5XClWLRhhHdoVBOWc/Rw/DuDkVBfJdskNjzft2k/TJdNp7pXQVYNspK1d7Um8hNBMbK0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779089918; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 18 May 2026 00:34:10 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org, "Edgar E. Iglesias" Subject: [PATCH v7 07/16] hw/misc/zynq_slcr: Add logic for DCI configuration Date: Mon, 18 May 2026 09:33:52 +0200 Message-ID: <20260518073401.11279-8-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=corvin.koehne@gmail.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089920401158500 Content-Type: text/plain; charset="utf-8" From: YannickV The registers for the digitally controlled impedance (DCI) clock are part of the system level control registers (SLCR). The DONE bit in the status register indicates a successfull DCI calibration. An description of the calibration process can be found here: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/DDR-IOB-Impedance-Cali= bration The DCI control register and status register have been added. As soon as the ENABLE and RESET bit are set, the RESET bit has also been toggled to 0 before and the UPDATE_CONTROL is not set, the DONE bit in the status register is set. If these bits change the DONE bit is reset. Note that the option bits are not taken into consideration. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/misc/zynq_slcr.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index faae98fa02..0ae5d607be 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -180,6 +180,12 @@ REG32(GPIOB_CFG_HSTL, 0xb14) REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) =20 REG32(DDRIOB, 0xb40) +REG32(DDRIOB_DCI_CTRL, 0xb70) + FIELD(DDRIOB_DCI_CTRL, RESET, 0, 1) + FIELD(DDRIOB_DCI_CTRL, ENABLE, 1, 1) + FIELD(DDRIOB_DCI_CTRL, UPDATE_CONTROL, 20, 1) +REG32(DDRIOB_DCI_STATUS, 0xb74) + FIELD(DDRIOB_DCI_STATUS, DONE, 13, 1) #define DDRIOB_LENGTH 14 =20 #define ZYNQ_SLCR_MMIO_SIZE 0x1000 @@ -193,6 +199,8 @@ struct ZynqSLCRState { =20 MemoryRegion iomem; =20 + bool ddriob_dci_ctrl_reset_toggled; + uint32_t regs[ZYNQ_SLCR_NUM_REGS]; =20 Clock *ps_clk; @@ -331,6 +339,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) =20 DB_PRINT("RESET\n"); =20 + s->ddriob_dci_ctrl_reset_toggled =3D false; + s->regs[R_LOCKSTA] =3D 1; /* 0x100 - 0x11C */ s->regs[R_ARM_PLL_CTRL] =3D 0x0001A008; @@ -418,6 +428,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_DDRIOB + 4] =3D s->regs[R_DDRIOB + 5] =3D s->regs[R_DDRIOB += 6] =3D 0x00000e00; s->regs[R_DDRIOB + 12] =3D 0x00000021; + + s->regs[R_DDRIOB_DCI_CTRL] =3D 0x00000020; } =20 static void zynq_slcr_reset_hold(Object *obj, ResetType type) @@ -554,6 +566,25 @@ static void zynq_slcr_write(void *opaque, hwaddr offse= t, (int)offset, (unsigned)val & 0xFFFF); } return; + + case R_DDRIOB_DCI_CTRL: + if (!FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + FIELD_EX32(s->regs[R_DDRIOB_DCI_CTRL], DDRIOB_DCI_CTRL, RESET)= ) { + + s->ddriob_dci_ctrl_reset_toggled =3D true; + DB_PRINT("DDRIOB DCI CTRL RESET was toggled\n"); + } + + if (FIELD_EX32(val, DDRIOB_DCI_CTRL, ENABLE) && + FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + !FIELD_EX32(val, DDRIOB_DCI_CTRL, UPDATE_CONTROL) && + s->ddriob_dci_ctrl_reset_toggled) { + + s->regs[R_DDRIOB_DCI_STATUS] |=3D R_DDRIOB_DCI_STATUS_DONE_MAS= K; + } else { + s->regs[R_DDRIOB_DCI_STATUS] &=3D ~R_DDRIOB_DCI_STATUS_DONE_MA= SK; + } + break; } =20 if (s->regs[R_LOCKSTA]) { --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779089759; cv=none; d=zohomail.com; s=zohoarc; b=M5R86M8TQIyb397nvQyYMpAWkKUcjw5sH5K6iicx9kRCA0oT7cOxbwXfE6q5LG2O0HrqGmQjZzYvQMQstQ7dG1+A9aO6FLYpHGo3s4eGlUL3NDCyiyrqYQAu00Ne5f/xO7rkl4G0Gskpjdm9XpHNIp7hOOhoPmT+mITf7LL/rBo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779089759; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 18 May 2026 00:34:11 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org Subject: [PATCH v7 08/16] hw/misc: Add Beckhoff CCAT device Date: Mon, 18 May 2026 09:33:53 +0200 Message-ID: <20260518073401.11279-9-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=corvin.koehne@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089762996158500 Content-Type: text/plain; charset="utf-8" From: YannickV This adds the Beckhoff Communication Controller (CCAT). The information block, EEPROM interface and DMA controller are currently implemented. The EEPROM provides production information for Beckhoff Devices. An EEPORM binary must therefor be handed over. It should be aligned to a power of two. If no EEPROM binary is handed over an empty EEPROM of size 4096 is initialized. This device is needed for the Beckhoff CX7200 board emulation. Signed-off-by: YannickV --- hw/misc/Kconfig | 3 + hw/misc/beckhoff_ccat.c | 339 ++++++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 343 insertions(+) create mode 100644 hw/misc/beckhoff_ccat.c diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 1543ee6653..2217b2005b 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -257,4 +257,7 @@ config XLNX_VERSAL_TRNG config XLNX_ZYNQ_DDRC bool =20 +config BECKHOFF_CCAT + bool + source macio/Kconfig diff --git a/hw/misc/beckhoff_ccat.c b/hw/misc/beckhoff_ccat.c new file mode 100644 index 0000000000..a29e9f6166 --- /dev/null +++ b/hw/misc/beckhoff_ccat.c @@ -0,0 +1,339 @@ +/* + * Beckhoff Communication Controller Emulation + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/sysbus.h" +#include "qemu/units.h" +#include "hw/core/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "system/block-backend.h" +#include "system/address-spaces.h" +#include "system/memory.h" +#include "system/dma.h" +#include "qemu/error-report.h" +#include "block/block.h" +#include "block/block_int.h" +#include "block/qdict.h" +#include "hw/block/block.h" +#include "migration/vmstate.h" +#include "qemu/bswap.h" + +#ifndef CCAT_ERR_DEBUG +#define CCAT_ERR_DEBUG 0 +#endif + +#define TYPE_BECKHOFF_CCAT "beckhoff-ccat" +OBJECT_DECLARE_SIMPLE_TYPE(BeckhoffCcat, BECKHOFF_CCAT) + +#define MAX_NUM_SLOTS 32 +#define CCAT_FUNCTION_BLOCK_SIZE 16 + +#define CCAT_EEPROM_OFFSET 0x100 +#define CCAT_DMA_OFFSET 0x8000 + +#define CCAT_MEM_SIZE (64 * KiB) +#define CCAT_DMA_SIZE 0x800 +#define CCAT_EEPROM_SIZE 0x20 + +#define EEPROM_MEMORY_SIZE 0x1000 + +#define EEPROM_CMD_OFFSET (CCAT_EEPROM_OFFSET + 0x00) + #define EEPROM_CMD_WRITE_MASK 0x2 + #define EEPROM_CMD_READ_MASK 0x1 +#define EEPROM_ADR_OFFSET (CCAT_EEPROM_OFFSET + 0x04) +#define EEPROM_DATA_OFFSET (CCAT_EEPROM_OFFSET + 0x08) + +#define DMA_BUFFER_OFFSET (CCAT_DMA_OFFSET + 0x00) +#define DMA_DIRECTION_OFFSET (CCAT_DMA_OFFSET + 0x7c0) + #define DMA_DIRECTION_MASK 1 +#define DMA_TRANSFER_OFFSET (CCAT_DMA_OFFSET + 0x7c4) +#define DMA_HOST_ADR_OFFSET (CCAT_DMA_OFFSET + 0x7c8) +#define DMA_TRANSFER_LENGTH_OFFSET (CCAT_DMA_OFFSET + 0x7cc) + +/* + * The informationblock is always located at address 0x0. + * Address and size are therefor replaced by two identifiers. + * The Parameter give information about the maximal number of + * function slots and the creation date (in this case 01.01.2001) + */ +#define CCAT_ID_1 0x88a4 +#define CCAT_ID_2 0x54414343 +#define CCAT_INFO_BLOCK_PARAMS ((MAX_NUM_SLOTS << 0) | (0x1 << 8) | \ + (0x1 << 16) | (0x1 << 24)) + +#define CCAT_FUN_TYPE_ENTRY 0x0001 +#define CCAT_FUN_TYPE_EEPROM 0x0012 +#define CCAT_FUN_TYPE_DMA 0x0013 + +typedef struct BeckhoffCcat { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint8_t mem[CCAT_MEM_SIZE]; + + BlockBackend *eeprom_blk; + uint8_t *eeprom_storage; + uint32_t eeprom_size; +} BeckhoffCcat; + +static void sync_eeprom(BeckhoffCcat *s) +{ + if (!s->eeprom_blk) { + return; + } + blk_pwrite(s->eeprom_blk, 0, s->eeprom_size, s->eeprom_storage, 0); +} + +static uint64_t beckhoff_ccat_eeprom_read(void *opaque, hwaddr addr, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + return ldn_le_p(&s->mem[addr], size); +} + +static void beckhoff_ccat_eeprom_write(void *opaque, hwaddr addr, uint64_t= val, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + uint64_t eeprom_adr; + uint64_t buf; + uint32_t bytes_to_read; + + switch (addr) { + case EEPROM_CMD_OFFSET: + eeprom_adr =3D ldl_le_p(&s->mem[EEPROM_ADR_OFFSET]); + eeprom_adr =3D (eeprom_adr * 2) % s->eeprom_size; + if (val & EEPROM_CMD_READ_MASK) { + buf =3D 0; + bytes_to_read =3D 8; + if (eeprom_adr > s->eeprom_size - 8) { + bytes_to_read =3D s->eeprom_size - eeprom_adr; + } + buf =3D ldn_le_p(s->eeprom_storage + eeprom_adr, bytes_to_read= ); + stq_le_p(&s->mem[EEPROM_DATA_OFFSET], buf); + } else if (val & EEPROM_CMD_WRITE_MASK) { + buf =3D ldl_le_p(&s->mem[EEPROM_DATA_OFFSET]); + stw_le_p((uint16_t *)(s->eeprom_storage + eeprom_adr), buf); + sync_eeprom(s); + } + break; + default: + stn_le_p(&s->mem[addr], size, val); + } +} + +static uint64_t beckhoff_ccat_dma_read(void *opaque, hwaddr addr, unsigned= size) +{ + BeckhoffCcat *s =3D opaque; + + switch (addr) { + case DMA_TRANSFER_OFFSET: + if (s->mem[DMA_TRANSFER_OFFSET] & 0x1) { + s->mem[DMA_TRANSFER_OFFSET] =3D 0; + } + break; + } + return ldn_le_p(&s->mem[addr], size); +} + +static void beckhoff_ccat_dma_write(void *opaque, hwaddr addr, uint64_t va= l, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + dma_addr_t dmaAddr; + uint8_t len; + uint8_t *mem_buf; + + switch (addr) { + case DMA_TRANSFER_OFFSET: + len =3D s->mem[DMA_TRANSFER_LENGTH_OFFSET]; + mem_buf =3D &s->mem[DMA_BUFFER_OFFSET]; + dmaAddr =3D ldl_le_p(&s->mem[DMA_HOST_ADR_OFFSET]); + if (s->mem[DMA_DIRECTION_OFFSET] & DMA_DIRECTION_MASK) { + dma_memory_read(&address_space_memory, dmaAddr, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } else { + /* + * The write transfer uses Host DMA Address + 8 as the target + * offset, as described in the CCAT manual Version 0.0.41 + * section 20.2. + */ + dma_memory_write(&address_space_memory, dmaAddr + 8, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } + break; + } + stn_le_p(&s->mem[addr], size, val); +} + +static uint64_t beckhoff_ccat_read(void *opaque, hwaddr addr, unsigned siz= e) +{ + BeckhoffCcat *s =3D opaque; + uint64_t val =3D 0; + + assert(addr <=3D CCAT_MEM_SIZE - size); + + if (addr >=3D CCAT_EEPROM_OFFSET && + addr <=3D CCAT_EEPROM_OFFSET + s->eeprom_size) { + return beckhoff_ccat_eeprom_read(opaque, addr, size); + } else if (addr >=3D CCAT_DMA_OFFSET && + addr <=3D CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + return beckhoff_ccat_dma_read(opaque, addr, size); + } else { + val =3D ldn_le_p(&s->mem[addr], size); + } + + return val; +} + +static void beckhoff_ccat_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + + assert(addr <=3D CCAT_MEM_SIZE - size); + + if (addr >=3D CCAT_EEPROM_OFFSET && + addr <=3D CCAT_EEPROM_OFFSET + s->eeprom_size) { + beckhoff_ccat_eeprom_write(opaque, addr, val, size); + } else if (addr >=3D CCAT_DMA_OFFSET && + addr <=3D CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + beckhoff_ccat_dma_write(opaque, addr, val, size); + } else { + stn_le_p(&s->mem[addr], size, val); + } +} + +static const MemoryRegionOps beckhoff_ccat_ops =3D { + .read =3D beckhoff_ccat_read, + .write =3D beckhoff_ccat_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + +static void beckhoff_ccat_reset(DeviceState *dev) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(dev); + + memset(&s->mem[0], 0, MAX_NUM_SLOTS * CCAT_FUNCTION_BLOCK_SIZE); + + size_t offset =3D 0 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_ENTRY); + stw_le_p(&s->mem[offset + 2], 0x0001); + stl_le_p(&s->mem[offset + 4], CCAT_INFO_BLOCK_PARAMS); + stl_le_p(&s->mem[offset + 8], CCAT_ID_1); + stl_le_p(&s->mem[offset + 12], CCAT_ID_2); + + offset =3D 11 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_EEPROM); + stw_le_p(&s->mem[offset + 2], 0x0001); + stl_le_p(&s->mem[offset + 4], 0); + stl_le_p(&s->mem[offset + 8], CCAT_EEPROM_OFFSET); + stl_le_p(&s->mem[offset + 12], CCAT_EEPROM_SIZE); + + offset =3D 15 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_DMA); + stw_le_p(&s->mem[offset + 2], 0x0000); + stl_le_p(&s->mem[offset + 4], 0); + stl_le_p(&s->mem[offset + 8], CCAT_DMA_OFFSET); + stl_le_p(&s->mem[offset + 12], CCAT_DMA_SIZE); +} + +static void beckhoff_ccat_realize(DeviceState *dev, Error **errp) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(dev); + BlockBackend *blk; + + blk =3D s->eeprom_blk; + + if (blk) { + uint64_t blk_size =3D blk_getlength(blk); + if (!is_power_of_2(blk_size)) { + error_setg(errp, "Blockend size is not a power of two."); + return; + } + + if (blk_size < 512) { + error_setg(errp, "Blockend size is too small."); + return; + } else { + blk_set_perm(blk, BLK_PERM_WRITE, BLK_PERM_ALL, errp); + + s->eeprom_size =3D blk_size; + s->eeprom_blk =3D blk; + s->eeprom_storage =3D blk_blockalign(s->eeprom_blk, s->eeprom_= size); + + if (!blk_check_size_and_read_all(s->eeprom_blk, DEVICE(s), + s->eeprom_storage, s->eeprom_= size, + errp)) { + return; + } + } + } else { + s->eeprom_size =3D EEPROM_MEMORY_SIZE; + s->eeprom_storage =3D blk_blockalign(NULL, s->eeprom_size); + memset(s->eeprom_storage, 0x00, s->eeprom_size); + } +} + +static void beckhoff_ccat_init(Object *obj) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &beckhoff_ccat_ops, s, + TYPE_BECKHOFF_CCAT, CCAT_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription vmstate_beckhoff_ccat =3D { + .name =3D "beckhoff-ccat", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8_ARRAY(mem, BeckhoffCcat, CCAT_MEM_SIZE), + VMSTATE_UINT32(eeprom_size, BeckhoffCcat), + VMSTATE_VBUFFER_UINT32(eeprom_storage, BeckhoffCcat, 1, NULL, + eeprom_size), + VMSTATE_END_OF_LIST() + } +}; + +static const Property beckhoff_ccat_properties[] =3D { + DEFINE_PROP_DRIVE("eeprom", BeckhoffCcat, eeprom_blk), +}; + +static void beckhoff_ccat_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D beckhoff_ccat_realize; + device_class_set_legacy_reset(dc, beckhoff_ccat_reset); + dc->vmsd =3D &vmstate_beckhoff_ccat; + device_class_set_props(dc, beckhoff_ccat_properties); +} + +static const TypeInfo beckhoff_ccat_info =3D { + .name =3D TYPE_BECKHOFF_CCAT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(BeckhoffCcat), + .instance_init =3D beckhoff_ccat_init, + .class_init =3D beckhoff_ccat_class_init, +}; + +static void beckhoff_ccat_register_types(void) +{ + type_register_static(&beckhoff_ccat_info); +} + +type_init(beckhoff_ccat_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 23265f6035..8e1e6e7586 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -15,6 +15,7 @@ system_ss.add(when: 'CONFIG_PL310', if_true: files('arm_l= 2x0.c')) system_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integra= tor_debug.c')) system_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c')) system_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) +system_ss.add(when: 'CONFIG_BECKHOFF_CCAT', if_true: files('beckhoff_ccat.= c')) =20 system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c')) =20 --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 18 May 2026 00:34:12 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org Subject: [PATCH v7 09/16] hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d Date: Mon, 18 May 2026 09:33:54 +0200 Message-ID: <20260518073401.11279-10-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=corvin.koehne@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089785001158500 Content-Type: text/plain; charset="utf-8" From: YannickV The is25lp016d has 4 Block Write Protect Bits. BP3 specifies whether the upper or lower range should be protected. Therefore, we add the HAS_SR_TB flag to the is25lp016d flags. Signed-off-by: YannickV Reviewed-by: Peter Maydell --- hw/block/m25p80.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index b8a2543c0b..4a4cda6602 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -217,7 +217,8 @@ static const FlashPartInfo known_devices[] =3D { /* ISSI */ { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, - { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, + { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, + ER_4K | HAS_SR_TB) }, { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 18 May 2026 00:34:13 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org Subject: [PATCH v7 10/16] hw/arm/xilinx_zynq: Split xilinx_zynq into header and implementation files Date: Mon, 18 May 2026 09:33:55 +0200 Message-ID: <20260518073401.11279-11-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=corvin.koehne@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089825538154101 Content-Type: text/plain; charset="utf-8" From: YannickV Create xilinx_zynq.h header file to expose ZynqMachineState and related definitions for machine inheritance. This enables creation of derived machines based on the Zynq platform. Signed-off-by: YannickV Reviewed-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 13 +------------ include/hw/arm/xilinx_zynq.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 12 deletions(-) create mode 100644 include/hw/arm/xilinx_zynq.h diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 66a4480cc8..6c83439017 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -41,9 +41,7 @@ #include "exec/tswap.h" #include "target/arm/cpu-qom.h" #include "qapi/visitor.h" - -#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") -OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) +#include "hw/arm/xilinx_zynq.h" =20 /* board base frequency: 33.333333 MHz */ #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) @@ -87,15 +85,6 @@ static const int dma_irqs[8] =3D { 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 0xe5801000 + (addr) =20 -#define ZYNQ_MAX_CPUS 2 - -struct ZynqMachineState { - MachineState parent; - Clock *ps_clk; - ARMCPU *cpu[ZYNQ_MAX_CPUS]; - uint8_t boot_mode; -}; - static void zynq_write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h new file mode 100644 index 0000000000..cefb7789ff --- /dev/null +++ b/include/hw/arm/xilinx_zynq.h @@ -0,0 +1,30 @@ +/* + * Xilinx Zynq Baseboard System emulation. + * + * Copyright (c) 2010 Xilinx. + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.= com) + * Copyright (c) 2012 Petalogix Pty Ltd. + * Written by Haibing Ma + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_ARM_ZYNQ_H +#define QEMU_ARM_ZYNQ_H + +#include "target/arm/cpu-qom.h" +#include "hw/core/qdev-clock.h" + +#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") +OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) + +#define ZYNQ_MAX_CPUS 2 + +struct ZynqMachineState { + MachineState parent; + Clock *ps_clk; + ARMCPU *cpu[ZYNQ_MAX_CPUS]; + uint8_t boot_mode; +}; + +#endif /* QEMU_ARM_ZYNQ_H */ --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779089787; cv=none; d=zohomail.com; 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Mon, 18 May 2026 00:34:14 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org Subject: [PATCH v7 11/16] hw/arm/xilinx_zynq: Add flash type as machine class property Date: Mon, 18 May 2026 09:33:56 +0200 Message-ID: <20260518073401.11279-12-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=corvin.koehne@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089789142158500 Content-Type: text/plain; charset="utf-8" From: YannickV Introduce ZynqMachineClass with qspi_flash_type field to allow different Zynq-based machines to specify their flash device type. The base Zynq machine defaults to n25q128. Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 21 ++++++++++++++++----- include/hw/arm/xilinx_zynq.h | 8 +++++++- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 6c83439017..52c9e41a76 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -120,7 +120,8 @@ static void gem_init(uint32_t base, qemu_irq irq) } =20 static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, - bool is_qspi, int unit0) + bool is_qspi, int unit0, + const char *flash_type) { int unit =3D unit0; DeviceState *dev; @@ -152,7 +153,11 @@ static inline int zynq_init_spi_flashes(uint32_t base_= addr, qemu_irq irq, =20 for (j =3D 0; j < num_ss; ++j) { DriveInfo *dinfo =3D drive_get(IF_MTD, 0, unit++); - flash_dev =3D qdev_new("n25q128"); + + if (!flash_type || !flash_type[0]) { + flash_type =3D "n25q128"; + } + flash_dev =3D qdev_new(flash_type); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), @@ -204,6 +209,7 @@ static void ddr_ctrl_init(uint32_t base) static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); + ZynqMachineClass *zmc =3D ZYNQ_MACHINE_GET_CLASS(machine); MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *ocm_ram =3D g_new(MemoryRegion, 1); DeviceState *dev, *slcr; @@ -283,9 +289,12 @@ static void zynq_init(MachineState *machine) pic[n] =3D qdev_get_gpio_in(dev, n); } =20 - n =3D zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false,= 0); - n =3D zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false,= n); - n =3D zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, = n); + n =3D zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false,= 0, + zmc->qspi_flash_type); + n =3D zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false,= n, + zmc->qspi_flash_type); + n =3D zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, = n, + zmc->qspi_flash_type); =20 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]= ); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]= ); @@ -460,6 +469,7 @@ static void zynq_machine_class_init(ObjectClass *oc, co= nst void *data) NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); + ZynqMachineClass *zmc =3D ZYNQ_MACHINE_CLASS(oc); ObjectProperty *prop; mc->desc =3D "Xilinx Zynq 7000 Platform Baseboard for Cortex-A9"; mc->init =3D zynq_init; @@ -473,6 +483,7 @@ static void zynq_machine_class_init(ObjectClass *oc, co= nst void *data) "Supported boot modes:" " jtag qspi sd nor"); object_property_set_default_str(prop, "qspi"); + zmc->qspi_flash_type =3D "n25q128"; } =20 static const TypeInfo zynq_machine_type =3D { diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h index cefb7789ff..662b390431 100644 --- a/include/hw/arm/xilinx_zynq.h +++ b/include/hw/arm/xilinx_zynq.h @@ -12,11 +12,12 @@ #ifndef QEMU_ARM_ZYNQ_H #define QEMU_ARM_ZYNQ_H =20 +#include "hw/core/boards.h" #include "target/arm/cpu-qom.h" #include "hw/core/qdev-clock.h" =20 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") -OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) +OBJECT_DECLARE_TYPE(ZynqMachineState, ZynqMachineClass, ZYNQ_MACHINE) =20 #define ZYNQ_MAX_CPUS 2 =20 @@ -27,4 +28,9 @@ struct ZynqMachineState { uint8_t boot_mode; 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Mon, 18 May 2026 00:34:15 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org Subject: [PATCH v7 12/16] hw/misc/zynq_slcr: Add CPU clock outputs and ratios Date: Mon, 18 May 2026 09:33:57 +0200 Message-ID: <20260518073401.11279-13-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=corvin.koehne@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089915300154100 Content-Type: text/plain; charset="utf-8" From: YannickV Add CPU clock outs und derive the related domains from the base CPU clock ration. This makes the CPU clock domains visible and keeps their ratios consistent with the hardware clock tree. We also need to set the reset values during realization to ensure CPU clocks are properly enabled at startup. Without this, CPU clocks would have a frequency of 0 Hz, which causes problems in the a9mpcore timer implementations. Signed-off-by: YannickV --- hw/misc/zynq_slcr.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 0ae5d607be..43e4cc74fe 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -61,6 +61,13 @@ REG32(DDR_PLL_CFG, 0x114) REG32(IO_PLL_CFG, 0x118) =20 REG32(ARM_CLK_CTRL, 0x120) + FIELD(ARM_CLK_CTRL, CPU_PERI_CLKACT, 28, 1); + FIELD(ARM_CLK_CTRL, CPU_1XCLKACT, 27, 1); + FIELD(ARM_CLK_CTRL, CPU_2XCLKACT, 26, 1); + FIELD(ARM_CLK_CTRL, CPU_3OR2XCLKACT, 25, 1); + FIELD(ARM_CLK_CTRL, CPU_6OR4XCLKACT, 24, 1); + FIELD(ARM_CLK_CTRL, DIVISOR, 8, 6); + FIELD(ARM_CLK_CTRL, SRCSEL, 4, 2); REG32(DDR_CLK_CTRL, 0x124) REG32(DCI_CLK_CTRL, 0x128) REG32(APER_CLK_CTRL, 0x12c) @@ -98,6 +105,7 @@ FPGA_CTRL_REGS(3, 0x1a0) REG32(BANDGAP_TRIP, 0x1b8) REG32(PLL_PREDIVISOR, 0x1c0) REG32(CLK_621_TRUE, 0x1c4) + FIELD(CLK_621_TRUE, CLK_621_TRUE, 0, 1) =20 REG32(PSS_RST_CTRL, 0x200) FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1) @@ -206,6 +214,10 @@ struct ZynqSLCRState { Clock *ps_clk; Clock *uart0_ref_clk; Clock *uart1_ref_clk; + Clock *cpu_1x; + Clock *cpu_2x; + Clock *cpu_3x2x; + Clock *cpu_6x4x; uint8_t boot_mode; }; =20 @@ -286,14 +298,31 @@ static void zynq_slcr_compute_clocks_internal(ZynqSLC= RState *s, uint64_t ps_clk) uint64_t io_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTR= L]); uint64_t arm_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_C= TRL]); uint64_t ddr_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_C= TRL]); + uint64_t cpu_base; =20 uint64_t uart_mux[4] =3D {io_pll, io_pll, arm_pll, ddr_pll}; + uint64_t cpu_mux[4] =3D {arm_pll, arm_pll, ddr_pll, io_pll}; + + bool use_621 =3D FIELD_EX32(s->regs[R_CLK_621_TRUE], CLK_621_TRUE, + CLK_621_TRUE); + /* Select 6:2:1 (true) or 4:2:1 (false) CPU clock ratios. */ + uint32_t ratio_6x4x =3D use_621 ? 6 : 4; + uint32_t ratio_3x2x =3D use_621 ? 3 : 2; + =20 /* compute uartX reference clocks */ clock_set(s->uart0_ref_clk, ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); clock_set(s->uart1_ref_clk, ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); + + /* Base is CPU clock (6x/4x domain). Derive other CPU domains via rati= os. */ + cpu_base =3D ZYNQ_COMPUTE_CLK(s, cpu_mux, R_ARM_CLK_CTRL, CPU_6OR4XCLK= ACT); + + clock_set(s->cpu_6x4x, cpu_base); + clock_set(s->cpu_3x2x, cpu_base * ratio_6x4x / ratio_3x2x); + clock_set(s->cpu_2x, cpu_base * ratio_6x4x / 2); + clock_set(s->cpu_1x, cpu_base * ratio_6x4x); } =20 /** @@ -322,6 +351,10 @@ static void zynq_slcr_propagate_clocks(ZynqSLCRState *= s) { clock_propagate(s->uart0_ref_clk); clock_propagate(s->uart1_ref_clk); + clock_propagate(s->cpu_1x); + clock_propagate(s->cpu_2x); + clock_propagate(s->cpu_3x2x); + clock_propagate(s->cpu_6x4x); } =20 static void zynq_slcr_ps_clk_callback(void *opaque, ClockEvent event) @@ -620,6 +653,10 @@ static const ClockPortInitArray zynq_slcr_clocks =3D { QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback, ClockU= pdate), QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), + QDEV_CLOCK_OUT(ZynqSLCRState, cpu_1x), + QDEV_CLOCK_OUT(ZynqSLCRState, cpu_2x), + QDEV_CLOCK_OUT(ZynqSLCRState, cpu_3x2x), + QDEV_CLOCK_OUT(ZynqSLCRState, cpu_6x4x), QDEV_CLOCK_END }; =20 @@ -630,6 +667,9 @@ static void zynq_slcr_realize(DeviceState *dev, Error *= *errp) if (s->boot_mode > 0xF) { error_setg(errp, "Invalid boot mode %d specified", s->boot_mode); } + + zynq_slcr_reset_init(OBJECT(s), 0); + zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk)); } =20 static void zynq_slcr_init(Object *obj) --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1779089946819195.03607882957976; Mon, 18 May 2026 00:39:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wOsV8-000117-T8; Mon, 18 May 2026 03:34:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wOsUZ-0000hS-P7 for qemu-devel@nongnu.org; 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Mon, 18 May 2026 00:34:16 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org Subject: [PATCH v7 13/16] hw/timer, cpu: Add Clock API support to A9MPCore timers Date: Mon, 18 May 2026 09:33:58 +0200 Message-ID: <20260518073401.11279-14-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=corvin.koehne@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1779089950102154100 Content-Type: text/plain; charset="utf-8" From: YannickV Add a clock input to a9gtimer, arm_mptimer and a9mpcore. a9mpcore distributes the clock to the other timers. If no clock is connected, falls back to 100 MHz for backward compatibility with existing machine types. Frequency calculation now uses the input clock and prescaler values according to ARM Cortex-A9 MPCore Technical Reference Manual. More information about the A9MPCore timers can be found here: https://developer.arm.com/documentation/ddi0407/c/timers-and-watchdog-regis= ters?lang=3Den Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 1 + hw/cpu/a9mpcore.c | 12 ++++++++++++ hw/timer/a9gtimer.c | 18 +++++++++++++++--- hw/timer/arm_mptimer.c | 20 +++++++++++++++----- include/hw/cpu/a9mpcore.h | 1 + include/hw/timer/a9gtimer.h | 1 + include/hw/timer/arm_mptimer.h | 2 ++ 7 files changed, 47 insertions(+), 8 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 52c9e41a76..5aac215c27 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -271,6 +271,7 @@ static void zynq_init(MachineState *machine) dev =3D qdev_new(TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL); + qdev_connect_clock_in(dev, "clk", qdev_get_clock_out(slcr, "cpu_3x2x")= ); busdev =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 2127f95578..5ffdc9277b 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -14,6 +14,8 @@ #include "hw/cpu/a9mpcore.h" #include "hw/core/irq.h" #include "hw/core/qdev-properties.h" +#include "hw/core/qdev-clock.h" +#include "hw/core/clock.h" #include "hw/core/cpu.h" #include "target/arm/cpu-qom.h" =20 @@ -42,6 +44,13 @@ static void a9mp_priv_initfn(Object *obj) object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); =20 object_initialize_child(obj, "wdt", &s->wdt, TYPE_ARM_MPTIMER); + + /* + * Register a clock input. If no clock is connected the + * frequency falls back to 100 MHz for backward compatibility. + */ + s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", NULL, NULL, 0); + clock_set_ns(s->clk, 10); } =20 static void a9mp_priv_realize(DeviceState *dev, Error **errp) @@ -103,6 +112,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error *= *errp) =20 gtimerdev =3D DEVICE(&s->gtimer); qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); + qdev_connect_clock_in(gtimerdev, "clk", s->clk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gtimer), errp)) { return; } @@ -110,6 +120,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error *= *errp) =20 mptimerdev =3D DEVICE(&s->mptimer); qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); + qdev_connect_clock_in(mptimerdev, "clk", s->clk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->mptimer), errp)) { return; } @@ -117,6 +128,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error *= *errp) =20 wdtdev =3D DEVICE(&s->wdt); qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); + qdev_connect_clock_in(wdtdev, "clk", s->clk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt), errp)) { return; } diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index 3a086915c8..c9ffb4e2c1 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -24,6 +24,9 @@ #include "hw/core/hw-error.h" #include "hw/core/irq.h" #include "hw/core/qdev-properties.h" +#include "hw/core/qdev-properties-system.h" +#include "hw/core/qdev-clock.h" +#include "hw/core/clock.h" #include "hw/timer/a9gtimer.h" #include "migration/vmstate.h" #include "qapi/error.h" @@ -63,9 +66,10 @@ static inline int a9_gtimer_get_current_cpu(A9GTimerStat= e *s) static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s) { uint64_t prescale =3D extract32(s->control, R_CONTROL_PRESCALER_SHIFT, - R_CONTROL_PRESCALER_LEN); - - return (prescale + 1) * 10; + R_CONTROL_PRESCALER_LEN) + 1; + uint64_t clk_hz =3D clock_get_hz(s->clk); + assert(clk_hz !=3D 0); + return muldiv64(prescale, NANOSECONDS_PER_SECOND, clk_hz); } =20 static A9GTimerUpdate a9_gtimer_get_update(A9GTimerState *s) @@ -295,6 +299,13 @@ static void a9_gtimer_reset(DeviceState *dev) a9_gtimer_update(s, false); } =20 +static void a9_gtimer_init(Object *obj) +{ + A9GTimerState *s =3D A9_GTIMER(obj); + + s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", NULL, NULL, 0); +} + static void a9_gtimer_realize(DeviceState *dev, Error **errp) { A9GTimerState *s =3D A9_GTIMER(dev); @@ -391,6 +402,7 @@ static const TypeInfo a9_gtimer_info =3D { .name =3D TYPE_A9_GTIMER, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(A9GTimerState), + .instance_init =3D a9_gtimer_init, .class_init =3D a9_gtimer_class_init, }; =20 diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 88158144b2..eb40241ef6 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -24,9 +24,13 @@ #include "hw/core/irq.h" #include "hw/core/ptimer.h" #include "hw/core/qdev-properties.h" +#include "hw/core/qdev-properties-system.h" +#include "hw/core/qdev-clock.h" +#include "hw/core/clock.h" #include "hw/timer/arm_mptimer.h" #include "migration/vmstate.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qemu/module.h" #include "hw/core/cpu.h" =20 @@ -58,10 +62,12 @@ static inline void timerblock_update_irq(TimerBlock *tb) qemu_set_irq(tb->irq, tb->status && (tb->control & 4)); } =20 -/* Return conversion factor from mpcore timer ticks to qemu timer ticks. = */ -static inline uint32_t timerblock_scale(uint32_t control) +static inline uint32_t timerblock_scale(TimerBlock *tb, uint32_t control) { - return (((control >> 8) & 0xff) + 1) * 10; + uint64_t prescale =3D (((control >> 8) & 0xff) + 1); + uint64_t clk_hz =3D clock_get_hz(tb->clk); + assert(clk_hz !=3D 0); + return muldiv64(prescale, NANOSECONDS_PER_SECOND, clk_hz); } =20 /* Must be called within a ptimer transaction block */ @@ -155,7 +161,7 @@ static void timerblock_write(void *opaque, hwaddr addr, ptimer_stop(tb->timer); } if ((control & 0xff00) !=3D (value & 0xff00)) { - ptimer_set_period(tb->timer, timerblock_scale(value)); + ptimer_set_period(tb->timer, timerblock_scale(tb, value)); } if (value & 1) { uint64_t count =3D ptimer_get_count(tb->timer); @@ -222,7 +228,8 @@ static void timerblock_reset(TimerBlock *tb) ptimer_transaction_begin(tb->timer); ptimer_stop(tb->timer); ptimer_set_limit(tb->timer, 0, 1); - ptimer_set_period(tb->timer, timerblock_scale(0)); + ptimer_set_period(tb->timer, + timerblock_scale(tb, 0)); ptimer_transaction_commit(tb->timer); } } @@ -244,6 +251,8 @@ static void arm_mptimer_init(Object *obj) memory_region_init_io(&s->iomem, obj, &arm_thistimer_ops, s, "arm_mptimer_timer", 0x20); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", NULL, NULL, 0); } =20 static void arm_mptimer_realize(DeviceState *dev, Error **errp) @@ -269,6 +278,7 @@ static void arm_mptimer_realize(DeviceState *dev, Error= **errp) */ for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; + tb->clk =3D s->clk; tb->timer =3D ptimer_init(timerblock_tick, tb, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h index 6076599024..11b4b7cfe9 100644 --- a/include/hw/cpu/a9mpcore.h +++ b/include/hw/cpu/a9mpcore.h @@ -34,6 +34,7 @@ struct A9MPPrivState { A9GTimerState gtimer; ARMMPTimerState mptimer; ARMMPTimerState wdt; + Clock *clk; }; =20 #endif diff --git a/include/hw/timer/a9gtimer.h b/include/hw/timer/a9gtimer.h index 5c9b048b95..ef198a969e 100644 --- a/include/hw/timer/a9gtimer.h +++ b/include/hw/timer/a9gtimer.h @@ -87,6 +87,7 @@ struct A9GTimerState { uint32_t control; /* only non per cpu banked bits valid */ =20 A9GTimerPerCPU per_cpu[A9_GTIMER_MAX_CPUS]; + Clock *clk; }; =20 typedef struct A9GTimerUpdate { diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h index 4c6f569631..723f9b9319 100644 --- a/include/hw/timer/arm_mptimer.h +++ b/include/hw/timer/arm_mptimer.h @@ -33,6 +33,7 @@ typedef struct { struct ptimer_state *timer; qemu_irq irq; MemoryRegion iomem; + Clock *clk; } TimerBlock; =20 #define TYPE_ARM_MPTIMER "arm_mptimer" @@ -44,6 +45,7 @@ struct ARMMPTimerState { /*< public >*/ =20 uint32_t num_cpu; + Clock *clk; TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS]; MemoryRegion iomem; }; --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 18 May 2026 00:34:17 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org Subject: [PATCH v7 14/16] hw/arm/xilinx_zynq: Make PS frequency configurable Date: Mon, 18 May 2026 09:33:59 +0200 Message-ID: <20260518073401.11279-15-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=corvin.koehne@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089939701154100 Content-Type: text/plain; charset="utf-8" From: YannickV Add ps_clk_freq to ZynqMachineClass so derived machine types can set their own PS clock frequency instead of using the hardcoded default. Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 3 ++- include/hw/arm/xilinx_zynq.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 5aac215c27..a464189542 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -259,7 +259,7 @@ static void zynq_init(MachineState *machine) object_property_add_child(OBJECT(zynq_machine), "ps_clk", OBJECT(zynq_machine->ps_clk)); object_unref(OBJECT(zynq_machine->ps_clk)); - clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); + clock_set_hz(zynq_machine->ps_clk, zmc->ps_clk_freq); =20 /* Create slcr, keep a pointer to connect clocks */ slcr =3D qdev_new("xilinx-zynq_slcr"); @@ -485,6 +485,7 @@ static void zynq_machine_class_init(ObjectClass *oc, co= nst void *data) " jtag qspi sd nor"); object_property_set_default_str(prop, "qspi"); zmc->qspi_flash_type =3D "n25q128"; + zmc->ps_clk_freq =3D PS_CLK_FREQUENCY; } =20 static const TypeInfo zynq_machine_type =3D { diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h index 662b390431..bf411f1cc2 100644 --- a/include/hw/arm/xilinx_zynq.h +++ b/include/hw/arm/xilinx_zynq.h @@ -24,6 +24,7 @@ OBJECT_DECLARE_TYPE(ZynqMachineState, ZynqMachineClass, Z= YNQ_MACHINE) struct ZynqMachineState { MachineState parent; Clock *ps_clk; + Clock *mpcore_clk; ARMCPU *cpu[ZYNQ_MAX_CPUS]; uint8_t boot_mode; }; @@ -31,6 +32,7 @@ struct ZynqMachineState { struct ZynqMachineClass { MachineClass parent_class; const char *qspi_flash_type; + uint64_t ps_clk_freq; }; =20 #endif /* QEMU_ARM_ZYNQ_H */ --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1779089950; cv=none; d=zohomail.com; s=zohoarc; b=R511K8HlOhK5OIQfxFnE4eQWHVuL/SsOak6IBmsJObaitHCmOIi4qMX61P1heIVRSbJNJd0c2hHHKQ+P90S4QHHfHqIRhOpsSd4gHogJxcc1lCz/tfJ+MI3O3Q64qN46vjYyFJ79dB2vz58YCWnjZbtNKdBLWayDtyQTshjzXVs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1779089950; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Mon, 18 May 2026 00:34:18 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org Subject: [PATCH v7 15/16] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Date: Mon, 18 May 2026 09:34:00 +0200 Message-ID: <20260518073401.11279-16-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=corvin.koehne@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089951981154100 Content-Type: text/plain; charset="utf-8" From: YannickV Introduce a new machine type 'beckhoff-cx7200' that inherits from the xilinx-zynq-a9 machine. The CX7200 is an industrial PC based on the Xilinx Zynq-7000 SoC. The machine preserves all standard Zynq features (boot-mode selection, SPI, UART, Ethernet, etc.) while adding CX7200-specific hardware components. Signed-off-by: YannickV Reviewed-by: Peter Maydell --- MAINTAINERS | 9 +++++ hw/arm/Kconfig | 7 ++++ hw/arm/beckhoff_CX7200.c | 80 ++++++++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 4 files changed, 97 insertions(+) create mode 100644 hw/arm/beckhoff_CX7200.c diff --git a/MAINTAINERS b/MAINTAINERS index 788b815501..c0a9531bf1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1159,6 +1159,15 @@ F: include/hw/adc/zynq-xadc.h X: hw/ssi/xilinx_* F: docs/system/arm/xlnx-zynq.rst =20 +Beckhoff CX7200 +M: Yannick Vossen +M: Corvin Koehne +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/beckhoff_CX7200.c +F: hw/misc/beckhoff_ccat.c +F: include/hw/misc/beckhoff_ccat.h + Xilinx ZynqMP and Versal M: Alistair Francis M: Edgar E. Iglesias diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index fb798ccbee..be500186ca 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -292,6 +292,13 @@ config ZYNQ select XLNX_ZYNQ_DDRC select ZYNQ_DEVCFG =20 +config BECKHOFF_CX7200 + bool + default y + depends on TCG && ARM + select ZYNQ + select BECKHOFF_CCAT + config ARM_V7M bool # currently v7M must be included in a TCG build due to translate.c diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c new file mode 100644 index 0000000000..6e27515886 --- /dev/null +++ b/hw/arm/beckhoff_CX7200.c @@ -0,0 +1,80 @@ + +/* + * Modified Xilinx Zynq Baseboard System emulation for Beckhoff CX7200. + * + * Copyright (c) 2026 Beckhoff Automation GmbH & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/core/boards.h" +#include "hw/block/block.h" +#include "hw/core/loader.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/clock.h" +#include "qemu/error-report.h" +#include "hw/arm/xilinx_zynq.h" /* For ZynqMachineState */ +#include "hw/cpu/a9mpcore.h" +#include "hw/timer/a9gtimer.h" +#include "qom/object.h" + +#define TYPE_CX7200_MACHINE MACHINE_TYPE_NAME("beckhoff-cx7200") + +#define CX7200_PS_CLK_FREQUENCY (40 * 1000 * 1000) + +static void ccat_init(uint32_t base, BlockBackend *eeprom_blk) +{ + DeviceState *dev; + SysBusDevice *busdev; + + dev =3D qdev_new("beckhoff-ccat"); + if (eeprom_blk) { + qdev_prop_set_drive_err(dev, "eeprom", eeprom_blk, &error_fatal); + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); +} + +static void beckhoff_cx7200_init(MachineState *machine) +{ + DriveInfo *di; + BlockBackend *blk; + MachineClass *parent_mc; + + parent_mc =3D MACHINE_CLASS(object_class_get_parent( + object_get_class(OBJECT(machine)))); + parent_mc->init(machine); + + di =3D drive_get(IF_NONE, 0, 0); + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; + ccat_init(0x40000000, blk); +} + +static void beckhoff_cx7200_machine_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + ZynqMachineClass *zmc =3D ZYNQ_MACHINE_CLASS(oc); + + mc->desc =3D "Beckhoff CX7200 Industrial PC (Zynq-based)"; + mc->init =3D beckhoff_cx7200_init; + zmc->qspi_flash_type =3D "is25lp016d"; + zmc->ps_clk_freq =3D CX7200_PS_CLK_FREQUENCY; +} + +static const TypeInfo beckhoff_cx7200_machine_type =3D { + .name =3D TYPE_CX7200_MACHINE, + .parent =3D TYPE_ZYNQ_MACHINE, + .class_init =3D beckhoff_cx7200_machine_class_init, + .instance_size =3D sizeof(ZynqMachineState), +}; + +static void beckhoff_cx7200_machine_register_types(void) +{ + type_register_static(&beckhoff_cx7200_machine_type); +} + +type_init(beckhoff_cx7200_machine_register_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 80068f70bb..46e77cb49b 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -2,6 +2,7 @@ arm_ss =3D ss.source_set() arm_common_ss =3D ss.source_set() arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) +arm_common_ss.add(when: 'CONFIG_BECKHOFF_CX7200', if_true: files('beckhoff= _CX7200.c')) arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) arm_common_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.= c')) --=20 2.47.3 From nobody Sat May 30 18:34:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 18 May 2026 00:34:19 -0700 (PDT) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , Hanna Reitz , =?UTF-8?q?Corvin=20K=C3=B6hne?= , Paolo Bonzini , "Edgar E. Iglesias" , Pierrick Bouvier , Yannick Vossen , qemu-arm@nongnu.org, Kevin Wolf , Alistair Francis , Corvin Koehne , qemu-block@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v7 16/16] docs/system/arm: Add support for Beckhoff CX7200 Date: Mon, 18 May 2026 09:34:01 +0200 Message-ID: <20260518073401.11279-17-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260518073401.11279-1-corvin.koehne@gmail.com> References: <20260518073401.11279-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=corvin.koehne@gmail.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779089742734158501 From: YannickV This commit offers some documentation on the Beckhoff CX7200 qemu emulation. Signed-off-by: YannickV Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- docs/system/arm/beckhoff-cx7200.rst | 62 +++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 2 files changed, 63 insertions(+) create mode 100644 docs/system/arm/beckhoff-cx7200.rst diff --git a/docs/system/arm/beckhoff-cx7200.rst b/docs/system/arm/beckhoff= -cx7200.rst new file mode 100644 index 0000000000..6163a0cfa5 --- /dev/null +++ b/docs/system/arm/beckhoff-cx7200.rst @@ -0,0 +1,62 @@ +Beckhoff CX7200 (``beckhoff-cx7200``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The Beckhoff CX7200 is based on the same architecture as the Xilinx Zynq A= 9. +The Zynq 7000 family is based on the AMD SoC architecture. These products +integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based +processing system (PS) and AMD programmable logic (PL) in a single device. +The Beckhoff Communication Controller (CCAT) can be found in the PL of Zyn= q. + +You can find more detail about this board on +`the manufacturer's product page `__. +The SoC is documented in the +`Zynq 7000 Technical Reference manual `__. + +The CX7200 supports the following: + +- Arm Cortex-A9 MPCore CPU + + - Cortex-A9 CPUs + - GIC v1 interrupt controller + - Generic timer + - Watchdog timer + +- OCM 256KB +- SMC SRAM 64MB +- Zynq SLCR +- SPI x2 +- QSPI +- UART +- TTC x2 +- Gigabit Ethernet Controller x2 +- SD Controller x2 +- XADC +- Arm PrimeCell DMA Controller +- DDR Memory +- USB 2.0 x2 +- DDR Controller +- Beckhoff Communication Controller (CCAT) + + - EEPROM Interface + - DMA Controller + +The following is not supported: + - I2C + +Running +""""""" +Directly loading an ELF file to the CPU of the CX7200 to run f.e. TC/RTOS = (based on FreeRTOS): + +.. code-block:: bash + + $ qemu-system-arm -M beckhoff-cx7200 \ + -device loader,file=3DCX7200_Zynq_Fsbl.elf \ + -display none + + +For setting the EEPROM content of the CCAT provide the following on the co= mmand line: + +.. code-block:: bash + + -drive file=3Deeprom.bin,format=3Draw,id=3Dccat-eeprom + +The size of eeprom.bin must be aligned to a power of 2 and bigger than 256= bytes. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index e34492402f..e6fbdb663c 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -82,6 +82,7 @@ Board-specific documentation arm/aspeed arm/bananapi_m2u.rst arm/b-l475e-iot01a.rst + arm/beckhoff-cx7200 arm/sabrelite arm/digic arm/cubieboard --=20 2.47.3