[v5] hw/riscv: Server Platform Reference Board

[PATCH v5 0/4] hw/riscv: Server Platform Reference Board

Daniel Henrique Barboza posted 4 patches 1 month ago

Diff against v6
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260424191129.1494381-1-daniel.barboza@oss.qualcomm.com

Maintainers: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>, Paolo Bonzini <pbonzini@redhat.com>

There is a newer version of this series

configs/devices/riscv64-softmmu/default.mak |    1 +
docs/system/riscv/riscv-server-ref.rst      |   31 +
docs/system/target-riscv.rst                |    1 +
hw/riscv/Kconfig                            |   15 +
hw/riscv/meson.build                        |    1 +
hw/riscv/server_platform_ref.c              | 1371 +++++++++++++++++++
target/riscv/cpu-qom.h                      |    1 +
target/riscv/cpu.c                          |   12 +-
8 files changed, 1432 insertions(+), 1 deletion(-)
create mode 100644 docs/system/riscv/riscv-server-ref.rst
create mode 100644 hw/riscv/server_platform_ref.c

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[PATCH v5 0/4] hw/riscv: Server Platform Reference Board

Posted by Daniel Henrique Barboza 1 month ago

Greetings,

In this new version the main change is that now we're no longer claiming
an 'experimental' support, like we did in v4, because at this moment
(well, when sdext [1] is upstreamed) we have all extensions required to
support this reference board.

Another major change is the rename of the CPU and the board: we're
naming both 'riscv-server-ref' instead of 'rvsp-ref'.  We're keeping the
"-ref" suffix to match what ARM does with its reference board
(sbsa-ref), but adding a longer name to be clearer about what the board
is.

Patches patches are based on alistair/riscv-to-apply.next @56bbd4f25c,
plus Chao Liu's series "[PATCH v6 0/7] riscv: add initial sdext support"
[1].  For convenience this series is available at this branch:

https://gitlab.com/danielhb/qemu/-/tree/riscv-server-ref_v5


Changes from v4:
- removed 'experimental' qualifier from the board description;
- changed CPU name from "rvsp-ref" to "riscv-server-ref"
- changed board name from "rvsp-ref" to "riscv-server-ref"
- former patch 4 ("hw/riscv/server_platform_ref.c: add riscv-iommu-sys"):
  - squashed into patch 3
- v4 link: https://lore.kernel.org/qemu-devel/20251111182944.2895892-1-dbarboza@ventanamicro.com/

[1] https://lore.kernel.org/qemu-devel/cover.1775959096.git.chao.liu.zevorn@gmail.com/


Daniel Henrique Barboza (2):
  target/riscv/cpu.c: remove 'bare' condition for .profile
  docs: add riscv-server-ref.rst

Fei Wu (2):
  target/riscv: Add server platform reference cpu
  hw/riscv: server platform reference machine

 configs/devices/riscv64-softmmu/default.mak |    1 +
 docs/system/riscv/riscv-server-ref.rst      |   31 +
 docs/system/target-riscv.rst                |    1 +
 hw/riscv/Kconfig                            |   15 +
 hw/riscv/meson.build                        |    1 +
 hw/riscv/server_platform_ref.c              | 1371 +++++++++++++++++++
 target/riscv/cpu-qom.h                      |    1 +
 target/riscv/cpu.c                          |   12 +-
 8 files changed, 1432 insertions(+), 1 deletion(-)
 create mode 100644 docs/system/riscv/riscv-server-ref.rst
 create mode 100644 hw/riscv/server_platform_ref.c

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2.43.0