This series adds support for the RISC-V Packed SIMD (P) extension.

The P extension defines packed-SIMD fixed-point operations intended
for DSP-style workloads such as multimedia and signal processing.
These instructions operate on packed subword elements within
general-purpose registers (GPRs).

The implementation follows the current development draft of the
specification (v0.20):

  https://www.jhauser.us/RISCV/ext-P/

All instructions defined prior to the v0.20 update were verified
using a simple instruction coverage test suite:

  https://github.com/mollybuild/qemu-riscv-test-uart

Instructions newly introduced in v0.20 were not tested yet because
toolchain support for generating them is still under development.

The implementation focuses on functional correctness and ISA coverage.
Performance optimizations were not considered at this stage.

Feedback on implementation details would be highly appreciated.

Co-Authored by: Yin Zhang <zhangyin2018@iscas.ac.cn>
Co-Authored by: Dajun Huang <djhuang_1@std.uestc.edu.cn>
Co-Authored by: Zhiyuan Yang <zhiyuan.plct@isrc.iscas.ac.cn> 

Molly Chen (14):
  target/riscv: rvp: Add option defines and dependency check for packed
    simd extension
  target/riscv: rvp: add arithmetic instructions,including saturating
    and non-saturating operations
  target/riscv: rvp: add averaging operations
  target/riscv: rvp: add absolute value and difference,comparison and
    mask generation operations
  target/riscv: rvp: add shift operations
  target/riscv: rvp: add exchange operations
  target/riscv: rvp: add horizontal reduction, pack, merge and cout
    leading operations
  target/riscv: rvp: add pure multiplication operations
  target/riscv: rvp: add multiply-accumulate operations
  target/riscv: rvp: add Q-format multiplication operations
  target/riscv: rvp: add two-way and four-way multiply and accumulate
    operations
  target/riscv: rvp: add load and replicate instructions.
  target/riscv: rvp: add rv32-only register-pair instructions
  target/riscv: rvp: update to v020, add SHL and PNCLIP[U]P.*
    instructions

 target/riscv/cpu.c                      |    5 +-
 target/riscv/cpu.h                      |    1 +
 target/riscv/helper.h                   |  531 ++
 target/riscv/insn32.decode              |  829 ++
 target/riscv/insn_trans/trans_rvp.c.inc | 1691 ++++
 target/riscv/meson.build                |    3 +-
 target/riscv/psimd_helper.c             | 9452 +++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c              |   16 +
 target/riscv/translate.c                |    3 +
 9 files changed, 12528 insertions(+), 3 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc
 create mode 100644 target/riscv/psimd_helper.c

-- 
2.34.1