Thank you for your very specific feedback. I fully understand your point
about eliminating code repetition — not only to reduce lines of code,
but also to have fewer points of logic to take care of. I will review
and revise the code according to your suggestions, reusing code where
possible to minimize redundancy. These changes will be reflected in v2.
Thanks again!
Best regards,
Molly
在 2026/4/22 20:44, Daniel Henrique Barboza 写道:
> Hi,
>
> On 4/17/2026 7:46 AM, Molly Chen wrote:
>> This series adds support for the RISC-V Packed SIMD (P) extension.
>>
>> The P extension defines packed-SIMD fixed-point operations intended
>> for DSP-style workloads such as multimedia and signal processing.
>> These instructions operate on packed subword elements within
>> general-purpose registers (GPRs).
>
> Thanks for the work in putting all this together.
>
> I did a review in patch 2 that I believe applies to all other patches:
> we should strive to code re-use and avoid any code duplication as we can.
> This would be a good goal for a version 2.
>
>>
>> The implementation follows the current development draft of the
>> specification (v0.20):
>>
>> https://www.jhauser.us/RISCV/ext-P/
>>
>> All instructions defined prior to the v0.20 update were verified
>> using a simple instruction coverage test suite:
>>
>> https://github.com/mollybuild/qemu-riscv-test-uart
>
> A testsuite is greatly appreciated, in particular due to the amount of
> code included in this work.
>
>>
>> Instructions newly introduced in v0.20 were not tested yet because
>> toolchain support for generating them is still under development.
>
> This is fine. You're adding experimental support so it's ok if it's not
> fully tested/completed, as long as we take care to document the
> limitations
> and caveats of the existing emulation.
>
>
> Also, I talked with RVI. I got told that this spec can move from 'draft'
> to 'frozen' later this year (Q3, maybe Q4). Depending on the
> time-frame of
> the spec status change, and the amount of progress we can make in the
> review
> process, the spec might move to 'frozen' and we can drop the experimental
> tag and upstream it as a regular extension. Let's see how we do.
>
>
> Thanks,
> Daniel
>
>>
>> The implementation focuses on functional correctness and ISA coverage.
>> Performance optimizations were not considered at this stage.
>>
>> Feedback on implementation details would be highly appreciated.
>>
>> Co-Authored by: Yin Zhang <zhangyin2018@iscas.ac.cn>
>> Co-Authored by: Dajun Huang <djhuang_1@std.uestc.edu.cn>
>> Co-Authored by: Zhiyuan Yang <zhiyuan.plct@isrc.iscas.ac.cn>
>>
>> Molly Chen (14):
>> target/riscv: rvp: Add option defines and dependency check for packed
>> simd extension
>> target/riscv: rvp: add arithmetic instructions,including saturating
>> and non-saturating operations
>> target/riscv: rvp: add averaging operations
>> target/riscv: rvp: add absolute value and difference,comparison and
>> mask generation operations
>> target/riscv: rvp: add shift operations
>> target/riscv: rvp: add exchange operations
>> target/riscv: rvp: add horizontal reduction, pack, merge and cout
>> leading operations
>> target/riscv: rvp: add pure multiplication operations
>> target/riscv: rvp: add multiply-accumulate operations
>> target/riscv: rvp: add Q-format multiplication operations
>> target/riscv: rvp: add two-way and four-way multiply and accumulate
>> operations
>> target/riscv: rvp: add load and replicate instructions.
>> target/riscv: rvp: add rv32-only register-pair instructions
>> target/riscv: rvp: update to v020, add SHL and PNCLIP[U]P.*
>> instructions
>>
>> target/riscv/cpu.c | 5 +-
>> target/riscv/cpu.h | 1 +
>> target/riscv/helper.h | 531 ++
>> target/riscv/insn32.decode | 829 ++
>> target/riscv/insn_trans/trans_rvp.c.inc | 1691 ++++
>> target/riscv/meson.build | 3 +-
>> target/riscv/psimd_helper.c | 9452 +++++++++++++++++++++++
>> target/riscv/tcg/tcg-cpu.c | 16 +
>> target/riscv/translate.c | 3 +
>> 9 files changed, 12528 insertions(+), 3 deletions(-)
>> create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc
>> create mode 100644 target/riscv/psimd_helper.c
>>