From: Yodel Eldar <yodel.eldar@yodel.dev>

Currently, a read of the Typhoon Cchip's MISC register
dereferences current_cpu for the CPU index. To decouple
Typhoon from the CPU, let's instead pass the CPU index
through the requester_id attribute of the memory transaction.

Signed-off-by: Yodel Eldar <yodel.eldar@yodel.dev>
---
 hw/alpha/typhoon.c    |  7 ++++---
 target/alpha/helper.c | 15 ++++++++++++---
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index 26580664d8..5dadfa7691 100644
--- a/hw/alpha/typhoon.c
+++ b/hw/alpha/typhoon.c
@@ -74,7 +74,6 @@ static MemTxResult cchip_read(void *opaque, hwaddr addr,
                               uint64_t *data, unsigned size,
                               MemTxAttrs attrs)
 {
-    CPUState *cpu = current_cpu;
     TyphoonState *s = opaque;
     uint64_t ret = 0;
 
@@ -90,10 +89,12 @@ static MemTxResult cchip_read(void *opaque, hwaddr addr,
         /* All sorts of stuff related to real DRAM.  */
         break;
 
-    case 0x0080:
+    case 0x0080: {
         /* MISC: Miscellaneous Register.  */
-        ret = s->cchip.misc | (cpu->cpu_index & 3);
+        uint64_t cpu_index = attrs.requester_id & 3;
+        ret = s->cchip.misc | cpu_index;
         break;
+    }
 
     case 0x00c0:
         /* MPD: Memory Presence Detect Register.  */
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 179dc2dc7a..bebb0e4804 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -164,13 +164,19 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
     env->trap_arg2 = cause;
 }
 #else
+static inline QEMU_ALWAYS_INLINE
+MemTxAttrs alpha_cpu_get_mem_attrs(const CPUState *cs)
+{
+    return (MemTxAttrs){ .requester_id = cs->cpu_index };
+}
+
 /* Returns the OSF/1 entMM failure indication, or -1 on success.  */
 static int get_physical_address(CPUAlphaState *env, vaddr addr,
                                 int prot_need, int mmu_idx,
                                 hwaddr *pphys, int *pprot)
 {
-    const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
     CPUState *cs = env_cpu(env);
+    const MemTxAttrs attrs = alpha_cpu_get_mem_attrs(cs);
     target_long saddr = addr;
     hwaddr phys = 0;
     uint64_t L1pte, L2pte, L3pte;
@@ -327,8 +333,11 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
         cpu_loop_exit_restore(cs, retaddr);
     }
 
-    tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
-                 prot, mmu_idx, TARGET_PAGE_SIZE);
+    tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK,
+                            phys & TARGET_PAGE_MASK,
+                            alpha_cpu_get_mem_attrs(cs),
+                            prot, mmu_idx, TARGET_PAGE_SIZE);
+
     return true;
 }
 
-- 
2.53.0