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[PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API

Philippe Mathieu-Daudé posted 16 patches 2 weeks, 5 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260318103122.97244-1-philmd@linaro.org
Maintainers: Laurent Vivier <laurent@vivier.eu>, Pierrick Bouvier <pierrick.bouvier@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu.zevorn@gmail.com>, Warner Losh <imp@bsdimp.com>, Kyle Evans <kevans@freebsd.org>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Vijai Kumar K <vijai@behindbytes.com>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Peter Maydell <peter.maydell@linaro.org>
configs/targets/riscv32-linux-user.mak       |  1 +
configs/targets/riscv32-softmmu.mak          |  1 +
configs/targets/riscv64-bsd-user.mak         |  1 +
configs/targets/riscv64-linux-user.mak       |  1 +
configs/targets/riscv64-softmmu.mak          |  1 +
target/riscv/internals.h                     | 12 ++++++
hw/char/ibex_uart.c                          |  2 +-
hw/char/shakti_uart.c                        |  2 +-
hw/char/sifive_uart.c                        |  2 +-
hw/misc/sifive_e_aon.c                       |  2 +-
hw/misc/sifive_e_prci.c                      |  2 +-
hw/misc/sifive_u_otp.c                       |  2 +-
hw/misc/sifive_u_prci.c                      |  2 +-
hw/riscv/riscv-iommu.c                       |  2 +-
hw/sd/cadence_sdhci.c                        |  2 +-
hw/timer/ibex_timer.c                        |  2 +-
hw/timer/sifive_pwm.c                        |  2 +-
target/riscv/cpu_helper.c                    |  4 +-
target/riscv/gdbstub.c                       | 42 ++++++++------------
target/riscv/op_helper.c                     | 14 -------
target/riscv/tcg/tcg-cpu.c                   | 10 -----
target/riscv/translate.c                     | 10 ++---
target/riscv/insn_trans/trans_rvi.c.inc      | 32 +++++++++++----
target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 +++++----
target/riscv/insn_trans/trans_xmips.c.inc    | 24 +++++++----
target/riscv/insn_trans/trans_zilsd.c.inc    |  4 +-
26 files changed, 104 insertions(+), 93 deletions(-)
[PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API
Posted by Philippe Mathieu-Daudé 2 weeks, 5 days ago 
Thanks to Frédéric patch on 128-bit registers, we can now
remove all legacy native endianness API uses of RISC-V.

Djordje: You should (re)base your "Add RISC-V big-endian
target support" [*] series on this (after addressing the
review comments) before posting your v4.

[*] https://lore.kernel.org/qemu-devel/20260311115910.564481-1-djordje.todorovic@htecgroup.com/

Djordje Todorovic (1):
  target/riscv: Use MO_LE for instruction fetch

Frédéric Pétrot (2):
  target/riscv: Make LQ and SQ use 128-bit ld/st
  target/riscv: Remove MTTCG check for x-rv128 CPU model

Philippe Mathieu-Daudé (13):
  hw/riscv: Mark RISC-V specific peripherals as little-endian
  target/riscv: Use explicit little-endian LD/ST API
  target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)
  target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire /
    store_release
  target/riscv: Factor tiny ldn() helper in gdbstub
  target/riscv: Simplify riscv_cpu_gdb_write_register()
  target/riscv: Expose mo_endian_env()
  target/riscv: Have gdbstub consider CPU endianness
  target/riscv: Replace MO_TE by mo_endian (MIPS extension)
  target/riscv: Replace MO_TE by mo_endian (Zilsd extension)
  target/riscv: Replace MO_TE by mo_endian (Zalasr extension)
  target/riscv: Replace MO_TE -> MO_LE
  configs/targets: Forbid RISC-V to use legacy native endianness APIs

 configs/targets/riscv32-linux-user.mak       |  1 +
 configs/targets/riscv32-softmmu.mak          |  1 +
 configs/targets/riscv64-bsd-user.mak         |  1 +
 configs/targets/riscv64-linux-user.mak       |  1 +
 configs/targets/riscv64-softmmu.mak          |  1 +
 target/riscv/internals.h                     | 12 ++++++
 hw/char/ibex_uart.c                          |  2 +-
 hw/char/shakti_uart.c                        |  2 +-
 hw/char/sifive_uart.c                        |  2 +-
 hw/misc/sifive_e_aon.c                       |  2 +-
 hw/misc/sifive_e_prci.c                      |  2 +-
 hw/misc/sifive_u_otp.c                       |  2 +-
 hw/misc/sifive_u_prci.c                      |  2 +-
 hw/riscv/riscv-iommu.c                       |  2 +-
 hw/sd/cadence_sdhci.c                        |  2 +-
 hw/timer/ibex_timer.c                        |  2 +-
 hw/timer/sifive_pwm.c                        |  2 +-
 target/riscv/cpu_helper.c                    |  4 +-
 target/riscv/gdbstub.c                       | 42 ++++++++------------
 target/riscv/op_helper.c                     | 14 -------
 target/riscv/tcg/tcg-cpu.c                   | 10 -----
 target/riscv/translate.c                     | 10 ++---
 target/riscv/insn_trans/trans_rvi.c.inc      | 32 +++++++++++----
 target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 +++++----
 target/riscv/insn_trans/trans_xmips.c.inc    | 24 +++++++----
 target/riscv/insn_trans/trans_zilsd.c.inc    |  4 +-
 26 files changed, 104 insertions(+), 93 deletions(-)

-- 
2.53.0
Re: [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API
Posted by Alistair Francis 1 week, 4 days ago 
On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Thanks to Frédéric patch on 128-bit registers, we can now
> remove all legacy native endianness API uses of RISC-V.
>
> Djordje: You should (re)base your "Add RISC-V big-endian
> target support" [*] series on this (after addressing the
> review comments) before posting your v4.
>
> [*] https://lore.kernel.org/qemu-devel/20260311115910.564481-1-djordje.todorovic@htecgroup.com/
>
> Djordje Todorovic (1):
>   target/riscv: Use MO_LE for instruction fetch
>
> Frédéric Pétrot (2):
>   target/riscv: Make LQ and SQ use 128-bit ld/st
>   target/riscv: Remove MTTCG check for x-rv128 CPU model
>
> Philippe Mathieu-Daudé (13):
>   hw/riscv: Mark RISC-V specific peripherals as little-endian
>   target/riscv: Use explicit little-endian LD/ST API
>   target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)
>   target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire /
>     store_release
>   target/riscv: Factor tiny ldn() helper in gdbstub
>   target/riscv: Simplify riscv_cpu_gdb_write_register()
>   target/riscv: Expose mo_endian_env()
>   target/riscv: Have gdbstub consider CPU endianness
>   target/riscv: Replace MO_TE by mo_endian (MIPS extension)
>   target/riscv: Replace MO_TE by mo_endian (Zilsd extension)
>   target/riscv: Replace MO_TE by mo_endian (Zalasr extension)
>   target/riscv: Replace MO_TE -> MO_LE
>   configs/targets: Forbid RISC-V to use legacy native endianness APIs

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  configs/targets/riscv32-linux-user.mak       |  1 +
>  configs/targets/riscv32-softmmu.mak          |  1 +
>  configs/targets/riscv64-bsd-user.mak         |  1 +
>  configs/targets/riscv64-linux-user.mak       |  1 +
>  configs/targets/riscv64-softmmu.mak          |  1 +
>  target/riscv/internals.h                     | 12 ++++++
>  hw/char/ibex_uart.c                          |  2 +-
>  hw/char/shakti_uart.c                        |  2 +-
>  hw/char/sifive_uart.c                        |  2 +-
>  hw/misc/sifive_e_aon.c                       |  2 +-
>  hw/misc/sifive_e_prci.c                      |  2 +-
>  hw/misc/sifive_u_otp.c                       |  2 +-
>  hw/misc/sifive_u_prci.c                      |  2 +-
>  hw/riscv/riscv-iommu.c                       |  2 +-
>  hw/sd/cadence_sdhci.c                        |  2 +-
>  hw/timer/ibex_timer.c                        |  2 +-
>  hw/timer/sifive_pwm.c                        |  2 +-
>  target/riscv/cpu_helper.c                    |  4 +-
>  target/riscv/gdbstub.c                       | 42 ++++++++------------
>  target/riscv/op_helper.c                     | 14 -------
>  target/riscv/tcg/tcg-cpu.c                   | 10 -----
>  target/riscv/translate.c                     | 10 ++---
>  target/riscv/insn_trans/trans_rvi.c.inc      | 32 +++++++++++----
>  target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 +++++----
>  target/riscv/insn_trans/trans_xmips.c.inc    | 24 +++++++----
>  target/riscv/insn_trans/trans_zilsd.c.inc    |  4 +-
>  26 files changed, 104 insertions(+), 93 deletions(-)
>
> --
> 2.53.0
>
>
Re: [PATCH-for-11.1 00/16] target/riscv: Forbid to use legacy native endianness API
Posted by Philippe Mathieu-Daudé 1 week, 4 days ago 
On 26/3/26 03:28, Alistair Francis wrote:
> On Wed, Mar 18, 2026 at 8:33 PM Philippe Mathieu-Daudé
> <philmd@linaro.org> wrote:
>>
>> Thanks to Frédéric patch on 128-bit registers, we can now
>> remove all legacy native endianness API uses of RISC-V.
>>
>> Djordje: You should (re)base your "Add RISC-V big-endian
>> target support" [*] series on this (after addressing the
>> review comments) before posting your v4.
>>
>> [*] https://lore.kernel.org/qemu-devel/20260311115910.564481-1-djordje.todorovic@htecgroup.com/
>>
>> Djordje Todorovic (1):
>>    target/riscv: Use MO_LE for instruction fetch
>>
>> Frédéric Pétrot (2):
>>    target/riscv: Make LQ and SQ use 128-bit ld/st
>>    target/riscv: Remove MTTCG check for x-rv128 CPU model
>>
>> Philippe Mathieu-Daudé (13):
>>    hw/riscv: Mark RISC-V specific peripherals as little-endian

(Note the first single patch is now commit cf430fa1f1b)

>>    target/riscv: Use explicit little-endian LD/ST API
>>    target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)
>>    target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire /
>>      store_release
>>    target/riscv: Factor tiny ldn() helper in gdbstub
>>    target/riscv: Simplify riscv_cpu_gdb_write_register()
>>    target/riscv: Expose mo_endian_env()
>>    target/riscv: Have gdbstub consider CPU endianness
>>    target/riscv: Replace MO_TE by mo_endian (MIPS extension)
>>    target/riscv: Replace MO_TE by mo_endian (Zilsd extension)
>>    target/riscv: Replace MO_TE by mo_endian (Zalasr extension)
>>    target/riscv: Replace MO_TE -> MO_LE
>>    configs/targets: Forbid RISC-V to use legacy native endianness APIs
> 
> Thanks!
> 
> Applied to riscv-to-apply.next

Thank you!

Phil.

Patchew 2.1-devel-ea86937

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