Import gdb-xml/sparc32-{cpu,fpu,cp0}.xml from mainstream binutils,
tag 'binutils-2_46', found in the gdb/features/sparc/folder [*].
Register them by setting the CPUClass::gdb_core_xml_file field and
calling gdb_register_coprocessor() in sparc_cpu_register_gdb_regs().
[*] https://sourceware.org/git/?p=binutils-gdb.git;a=tree;f=gdb/features/sparc;hb=refs/tags/binutils-2_46
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
configs/targets/sparc-linux-user.mak | 1 +
configs/targets/sparc-softmmu.mak | 1 +
target/sparc/cpu.c | 2 +-
target/sparc/gdbstub.c | 13 +++++----
gdb-xml/sparc32-cp0.xml | 18 ++++++++++++
gdb-xml/sparc32-cpu.xml | 42 ++++++++++++++++++++++++++++
gdb-xml/sparc32-fpu.xml | 42 ++++++++++++++++++++++++++++
7 files changed, 113 insertions(+), 6 deletions(-)
create mode 100644 gdb-xml/sparc32-cp0.xml
create mode 100644 gdb-xml/sparc32-cpu.xml
create mode 100644 gdb-xml/sparc32-fpu.xml
diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-linux-user.mak
index d3f0716ca2d..01446e28783 100644
--- a/configs/targets/sparc-linux-user.mak
+++ b/configs/targets/sparc-linux-user.mak
@@ -2,5 +2,6 @@ TARGET_ARCH=sparc
TARGET_SYSTBL_ABI=common,32
TARGET_SYSTBL=syscall.tbl
TARGET_BIG_ENDIAN=y
+TARGET_XML_FILES=gdb-xml/sparc32-cpu.xml gdb-xml/sparc32-fpu.xml gdb-xml/sparc32-cp0.xml
TARGET_LONG_BITS=32
TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak
index c4c38946d54..ed846735f41 100644
--- a/configs/targets/sparc-softmmu.mak
+++ b/configs/targets/sparc-softmmu.mak
@@ -1,5 +1,6 @@
TARGET_ARCH=sparc
TARGET_BIG_ENDIAN=y
+TARGET_XML_FILES=gdb-xml/sparc32-cpu.xml gdb-xml/sparc32-fpu.xml gdb-xml/sparc32-cp0.xml
TARGET_LONG_BITS=32
TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y
TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index d82f858efb1..1493336e7a2 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1095,7 +1095,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data)
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
cc->gdb_core_xml_file = "sparc64-cpu.xml";
#else
- cc->gdb_num_core_regs = 72;
+ cc->gdb_core_xml_file = "sparc32-cpu.xml";
#endif
cc->tcg_ops = &sparc_tcg_ops;
}
diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
index b5b1494950a..ed52e521dcc 100644
--- a/target/sparc/gdbstub.c
+++ b/target/sparc/gdbstub.c
@@ -43,7 +43,6 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-__attribute__((unused))
static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
CPUSPARCState *env = cpu_env(cs);
@@ -79,7 +78,6 @@ static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
-__attribute__((unused))
static int sparc_cp0_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
CPUSPARCState *env = cpu_env(cs);
@@ -154,7 +152,6 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
#endif
}
-__attribute__((unused))
static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
CPUSPARCState *env = cpu_env(cs);
@@ -197,7 +194,6 @@ static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
#endif
}
-__attribute__((unused))
static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
CPUSPARCState *env = cpu_env(cs);
@@ -271,7 +267,14 @@ static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
void sparc_cpu_register_gdb_regs(CPUState *cs)
{
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
- /* Not yet supported */
+ gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register,
+ sparc_fpu_gdb_write_register,
+ gdb_find_static_feature("sparc32-fpu.xml"),
+ 0);
+ gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register,
+ sparc_cp0_gdb_write_register,
+ gdb_find_static_feature("sparc32-cp0.xml"),
+ 0);
#else
gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register,
sparc_fpu_gdb_write_register,
diff --git a/gdb-xml/sparc32-cp0.xml b/gdb-xml/sparc32-cp0.xml
new file mode 100644
index 00000000000..eacd89cf3b5
--- /dev/null
+++ b/gdb-xml/sparc32-cp0.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2026 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.cp0">
+ <reg name="y" bitsize="32" type="uint32" regnum="64"/>
+ <reg name="psr" bitsize="32" type="uint32" regnum="65"/>
+ <reg name="wim" bitsize="32" type="uint32" regnum="66"/>
+ <reg name="tbr" bitsize="32" type="uint32" regnum="67"/>
+ <reg name="pc" bitsize="32" type="code_ptr" regnum="68"/>
+ <reg name="npc" bitsize="32" type="code_ptr" regnum="69"/>
+ <reg name="fsr" bitsize="32" type="uint32" regnum="70"/>
+ <reg name="csr" bitsize="32" type="uint32" regnum="71"/>
+</feature>
diff --git a/gdb-xml/sparc32-cpu.xml b/gdb-xml/sparc32-cpu.xml
new file mode 100644
index 00000000000..242295c886e
--- /dev/null
+++ b/gdb-xml/sparc32-cpu.xml
@@ -0,0 +1,42 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2026 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.cpu">
+ <reg name="g0" bitsize="32" type="uint32" regnum="0"/>
+ <reg name="g1" bitsize="32" type="uint32" regnum="1"/>
+ <reg name="g2" bitsize="32" type="uint32" regnum="2"/>
+ <reg name="g3" bitsize="32" type="uint32" regnum="3"/>
+ <reg name="g4" bitsize="32" type="uint32" regnum="4"/>
+ <reg name="g5" bitsize="32" type="uint32" regnum="5"/>
+ <reg name="g6" bitsize="32" type="uint32" regnum="6"/>
+ <reg name="g7" bitsize="32" type="uint32" regnum="7"/>
+ <reg name="o0" bitsize="32" type="uint32" regnum="8"/>
+ <reg name="o1" bitsize="32" type="uint32" regnum="9"/>
+ <reg name="o2" bitsize="32" type="uint32" regnum="10"/>
+ <reg name="o3" bitsize="32" type="uint32" regnum="11"/>
+ <reg name="o4" bitsize="32" type="uint32" regnum="12"/>
+ <reg name="o5" bitsize="32" type="uint32" regnum="13"/>
+ <reg name="sp" bitsize="32" type="uint32" regnum="14"/>
+ <reg name="o7" bitsize="32" type="uint32" regnum="15"/>
+ <reg name="l0" bitsize="32" type="uint32" regnum="16"/>
+ <reg name="l1" bitsize="32" type="uint32" regnum="17"/>
+ <reg name="l2" bitsize="32" type="uint32" regnum="18"/>
+ <reg name="l3" bitsize="32" type="uint32" regnum="19"/>
+ <reg name="l4" bitsize="32" type="uint32" regnum="20"/>
+ <reg name="l5" bitsize="32" type="uint32" regnum="21"/>
+ <reg name="l6" bitsize="32" type="uint32" regnum="22"/>
+ <reg name="l7" bitsize="32" type="uint32" regnum="23"/>
+ <reg name="i0" bitsize="32" type="uint32" regnum="24"/>
+ <reg name="i1" bitsize="32" type="uint32" regnum="25"/>
+ <reg name="i2" bitsize="32" type="uint32" regnum="26"/>
+ <reg name="i3" bitsize="32" type="uint32" regnum="27"/>
+ <reg name="i4" bitsize="32" type="uint32" regnum="28"/>
+ <reg name="i5" bitsize="32" type="uint32" regnum="29"/>
+ <reg name="fp" bitsize="32" type="uint32" regnum="30"/>
+ <reg name="i7" bitsize="32" type="uint32" regnum="31"/>
+</feature>
diff --git a/gdb-xml/sparc32-fpu.xml b/gdb-xml/sparc32-fpu.xml
new file mode 100644
index 00000000000..38217ca7a92
--- /dev/null
+++ b/gdb-xml/sparc32-fpu.xml
@@ -0,0 +1,42 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2013-2026 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.sparc.fpu">
+ <reg name="f0" bitsize="32" type="ieee_single" regnum="32"/>
+ <reg name="f1" bitsize="32" type="ieee_single" regnum="33"/>
+ <reg name="f2" bitsize="32" type="ieee_single" regnum="34"/>
+ <reg name="f3" bitsize="32" type="ieee_single" regnum="35"/>
+ <reg name="f4" bitsize="32" type="ieee_single" regnum="36"/>
+ <reg name="f5" bitsize="32" type="ieee_single" regnum="37"/>
+ <reg name="f6" bitsize="32" type="ieee_single" regnum="38"/>
+ <reg name="f7" bitsize="32" type="ieee_single" regnum="39"/>
+ <reg name="f8" bitsize="32" type="ieee_single" regnum="40"/>
+ <reg name="f9" bitsize="32" type="ieee_single" regnum="41"/>
+ <reg name="f10" bitsize="32" type="ieee_single" regnum="42"/>
+ <reg name="f11" bitsize="32" type="ieee_single" regnum="43"/>
+ <reg name="f12" bitsize="32" type="ieee_single" regnum="44"/>
+ <reg name="f13" bitsize="32" type="ieee_single" regnum="45"/>
+ <reg name="f14" bitsize="32" type="ieee_single" regnum="46"/>
+ <reg name="f15" bitsize="32" type="ieee_single" regnum="47"/>
+ <reg name="f16" bitsize="32" type="ieee_single" regnum="48"/>
+ <reg name="f17" bitsize="32" type="ieee_single" regnum="49"/>
+ <reg name="f18" bitsize="32" type="ieee_single" regnum="50"/>
+ <reg name="f19" bitsize="32" type="ieee_single" regnum="51"/>
+ <reg name="f20" bitsize="32" type="ieee_single" regnum="52"/>
+ <reg name="f21" bitsize="32" type="ieee_single" regnum="53"/>
+ <reg name="f22" bitsize="32" type="ieee_single" regnum="54"/>
+ <reg name="f23" bitsize="32" type="ieee_single" regnum="55"/>
+ <reg name="f24" bitsize="32" type="ieee_single" regnum="56"/>
+ <reg name="f25" bitsize="32" type="ieee_single" regnum="57"/>
+ <reg name="f26" bitsize="32" type="ieee_single" regnum="58"/>
+ <reg name="f27" bitsize="32" type="ieee_single" regnum="59"/>
+ <reg name="f28" bitsize="32" type="ieee_single" regnum="60"/>
+ <reg name="f29" bitsize="32" type="ieee_single" regnum="61"/>
+ <reg name="f30" bitsize="32" type="ieee_single" regnum="62"/>
+ <reg name="f31" bitsize="32" type="ieee_single" regnum="63"/>
+</feature>
--
2.52.0