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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a316eb08sm25010325e9.0.2026.02.19.11.21.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 19 Feb 2026 11:21:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771528906; x=1772133706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iBslSAoVL6gslfaibh72PbWC4QaSzp3PaLMupF2j1EA=; b=K1pqDAmpYgDuBKAwecufOFmEyW/A/aX1YihG5UHh1IMWP6204ghhNMypqbp0r79b9h RHgbRPcSHFpBx8o1g8msw8Ez0/yD6kY7pdUzyTXuSYFC0AuFMDlX3iOrDUhJ5v2X5Xuz tEqUAaSWFuHIz2/PWuRDlr+mBCoVFP43wsCJGs0OJQZ+i9HJYhksot5WRaW6iNlpqx3s tleV29dOlfoblnfkPEhwOhLo9oCiE115oHbu44sjdylO9g1wtJ78jkgyieTAm4clqSag zjlo9D8Wh623iOkB4FlOBgvjEQI27Kh+Cu4gxKrsZ++9ZHk6rCiu30fbaytaMggfb3RE jTUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771528906; x=1772133706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=iBslSAoVL6gslfaibh72PbWC4QaSzp3PaLMupF2j1EA=; b=W/b7OshDNKLRpA0MFWgjUhWCnC/+JVVB+rkU/STS3iJFT8WY5+I3vwsWBN0SFJxMG5 bI7ikodwZ4NoYqMQUCxReOTP4uP83DkqwoQpU875G9DtmIY8ZU6DH2gLkhKykGvxWJmV zGSyzU+CNej4Y3I9djQRTPaXKsOJqz3WHDj6A71tG4jVODsxDpQRFuEC0y0bAD7bbHzL PxyAluOLG1f+E9xLWTUDzPsj+AvSGYq3yCjC/vT6eTPUcp08JgL6RGenZTra33NBfwmk Mt7e0N8u7/p/riFr0ZFCHC+b81vK5J4ULWkfU8EXX8PZna0110aGprYSLXpKrAdrdaQI y/UA== X-Gm-Message-State: AOJu0YxMSEpoXb7EnZYk0U4PpafdszILi8p/9sEhbCLHtnAU1y5/LYKc eq5k4w5krmj6au5qVhpBLjAskIFLVJqv038GwFJXiED2mfud8s7UoJlX+CeIsesZBePQkRB//4X f/VS2enixAg== X-Gm-Gg: AZuq6aIATrKj7X5gwS43YUbIAhglN0FFXQDJ8/vB5gJgcw+N5aOjtds2KlUcjTkJiFx cpupyKJjBpq9r7enLRa/nxuOw16Pdqu3ZvAf3KMBKfs4YoZcHsFeyUtRSi0XqDSYCKX4i8dwIkH gifxy6e+R54bDWjDOHdLBY8+ZXMWqxn46YOwLJI/ErBz49pCKGF24n451/eVRlqTYVyKqZUSmk/ YisE22m+wbkPU1R8P6T8aj0Af9HwAdoXsYIJUoTjQV5scyLReugWZvfSEYhIaa7eqEDAr0RqEih IbpZzrqPWI3vT7XmbvmhvzXVifqt1Sp6DfszBvIoqzeYFbf44n2xEpIN/iyrwTZ84EycEhEePas 15CDH0sRIwX9Sc8wQOxggcZ7iZfOYDVyZ9ck2ZJkb4NGLJkMNl2WSaOId5nTtGhL8jIQsHJ7WRq pUI+8kTiUPitLZJTm05N7DFItxHuwC0PSH/ShcLFDUJjqkisUbqsZVWUWI4Z2vwnkvOZogGtyQ X-Received: by 2002:a05:600c:8b61:b0:47e:e78a:c832 with SMTP id 5b1f17b1804b1-48379c286d4mr306325785e9.37.1771528906207; Thu, 19 Feb 2026 11:21:46 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , Richard Henderson , qemu-s390x@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH v2 15/50] target/sparc: Expose gdbstub registers to sparc32 targets Date: Thu, 19 Feb 2026 20:19:17 +0100 Message-ID: <20260219191955.83815-16-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260219191955.83815-1-philmd@linaro.org> References: <20260219191955.83815-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771529029567158500 Import gdb-xml/sparc32-{cpu,fpu,cp0}.xml from mainstream binutils, tag 'binutils-2_46', found in the gdb/features/sparc/folder [*]. Register them by setting the CPUClass::gdb_core_xml_file field and calling gdb_register_coprocessor() in sparc_cpu_register_gdb_regs(). [*] https://sourceware.org/git/?p=3Dbinutils-gdb.git;a=3Dtree;f=3Dgdb/featu= res/sparc;hb=3Drefs/tags/binutils-2_46 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- configs/targets/sparc-linux-user.mak | 1 + configs/targets/sparc-softmmu.mak | 1 + target/sparc/cpu.c | 2 +- target/sparc/gdbstub.c | 13 +++++---- gdb-xml/sparc32-cp0.xml | 18 ++++++++++++ gdb-xml/sparc32-cpu.xml | 42 ++++++++++++++++++++++++++++ gdb-xml/sparc32-fpu.xml | 42 ++++++++++++++++++++++++++++ 7 files changed, 113 insertions(+), 6 deletions(-) create mode 100644 gdb-xml/sparc32-cp0.xml create mode 100644 gdb-xml/sparc32-cpu.xml create mode 100644 gdb-xml/sparc32-fpu.xml diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-l= inux-user.mak index d3f0716ca2d..01446e28783 100644 --- a/configs/targets/sparc-linux-user.mak +++ b/configs/targets/sparc-linux-user.mak @@ -2,5 +2,6 @@ TARGET_ARCH=3Dsparc TARGET_SYSTBL_ABI=3Dcommon,32 TARGET_SYSTBL=3Dsyscall.tbl TARGET_BIG_ENDIAN=3Dy +TARGET_XML_FILES=3Dgdb-xml/sparc32-cpu.xml gdb-xml/sparc32-fpu.xml gdb-xml= /sparc32-cp0.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-soft= mmu.mak index c4c38946d54..ed846735f41 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,5 +1,6 @@ TARGET_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy +TARGET_XML_FILES=3Dgdb-xml/sparc32-cpu.xml gdb-xml/sparc32-fpu.xml gdb-xml= /sparc32-cp0.xml TARGET_LONG_BITS=3D32 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index d82f858efb1..1493336e7a2 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1095,7 +1095,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, con= st void *data) #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) cc->gdb_core_xml_file =3D "sparc64-cpu.xml"; #else - cc->gdb_num_core_regs =3D 72; + cc->gdb_core_xml_file =3D "sparc32-cpu.xml"; #endif cc->tcg_ops =3D &sparc_tcg_ops; } diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index b5b1494950a..ed52e521dcc 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -43,7 +43,6 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) return 0; } =20 -__attribute__((unused)) static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, = int n) { CPUSPARCState *env =3D cpu_env(cs); @@ -79,7 +78,6 @@ static int sparc_fpu_gdb_read_register(CPUState *cs, GByt= eArray *mem_buf, int n) return 0; } =20 -__attribute__((unused)) static int sparc_cp0_gdb_read_register(CPUState *cs, GByteArray *mem_buf, = int n) { CPUSPARCState *env =3D cpu_env(cs); @@ -154,7 +152,6 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) #endif } =20 -__attribute__((unused)) static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, in= t n) { CPUSPARCState *env =3D cpu_env(cs); @@ -197,7 +194,6 @@ static int sparc_fpu_gdb_write_register(CPUState *cs, u= int8_t *mem_buf, int n) #endif } =20 -__attribute__((unused)) static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, in= t n) { CPUSPARCState *env =3D cpu_env(cs); @@ -271,7 +267,14 @@ static int sparc_cp0_gdb_write_register(CPUState *cs, = uint8_t *mem_buf, int n) void sparc_cpu_register_gdb_regs(CPUState *cs) { #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) - /* Not yet supported */ + gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register, + sparc_fpu_gdb_write_register, + gdb_find_static_feature("sparc32-fpu.xml"), + 0); + gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register, + sparc_cp0_gdb_write_register, + gdb_find_static_feature("sparc32-cp0.xml"), + 0); #else gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register, sparc_fpu_gdb_write_register, diff --git a/gdb-xml/sparc32-cp0.xml b/gdb-xml/sparc32-cp0.xml new file mode 100644 index 00000000000..eacd89cf3b5 --- /dev/null +++ b/gdb-xml/sparc32-cp0.xml @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + diff --git a/gdb-xml/sparc32-cpu.xml b/gdb-xml/sparc32-cpu.xml new file mode 100644 index 00000000000..242295c886e --- /dev/null +++ b/gdb-xml/sparc32-cpu.xml @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/sparc32-fpu.xml b/gdb-xml/sparc32-fpu.xml new file mode 100644 index 00000000000..38217ca7a92 --- /dev/null +++ b/gdb-xml/sparc32-fpu.xml @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.52.0