RISC-V WorldGuard [1] will add 5-bit world_id (WID) to the each memory
transaction on the bus. The wgChecker in front of RAM or peripherals
MMIO could do the access control based on the WID. It is similar to ARM
TrustZone NS bit, but the WID is a 5-bit value.
WID is usually implemented in AXI AxUSER signal (user-defined signals)
in the AXI transaction. As we have a secure bit in MemTxAttrs to emulate
the TrustZone NS bit, which is implemented in AXI AxPROT[1] signal,
I'd like to propose to add world_id field into MemTxAttrs struct.
Since the '_reserved*' fields in MemTxAttr are for padding the struct
to be 8-byte [2], we change the reserved fields from 3 to 2 bytes when
adding 5-bit world_id field.
[1] RISC-V WG:
https://patchew.org/QEMU/20251021155548.584543-1-jim.shu@sifive.com/
[2] Commit 5014e33b1e00d330f13df33c09a3932ac88f8d94
Link: https://lore.kernel.org/r/20250121151322.171832-2-zhao1.liu@intel.com
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Signed-off-by: Jim Shu <jim.shu@sifive.com>
---
include/exec/memattrs.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 52ee9552491..6bde90d482f 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -57,6 +57,11 @@ typedef struct MemTxAttrs {
/* PCI - IOMMU operations, see PCIAddressType */
unsigned int address_type:1;
+ /*
+ * RISC-V WorldGuard: the 5-bit WID field of memory access.
+ */
+ unsigned int world_id:5;
+
/*
* Bus masters which don't specify any attributes will get this
* (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
@@ -66,8 +71,7 @@ typedef struct MemTxAttrs {
*/
bool unspecified;
- uint8_t _reserved1;
- uint16_t _reserved2;
+ uint16_t _reserved1;
} MemTxAttrs;
QEMU_BUILD_BUG_ON(sizeof(MemTxAttrs) > 8);
--
2.43.0