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Tsirkin" , Peter Xu , David Hildenbrand , =?UTF-8?q?Cl=C3=A9ment=20Mathieu--Drif?= , Jim Shu , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Daniel Henrique Barboza Subject: [PATCH] exec: Add RISC-V WorldGuard WID field to MemTxAttrs Date: Mon, 9 Feb 2026 19:58:44 +0800 Message-ID: <20260209115846.2276651-1-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_SBL=1.623 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1770638408693154100 RISC-V WorldGuard [1] will add 5-bit world_id (WID) to the each memory transaction on the bus. The wgChecker in front of RAM or peripherals MMIO could do the access control based on the WID. It is similar to ARM TrustZone NS bit, but the WID is a 5-bit value. WID is usually implemented in AXI AxUSER signal (user-defined signals) in the AXI transaction. As we have a secure bit in MemTxAttrs to emulate the TrustZone NS bit, which is implemented in AXI AxPROT[1] signal, I'd like to propose to add world_id field into MemTxAttrs struct. Since the '_reserved*' fields in MemTxAttr are for padding the struct to be 8-byte [2], we change the reserved fields from 3 to 2 bytes when adding 5-bit world_id field. [1] RISC-V WG: https://patchew.org/QEMU/20251021155548.584543-1-jim.shu@sifive.com/ [2] Commit 5014e33b1e00d330f13df33c09a3932ac88f8d94 Link: https://lore.kernel.org/r/20250121151322.171832-2-zhao1.liu@intel= .com Cc: Paolo Bonzini Cc: Peter Xu Cc: Philippe Mathieu-Daud=C3=A9 Cc: Richard Henderson Cc: Daniel Henrique Barboza Signed-off-by: Jim Shu --- include/exec/memattrs.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 52ee9552491..6bde90d482f 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -57,6 +57,11 @@ typedef struct MemTxAttrs { /* PCI - IOMMU operations, see PCIAddressType */ unsigned int address_type:1; =20 + /* + * RISC-V WorldGuard: the 5-bit WID field of memory access. + */ + unsigned int world_id:5; + /* * Bus masters which don't specify any attributes will get this * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can @@ -66,8 +71,7 @@ typedef struct MemTxAttrs { */ bool unspecified; =20 - uint8_t _reserved1; - uint16_t _reserved2; + uint16_t _reserved1; } MemTxAttrs; =20 QEMU_BUILD_BUG_ON(sizeof(MemTxAttrs) > 8); --=20 2.43.0