Hi,

Changes from RFCv1:
https://lore.kernel.org/qemu-devel/20251210133737.78257-1-skolothumtho@nvidia.com/

 - Rebased on top of latest master with SMMUv3 accel support.
 - RFC tag dropped as the SMMUv3 accel series is now applied.
 - Addressed feedback on RFC and collected tags. Thanks!
 - Introduces an ops interface to factor CMDQV specific
   behavior out of the base implementation(patch #5)
 - Split read/write implementation to multiple patches(10-12)
 - Only map the VINTF page0 MMIO region to guest(patch #15)
 - Add per-device identifier property to SMMUv3 dev so that
   both Tegra DSDT and SMMUv3 IORT uses the same identifier
   (patch #22)
 - TODO: There was a suggestion to factor out common code for vEVNTQ
   read side function. I have left it as is for now.

Please find the complete branch here:
https://github.com/shamiali2008/qemu-master/tree/master-veventq-v4-vcmdq-v2

I have sanity tested this on an NVIDIA GRACE platform and will
continue with additional tests.

Feedback and testing are very welcome.

Thanks,
Shameer

---
Background(from RFCv1):

Thanks to Nicolin for the initial patches and testing on which this
is based.

Tegra241 CMDQV extends SMMUv3 by allocating per-VM "virtual interfaces"
(VINTFs), each hosting up to 128 VCMDQs.

Each VINTF exposes two 64KB MMIO pages:
 - Page0 – guest owned control and status registers (directly mapped
           into the VM)
 - Page1 – queue configuration registers (trapped/emulated by QEMU)

Unlike the standard SMMU CMDQ, a guest owned Tegra241 VCMDQ does not
support the full command set. Only a subset, primarily invalidation
related commands, is accepted by the CMDQV hardware. For this reason,
a distinct CMDQV device must be exposed to the guest, and the guest OS
must include a Tegra241 CMDQV aware driver to take advantage of the
hardware acceleration.

VCMDQ support is integrated via the IOMMU_HW_QUEUE_ALLOC mechanism,
allowing QEMU to attach guest configured VCMDQ buffers to the
underlying CMDQV hardware through IOMMUFD. The Linux kernel already
supports the full CMDQV virtualisation model via IOMMUFD[0].

Summary of QEMU changes:

 - Integrated into the existing SMMUv3 accel path via a
   "tegra241-cmdqv" property.
 - Support for allocating vIOMMU objects of type
   IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV.
 - Mapping and emulation of the CMDQV MMIO register layout.
 - VCMDQ/VINTF read/write handling and queue allocation using IOMMUFD
   APIs.
 - Reset and initialisation hooks, including checks for at least one
   cold-plugged device.
 - CMDQV hardware reads guest queue memory using host physical addresses
   provided through IOMMUFD, which requires that the VCMDQ buffer be
   physically contiguous not only in guest PA space but also in host
   PA space. When Tegra241 CMDQV is enabled, QEMU must therefore only
   expose a CMDQV size that the host can reliably back with contiguous
   physical memory. Because of this constraint, it is suggested to use
   huge pages to back the guest RAM.
 - ACPI DSDT node generation for CMDQV devices on the virt machine.
---

Nicolin Chen (14):
  backends/iommufd: Update iommufd_backend_get_device_info
  backends/iommufd: Update iommufd_backend_alloc_viommu to allow user
    ptr
  backends/iommufd: Introduce iommufd_backend_alloc_hw_queue
  backends/iommufd: Introduce iommufd_backend_viommu_mmap
  hw/arm/tegra241-cmdqv: Implement CMDQV init and vIOMMU allocation
  hw/arm/tegra241-cmdqv: mmap VINTF Page0 for CMDQV
  hw/arm/tegra241-cmdqv: Emulate global CMDQV registers
  hw/arm/tegra241-cmdqv: Emulate global and VINTF VCMDQ register reads
  hw/arm/tegra241-cmdqv: Emulate global and VINTF VCMDQ register writes
  hw/arm/tegra241-cmdqv: Allocate HW VCMDQs on base register programming
  hw/arm/tegra241-cmdqv: map VINTF page0 MMIO region
  hw/arm/tegra241-cmdqv: Add reset handler
  hw/arm/tegra241-cmdqv: Limit queue size based on backend page size
  hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT

Shameer Kolothum (10):
  hw/arm/smmuv3-accel: Introduce CMDQV ops interface
  hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops backend stub
  hw/arm/smmuv3-accel: Wire CMDQV ops into accel lifecycle
  system/physmem: Add address_space_is_ram() helper
  hw/arm/tegra241-cmdqv: Use VINTF page0 for mapped VCMDQ registers
  hw/arm/tegra241-cmdqv: Add vEVENTQ allocation and free
  hw/arm/tegra241-cmdqv: Read and propagate Tegra241 CMDQV errors
  virt-acpi-build: Rename AcpiIortSMMUv3Dev to AcpiSMMUv3Dev
  hw/arm/smmuv3: Add per-device identifier poroperty
  hw/arm/smmuv3: Add tegra241-cmdqv property for SMMUv3 device

 backends/iommufd.c       |  65 ++++
 backends/trace-events    |   4 +-
 hw/arm/Kconfig           |   5 +
 hw/arm/meson.build       |   3 +-
 hw/arm/smmuv3-accel.c    |  73 +++-
 hw/arm/smmuv3-accel.h    |  24 ++
 hw/arm/smmuv3.c          |  15 +
 hw/arm/tegra241-cmdqv.c  | 778 +++++++++++++++++++++++++++++++++++++++
 hw/arm/tegra241-cmdqv.h  | 340 +++++++++++++++++
 hw/arm/trace-events      |   5 +
 hw/arm/virt-acpi-build.c | 121 ++++--
 hw/arm/virt.c            |   3 +
 hw/vfio/iommufd.c        |   4 +-
 include/hw/arm/smmuv3.h  |   3 +
 include/system/iommufd.h |  17 +
 include/system/memory.h  |  10 +
 system/physmem.c         |  11 +
 17 files changed, 1447 insertions(+), 34 deletions(-)
 create mode 100644 hw/arm/tegra241-cmdqv.c
 create mode 100644 hw/arm/tegra241-cmdqv.h

-- 
2.43.0