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charset="utf-8" From: Nicolin Chen The updated IOMMUFD uAPI introduces the ability for userspace to request a specific hardware info data type via IOMMU_GET_HW_INFO. Update iommufd_backend_get_device_info() to set IOMMU_HW_INFO_FLAG_INPUT_TYPE when a non-zero type is supplied, and adjust all callers to pass a type value explicitly initialised to zero (IOMMU_HW_INFO_TYPE_DEFAULT) when no specific type is requested. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 7 +++++++ hw/arm/smmuv3-accel.c | 2 +- hw/vfio/iommufd.c | 4 ++-- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/backends/iommufd.c b/backends/iommufd.c index acfab907c0..5daefe505e 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -387,16 +387,23 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend = *be, return true; } =20 +/* + * @type can carry a desired HW info type defined in the uapi headers. If = caller + * doesn't have one, indicating it wants the default type, then @type shou= ld be + * zeroed (i.e. IOMMU_HW_INFO_TYPE_DEFAULT). + */ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid, uint32_t *type, void *data, uint32_t = len, uint64_t *caps, uint8_t *max_pasid_lo= g2, Error **errp) { struct iommu_hw_info info =3D { + .flags =3D (*type) ? IOMMU_HW_INFO_FLAG_INPUT_TYPE : 0, .size =3D sizeof(info), .dev_id =3D devid, .data_len =3D len, .data_uptr =3D (uintptr_t)data, + .in_data_type =3D *type, }; =20 if (ioctl(be->fd, IOMMU_GET_HW_INFO, &info)) { diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index beffb8aa94..14ea4eac37 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -127,7 +127,7 @@ smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDev= iceIOMMUFD *idev, Error **errp) { struct iommu_hw_info_arm_smmuv3 info; - uint32_t data_type; + uint32_t data_type =3D 0; uint64_t caps; =20 if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 131612eb83..d0f124300d 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -349,7 +349,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, ERRP_GUARD(); IOMMUFDBackend *iommufd =3D vbasedev->iommufd; VFIOContainer *bcontainer =3D VFIO_IOMMU(container); - uint32_t type, flags =3D 0; + uint32_t type =3D 0, flags =3D 0; uint64_t hw_caps; VendorCaps caps; VFIOIOASHwpt *hwpt; @@ -938,7 +938,7 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *= hiod, void *opaque, HostIOMMUDeviceIOMMUFD *idev; HostIOMMUDeviceCaps *caps =3D &hiod->caps; VendorCaps *vendor_caps =3D &caps->vendor_caps; - enum iommu_hw_info_type type; + enum iommu_hw_info_type type =3D 0; uint8_t max_pasid_log2; uint64_t hw_caps; =20 --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1770389432; cv=pass; d=zohomail.com; s=zohoarc; b=GS6s/R7auA4JYuUeGGKzqN/zGbHc5jqhpnJrS74bl+FfZCIxgp+1ema30vdGg1Idhm6djRDjhby0D3IyfrKCB6TNdbQfFFvPj8a4uSW21YUjBri3U2gJ9Mbvug/3F0cjliefZdIM7QINAaQtGxkUGd14U1COQMaza6fuxQ2iBU4= ARC-Message-Signature: i=2; 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charset="utf-8" From: Nicolin Chen The updated IOMMUFD VIOMMU_ALLOC uAPI allows userspace to provide a data buffer when creating a vIOMMU (e.g. for Tegra241 CMDQV). Extend iommufd_backend_alloc_viommu() to pass a user pointer and size to the kernel. Update the caller accordingly. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 4 ++++ backends/trace-events | 2 +- hw/arm/smmuv3-accel.c | 4 ++-- include/system/iommufd.h | 1 + 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/backends/iommufd.c b/backends/iommufd.c index 5daefe505e..8ab26eb786 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -460,6 +460,7 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *b= e, uint32_t id, =20 bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_viommu_id, Error **errp) { int ret; @@ -468,11 +469,14 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be,= uint32_t dev_id, .type =3D viommu_type, .dev_id =3D dev_id, .hwpt_id =3D hwpt_id, + .data_len =3D data_len, + .data_uptr =3D (uintptr_t)data_ptr, }; =20 ret =3D ioctl(be->fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu); =20 trace_iommufd_backend_alloc_viommu(be->fd, dev_id, viommu_type, hwpt_i= d, + data_len, (uintptr_t)data_ptr, alloc_viommu.out_viommu_id, ret); if (ret) { error_setg_errno(errp, errno, "IOMMU_VIOMMU_ALLOC failed"); diff --git a/backends/trace-events b/backends/trace-events index b9365113e7..332888a576 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -21,7 +21,7 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret= ) " iommufd=3D%d id=3D%d (% iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" -iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" +iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t data_len, uint64_t data_ptr, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_len=3D%u d= ata_ptr=3D0x%"PRIx64" viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" =20 diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 14ea4eac37..9036b14601 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -531,8 +531,8 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *idev, IOMMUFDViommu *viommu; =20 if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, - s2_hwpt_id, &viommu_id, errp)) { + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, + NULL, 0, &viommu_id, errp)) { return false; } =20 diff --git a/include/system/iommufd.h b/include/system/iommufd.h index e4ca16da70..5ef23ad9e1 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -87,6 +87,7 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint3= 2_t dev_id, Error **errp); bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_hwpt, Error **errp); =20 bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Nicolin Chen Add a helper to allocate an iommufd backed HW queue for a vIOMMU. While at it, define a struct IOMMUFDHWqueue for use by vendor implementations. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 32 ++++++++++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 12 ++++++++++++ 3 files changed, 45 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 8ab26eb786..c6b79da0d4 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -546,6 +546,38 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, return true; } =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + enum iommu_hw_queue_type queue_type, + uint32_t index, uint64_t addr, + uint64_t length, uint32_t *out_hw_queu= e_id, + Error **errp) +{ + int ret; + struct iommu_hw_queue_alloc alloc_hw_queue =3D { + .size =3D sizeof(alloc_hw_queue), + .flags =3D 0, + .viommu_id =3D viommu_id, + .type =3D queue_type, + .index =3D index, + .nesting_parent_iova =3D addr, + .length =3D length, + }; + + ret =3D ioctl(be->fd, IOMMU_HW_QUEUE_ALLOC, &alloc_hw_queue); + + trace_iommufd_backend_alloc_hw_queue(be->fd, viommu_id, queue_type, + index, addr, length, + alloc_hw_queue.out_hw_queue_id, r= et); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_HW_QUEUE_ALLOC failed"); + return false; + } + + g_assert(out_hw_queue_id); + *out_hw_queue_id =3D alloc_hw_queue.out_hw_queue_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 332888a576..3e70338750 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -24,6 +24,7 @@ iommufd_backend_invalidate_cache(int iommufd, uint32_t id= , uint32_t data_type, u iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t data_len, uint64_t data_ptr, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_len=3D%u d= ata_ptr=3D0x%"PRIx64" viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" +iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 5ef23ad9e1..f72ad545f8 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -63,6 +63,12 @@ typedef struct IOMMUFDVeventq { uint32_t veventq_fd; } IOMMUFDVeventq; =20 +/* HW queue object for a vIOMMU-specific HW-accelerated queue */ +typedef struct IOMMUFDHWqueue { + IOMMUFDViommu *viommu; + uint32_t hw_queue_id; +} IOMMUFDHWqueue; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -99,6 +105,12 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, = uint32_t viommu_id, uint32_t *out_veventq_id, uint32_t *out_veventq_fd, Error **errp); =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + enum iommu_hw_queue_type queue_type, + uint32_t index, uint64_t addr, + uint64_t length, uint32_t *out_hw_queu= e_id, + Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F68.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9507 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=skolothumtho@nvidia.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1770389588248158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a backend helper to mmap hardware MMIO regions exposed via iommufd for a vIOMMU instance. This allows user space to access HW-accelerated MMIO pages provided by the vIOMMU. The caller is responsible for unmapping the returned region. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 22 ++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 4 ++++ 3 files changed, 27 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index c6b79da0d4..9e30501d38 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -578,6 +578,28 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, return true; } =20 +/* + * Helper to mmap HW MMIO regions exposed via iommufd for a vIOMMU instanc= e. + * The caller is responsible for unmapping the mapped region. + */ +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp) +{ + g_assert(viommu_id); + g_assert(out_ptr); + + *out_ptr =3D mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, be->= fd, + offset); + trace_iommufd_backend_viommu_mmap(be->fd, viommu_id, size, offset); + if (*out_ptr =3D=3D MAP_FAILED) { + error_setg_errno(errp, errno, "IOMMUFD vIOMMU mmap failed"); + return false; + } + + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 3e70338750..f824a8d197 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -25,6 +25,7 @@ iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id= , uint32_t type, uint32 iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" +iommufd_backend_viommu_mmap(int iommufd, uint32_t viommu_id, uint64_t size= , uint64_t offset) " iommufd=3D%d viommu_id=3D%u size=3D0x%"PRIx64" offset= =3D0x%"PRIx64 =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index f72ad545f8..87ddc39041 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -111,6 +111,10 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, uint64_t length, uint32_t *out_hw_queu= e_id, Error **errp); =20 +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1770389501; cv=pass; d=zohomail.com; s=zohoarc; b=RmVWskdYCQVNJAssFTtvUjE2N5+WrXEw6MxpvQQeEwFqW9Es9nKxO6Y/mLl9IGm1pbhYXxfHQSN7RlFEHhZ6hl0EKZongvQFc52iqdA53+LK+cNudSz5cEbMlAXA7dwrgUz6LMXUCP8s7rj7HC4JbYZQI5nmw9aMs44SoPGRR8w= ARC-Message-Signature: i=2; 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charset="utf-8" CMDQ-Virtualization (CMDQV) is a hardware extension to SMMUv3 that enables virtualization of multiple command queues (VCMDQs). CMDQV support is a specialization of the IOMMUFD backed accelerated SMMUv3 path. Introduce an ops interface to factor CMDQV specific initialization and CMDQV vIOMMU/vEVENTQ allocation behavior out of the base implementation. The ops pointer and associated state are stored in the accelerated SMMUv3 state. No functional change Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index c9c10e55c3..ca087240e5 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -16,6 +16,23 @@ #endif #include CONFIG_DEVICES =20 +/* + * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to + * support multiple VCMDQs with virtualization capabilities. + * CMDQV specific behavior is factored behind this ops interface. + */ +typedef struct SMMUv3AccelCmdqvOps { + bool (*init)(SMMUv3State *s, Error **errp); + bool (*alloc_viommu)(SMMUv3State *s, + HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, + Error **errp); + void (*free_viommu)(SMMUv3State *s); + bool (*alloc_veventq)(SMMUv3State *s, Error **errp); + void (*free_veventq)(SMMUv3State *s); + void (*reset)(SMMUv3State *s); +} SMMUv3AccelCmdqvOps; + /* * Represents an accelerated SMMU instance backed by an iommufd vIOMMU obj= ect. * Holds bypass and abort proxy HWPT IDs used for device attachment. @@ -28,6 +45,8 @@ typedef struct SMMUv3AccelState { uint32_t bypass_hwpt_id; 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charset="utf-8" Introduce a Tegra241 CMDQV backend that plugs into the SMMUv3 accelerated CMDQV ops interface. This patch wires up the Tegra241 CMDQV backend and provides a stub implementation for CMDQV initialization, vIOMMU/vEVENTQ allocation and reset handling. Functional CMDQV support is added in follow-up patches. Signed-off-by: Shameer Kolothum --- hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 1 + hw/arm/tegra241-cmdqv.c | 60 +++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 23 ++++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 hw/arm/tegra241-cmdqv.c create mode 100644 hw/arm/tegra241-cmdqv.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c66c452737..3305c6e76e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -626,6 +626,10 @@ config FSL_IMX8MP_EVK depends on TCG select FSL_IMX8MP =20 +config TEGRA241_CMDQV + bool + depends on ARM_SMMUV3_ACCEL + config ARM_SMMUV3_ACCEL bool depends on ARM_SMMUV3 @@ -633,6 +637,7 @@ config ARM_SMMUV3_ACCEL config ARM_SMMUV3 bool select ARM_SMMUV3_ACCEL if IOMMUFD + imply TEGRA241_CMDQV =20 config FSL_IMX6UL bool diff --git a/hw/arm/meson.build b/hw/arm/meson.build index c250487e64..4ec91db50a 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -86,6 +86,7 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: fil= es('fsl-imx8mp.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c= ')) +arm_ss.add(when: 'CONFIG_TEGRA241_CMDQV', if_true: files('tegra241-cmdqv.c= ')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_common_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c new file mode 100644 index 0000000000..6f30ca035b --- /dev/null +++ b/hw/arm/tegra241-cmdqv.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2025, NVIDIA CORPORATION + * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + +static void tegra241_cmdqv_free_veventq(SMMUv3State *s) +{ +} + +static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static void tegra241_cmdqv_free_viommu(SMMUv3State *s) +{ +} + +static bool +tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static void tegra241_cmdqv_reset(SMMUv3State *s) +{ +} + +static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops_impl =3D { + .init =3D tegra241_cmdqv_init, + .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, + .free_viommu =3D tegra241_cmdqv_free_viommu, + .alloc_veventq =3D tegra241_cmdqv_alloc_veventq, + .free_veventq =3D tegra241_cmdqv_free_veventq, + .reset =3D tegra241_cmdqv_reset, +}; + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void) +{ + return &tegra241_cmdqv_ops_impl; +} diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h new file mode 100644 index 0000000000..81c9deb384 --- /dev/null +++ b/hw/arm/tegra241-cmdqv.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2025, NVIDIA CORPORATION + * NVIDIA Tegra241 CMDQ-Virtualiisation extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_TEGRA241_CMDQV_H +#define HW_TEGRA241_CMDQV_H + +#include CONFIG_DEVICES + +#ifdef CONFIG_TEGRA241_CMDQV +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void); 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charset="utf-8" Integrate CMDQV ops support into the accelerated SMMUv3 path. When CMDQV is enabled, the backend ops are used to initialize CMDQV state and to allocate the vIOMMU instance. The current implementation connects the Tegra241 CMDQV backend, but does not enable functional support yet. No functional changes intended. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 65 ++++++++++++++++++++++++++++++++++++----- hw/arm/smmuv3-accel.h | 5 ++++ hw/arm/smmuv3.c | 1 + include/hw/arm/smmuv3.h | 2 ++ 4 files changed, 66 insertions(+), 7 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 9036b14601..b1a8ab79b5 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -18,6 +18,7 @@ =20 #include "smmuv3-internal.h" #include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" =20 /* * The root region aliases the global system memory, and shared_as_sysmem @@ -520,6 +521,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *idev, Error **errp) { SMMUv3AccelState *accel =3D s->s_accel; + const SMMUv3AccelCmdqvOps *cmdqv_ops =3D accel->cmdqv_ops; struct iommu_hwpt_arm_smmuv3 bypass_data =3D { .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, }; @@ -530,12 +532,24 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, uint32_t viommu_id, hwpt_id; IOMMUFDViommu *viommu; =20 - if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, - NULL, 0, &viommu_id, errp)) { + if (cmdqv_ops && (!cmdqv_ops->alloc_viommu || !cmdqv_ops->alloc_vevent= q)) { + error_setg(errp, "CMDQV vIOMMU allocation not supported"); return false; } =20 + if (cmdqv_ops) { + if (!cmdqv_ops->alloc_viommu(s, idev, &viommu_id, errp)) { + return false; + } + } else { + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, NULL, 0, &viommu_id, + errp)) { + return false; + } + } + viommu =3D g_new0(IOMMUFDViommu, 1); viommu->viommu_id =3D viommu_id; viommu->s2_hwpt_id =3D s2_hwpt_id; @@ -565,13 +579,21 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, goto free_bypass_hwpt; } =20 + if (cmdqv_ops && !cmdqv_ops->alloc_veventq(s, errp)) { + goto free_veventq; + } + /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */ hwpt_id =3D smmuv3_accel_gbpa_hwpt(s, accel); if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) { - goto free_veventq; + goto free_cmdqv_veventq; } return true; =20 +free_cmdqv_veventq: + if (cmdqv_ops && cmdqv_ops->free_veventq) { + cmdqv_ops->free_veventq(s); + } free_veventq: smmuv3_accel_free_veventq(accel); free_bypass_hwpt: @@ -579,7 +601,11 @@ free_bypass_hwpt: free_abort_hwpt: iommufd_backend_free_id(idev->iommufd, accel->abort_hwpt_id); free_viommu: - iommufd_backend_free_id(idev->iommufd, viommu->viommu_id); + if (cmdqv_ops && cmdqv_ops->free_viommu) { + cmdqv_ops->free_viommu(s); + } else { + iommufd_backend_free_id(idev->iommufd, viommu->viommu_id); + } g_free(viommu); accel->viommu =3D NULL; return false; @@ -865,8 +891,17 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Err= or **errp) =20 void smmuv3_accel_reset(SMMUv3State *s) { - /* Attach a HWPT based on GBPA reset value */ - smmuv3_accel_attach_gbpa_hwpt(s, NULL); + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel) { + return; + } + /* Attach a HWPT based on GBPA reset value */ + smmuv3_accel_attach_gbpa_hwpt(s, NULL); + + if (accel->cmdqv_ops && accel->cmdqv_ops->reset) { + accel->cmdqv_ops->reset(s); + } } =20 static void smmuv3_accel_as_init(SMMUv3State *s) @@ -886,6 +921,22 @@ static void smmuv3_accel_as_init(SMMUv3State *s) address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem"); } =20 +bool smmuv3_accel_cmdqv_init(SMMUv3State *s, Error **errp) +{ + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel || !s->tegra241_cmdqv) { + return true; + } + + accel->cmdqv_ops =3D tegra241_cmdqv_ops(); + if (!accel->cmdqv_ops || !accel->cmdqv_ops->init) { + error_setg(errp, "CMDQV support not available"); + return false; + } + return accel->cmdqv_ops->init(s, errp); +} + void smmuv3_accel_init(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index ca087240e5..33da37bfc1 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -74,6 +74,7 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd= , SMMUDevice *sdev, void smmuv3_accel_idr_override(SMMUv3State *s); bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp); void smmuv3_accel_reset(SMMUv3State *s); +bool smmuv3_accel_cmdqv_init(SMMUv3State *s, Error **errp); #else static inline void smmuv3_accel_init(SMMUv3State *s) { @@ -110,6 +111,10 @@ static inline bool smmuv3_accel_alloc_veventq(SMMUv3St= ate *s, Error **errp) static inline void smmuv3_accel_reset(SMMUv3State *s) { } +static bool smmuv3_accel_cmdqv_init(SMMUv3State *s, Error **errp) +{ + return true; +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 148af80efd..7858bf2c33 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2034,6 +2034,7 @@ static void smmu_realize(DeviceState *d, Error **errp) =20 smmu_init_irq(s, dev); smmuv3_init_id_regs(s); + smmuv3_accel_cmdqv_init(s, errp); } =20 static const VMStateDescription vmstate_smmuv3_queue =3D { diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 26b2fc42fd..87926f8cb3 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -73,6 +73,8 @@ struct SMMUv3State { bool ats; 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charset="utf-8" From: Nicolin Chen Add initial Tegra241 CMDQV support by wiring up initialization and IOMMUFD backed vIOMMU allocation. The CMDQV MMIO region and IRQ are registered, while register handling remains a stub and will be completed in subsequent patches. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 55 ++++++++++++++++++++++++++++++++++++++--- hw/arm/tegra241-cmdqv.h | 19 ++++++++++++++ 2 files changed, 70 insertions(+), 4 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 6f30ca035b..596b1c5595 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -13,6 +13,16 @@ #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned = size) +{ + return 0; +} + +static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t val= ue, + unsigned size) +{ +} + static void tegra241_cmdqv_free_veventq(SMMUv3State *s) { } @@ -25,24 +35,61 @@ static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s= , Error **errp) =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + IOMMUFDViommu *viommu =3D accel->viommu; + + if (!viommu) { + return; + } + iommufd_backend_free_id(viommu->iommufd, viommu->viommu_id); } =20 static bool tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, uint32_t *out_viommu_id, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, + idev->hwpt_id, &cmdqv->cmdqv_data, + sizeof(cmdqv->cmdqv_data), out_viomm= u_id, + errp)) { + error_append_hint(errp, "Tegra241 CMDQV support unavailable"); + return false; + } + return true; } =20 static void tegra241_cmdqv_reset(SMMUv3State *s) { } =20 +static const MemoryRegionOps mmio_cmdqv_ops =3D { + .read =3D tegra241_cmdqv_read, + .write =3D tegra241_cmdqv_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(OBJECT(s)); + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv; + + if (!accel) { + error_setg(errp, "Tegra241 CMDQV requires SMMUv3 acceleration"); + return false; + } + + cmdqv =3D g_new0(Tegra241CMDQV, 1); + memory_region_init_io(&cmdqv->mmio_cmdqv, OBJECT(s), &mmio_cmdqv_ops, = cmdqv, + "tegra241-cmdqv", TEGRA241_CMDQV_IO_LEN); + sysbus_init_mmio(sbd, &cmdqv->mmio_cmdqv); + sysbus_init_irq(sbd, &cmdqv->irq); + cmdqv->s_accel =3D accel; + accel->cmdqv =3D cmdqv; + return true; } =20 static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops_impl =3D { diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 81c9deb384..6ea0087f61 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,8 +10,27 @@ #ifndef HW_TEGRA241_CMDQV_H #define HW_TEGRA241_CMDQV_H =20 +#include "smmuv3-accel.h" #include CONFIG_DEVICES =20 +/* + * Tegra241 CMDQV MMIO layout (64KB pages): + * + * 0x00000: Global CMDQV registers + * 0x10000: Global VCMDQ registers, page 0 + * 0x20000: Global VCMDQ registers, page 1 + * 0x30000: VINTF0 logical VCMDQ registers, page 0 + * 0x40000: VINTF0 logical VCMDQ registers, page 1 + */ +#define TEGRA241_CMDQV_IO_LEN 0x50000 + +typedef struct Tegra241CMDQV { + struct iommu_viommu_tegra241_cmdqv cmdqv_data; + SMMUv3AccelState *s_accel; + MemoryRegion mmio_cmdqv; + qemu_irq irq; +} Tegra241CMDQV; + #ifdef CONFIG_TEGRA241_CMDQV const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void); #else --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1770389469; cv=pass; d=zohomail.com; s=zohoarc; b=i7EoIo6EfpG/5staWN9w5UUUi30HDOmzMsyPtdWuqUr+rx7mmPNLaRJPfPJICqDHm75zbEO5z6FDkUYwb/ZCzekrDoRlikidpRCsks0Z7M0hfbwePzDwsi15P04pz3m7Ng+zXM/kv+P5KEzxn5kNQA7cVayWEsMscqFetu4AS8E= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770389469; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" From: Nicolin Chen Tegra241 CMDQV extends SMMUv3 with support for virtual command queues (VCMDQs) exposed via a CMDQV MMIO region. The CMDQV MMIO space is split into 64KB pages as follows: 0x00000: Global CMDQV registers 0x10000: Global VCMDQ registers, Page0 (control/status) 0x20000: Global VCMDQ registers, Page1 (configuration) 0x30000: VINTF0 logical VCMDQ registers, Page0 (control/status) 0x40000: VINTF0 logical VCMDQ registers, Page1 (configuration) Global VCMDQ pages provide a VM wide view of all VCMDQs, while the VINTF pages expose a logical view local to a given VINTF. Although real hardware may support multiple VINTFs, the kernel currently exposes a single VINTF per VM. The kernel provides an mmap offset for the VINTF Page0 region during vIOMMU allocation. However, the logical-to-physical association between VCMDQs and a VINTF is only established after HW_QUEUE allocation. Prior to that, the mapped Page0 does not back any real VCMDQ state. Prepare the VINTF0 Page0 mapping by mmapping the kernel provided region when CMDQV is accessed, while keeping all CMDQV MMIO accesses trapped in QEMU. The mapping is not yet exposed to the guest address space. A subsequent patch will install the RAM backed MMIO subregion for VINTF page0 once HW_QUEUE allocation completes. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 38 ++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 3 +++ 2 files changed, 41 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 596b1c5595..97c9b9c8dc 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -13,14 +13,52 @@ #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **= errp) +{ + IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; + + if (!viommu) { + return true; + } + + g_assert(!cmdqv->vintf_page0); + if (!iommufd_backend_viommu_mmap(viommu->iommufd, viommu->viommu_id, + VINTF_REG_PAGE_SIZE, + cmdqv->cmdqv_data.out_vintf_mmap_offs= et, + &cmdqv->vintf_page0, errp)) { + return false; + } + + return true; +} + static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned = size) { + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + Error *local_err =3D NULL; + + if (!cmdqv->vintf_page0) { + if (!tegra241_cmdqv_mmap_vintf_page0(cmdqv, &local_err)) { + error_report_err(local_err); + local_err =3D NULL; + } + } + return 0; } =20 static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t val= ue, unsigned size) { + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + Error *local_err =3D NULL; + + if (!cmdqv->vintf_page0) { + if (!tegra241_cmdqv_mmap_vintf_page0(cmdqv, &local_err)) { + error_report_err(local_err); + local_err =3D NULL; + } + } } =20 static void tegra241_cmdqv_free_veventq(SMMUv3State *s) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 6ea0087f61..94bef8c978 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -29,8 +29,11 @@ typedef struct Tegra241CMDQV { SMMUv3AccelState *s_accel; MemoryRegion mmio_cmdqv; qemu_irq irq; + void *vintf_page0; } Tegra241CMDQV; =20 +#define VINTF_REG_PAGE_SIZE 0x10000 + #ifdef CONFIG_TEGRA241_CMDQV const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void); 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charset="utf-8" From: Nicolin Chen Tegra241 CMDQV defines a set of global control and status registers used to configure virtual command queue allocation and interrupt behavior. Add read/write emulation for the global CMDQV register page (offset 0x00000), backed by a simple register cache. This includes CONFIG, PARAM, STATUS, VI error and interrupt maps, CMDQ allocation map and the VINTF0 related registers defined in the global CMDQV register space. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 102 +++++++++++++++++++++++++++++++++++++++- hw/arm/tegra241-cmdqv.h | 86 +++++++++++++++++++++++++++++++++ 2 files changed, 187 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 97c9b9c8dc..49fca9d536 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -8,6 +8,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" =20 #include "hw/arm/smmuv3.h" #include "smmuv3-accel.h" @@ -32,6 +33,25 @@ static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMDQ= V *cmdqv, Error **errp) return true; } =20 +static uint64_t tegra241_cmdqv_read_vintf(Tegra241CMDQV *cmdqv, hwaddr off= set) +{ + int i; + + switch (offset) { + case A_VINTF0_CONFIG: + return cmdqv->vintf_config; + case A_VINTF0_STATUS: + return cmdqv->vintf_status; + case A_VINTF0_LVCMDQ_ERR_MAP_0 ... A_VINTF0_LVCMDQ_ERR_MAP_3: + i =3D (offset - A_VINTF0_LVCMDQ_ERR_MAP_0) / 4; + return cmdqv->vintf_cmdq_err_map[i]; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + return 0; + } +} + static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned = size) { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; @@ -44,7 +64,57 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr= offset, unsigned size) } } =20 - return 0; + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x50000)\n", __f= unc__, + offset); + return 0; + } + + switch (offset) { + case A_CONFIG: + return cmdqv->config; + case A_PARAM: + return cmdqv->param; + case A_STATUS: + return cmdqv->status; + case A_VI_ERR_MAP ... A_VI_ERR_MAP_1: + return cmdqv->vi_err_map[(offset - A_VI_ERR_MAP) / 4]; + case A_VI_INT_MASK ... A_VI_INT_MASK_1: + return cmdqv->vi_int_mask[(offset - A_VI_INT_MASK) / 4]; + case A_CMDQ_ERR_MAP ... A_CMDQ_ERR_MAP_3: + return cmdqv->cmdq_err_map[(offset - A_CMDQ_ERR_MAP) / 4]; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_127: + return cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4]; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + return tegra241_cmdqv_read_vintf(cmdqv, offset); + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + return 0; + } +} + +static void tegra241_cmdqv_write_vintf(Tegra241CMDQV *cmdqv, hwaddr offset, + uint64_t value) +{ + switch (offset) { + case A_VINTF0_CONFIG: + /* Strip off HYP_OWN setting from guest kernel */ + value &=3D ~R_VINTF0_CONFIG_HYP_OWN_MASK; + + cmdqv->vintf_config =3D value; + if (value & R_VINTF0_CONFIG_ENABLE_MASK) { + cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + } else { + cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; + } + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + return; + } } =20 static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t val= ue, @@ -59,6 +129,36 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, local_err =3D NULL; } } + + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x50000)\n", __f= unc__, + offset); + return; + } + + switch (offset) { + case A_CONFIG: + cmdqv->config =3D value; + if (value & R_CONFIG_CMDQV_EN_MASK) { + cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; + } else { + cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; + } + break; + case A_VI_INT_MASK ... A_VI_INT_MASK_1: + cmdqv->vi_int_mask[(offset - A_VI_INT_MASK) / 4] =3D value; + break; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_127: + cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; + break; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + tegra241_cmdqv_write_vintf(cmdqv, offset, value); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + } } =20 static void tegra241_cmdqv_free_veventq(SMMUv3State *s) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 94bef8c978..f157c8fd24 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,6 +10,7 @@ #ifndef HW_TEGRA241_CMDQV_H #define HW_TEGRA241_CMDQV_H =20 +#include "hw/core/registerfields.h" #include "smmuv3-accel.h" #include CONFIG_DEVICES =20 @@ -30,8 +31,93 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; void *vintf_page0; + + /* Register Cache */ + uint32_t config; + uint32_t param; + uint32_t status; + uint32_t vi_err_map[2]; + uint32_t vi_int_mask[2]; + uint32_t cmdq_err_map[4]; + uint32_t cmdq_alloc_map[128]; + uint32_t vintf_config; + uint32_t vintf_status; + uint32_t vintf_cmdq_err_map[4]; } Tegra241CMDQV; =20 +/* Global CMDQV MMIO registers (offset 0x00000) */ +REG32(CONFIG, 0x0) +FIELD(CONFIG, CMDQV_EN, 0, 1) +FIELD(CONFIG, CMDQV_PER_CMD_OFFSET, 1, 3) +FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) +FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) +FIELD(CONFIG, CONS_DRAM_EN, 20, 1) + +REG32(PARAM, 0x4) +FIELD(PARAM, CMDQV_VER, 0, 4) +FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) +FIELD(PARAM, CMDQV_NUM_VM_LOG2, 8, 4) +FIELD(PARAM, CMDQV_NUM_SID_PER_VM_LOG2, 12, 4) + +REG32(STATUS, 0x8) +FIELD(STATUS, CMDQV_ENABLED, 0, 1) + +#define A_VI_ERR_MAP 0x14 +#define A_VI_ERR_MAP_1 0x18 +#define V_VI_ERR_MAP_NO_ERROR (0) +#define V_VI_ERR_MAP_ERROR (1) + +#define A_VI_INT_MASK 0x1c +#define A_VI_INT_MASK_1 0x20 +#define V_VI_INT_MASK_NOT_MASKED (0) +#define V_VI_INT_MASK_MASKED (1) + +#define A_CMDQ_ERR_MAP 0x24 +#define A_CMDQ_ERR_MAP_1 0x28 +#define A_CMDQ_ERR_MAP_2 0x2c +#define A_CMDQ_ERR_MAP_3 0x30 + +/* i =3D [0, 127] */ +#define A_CMDQ_ALLOC_MAP_(i) \ + REG32(CMDQ_ALLOC_MAP_##i, 0x200 + i * 4) \ + FIELD(CMDQ_ALLOC_MAP_##i, ALLOC, 0, 1) \ + FIELD(CMDQ_ALLOC_MAP_##i, LVCMDQ, 1, 7) \ + FIELD(CMDQ_ALLOC_MAP_##i, VIRT_INTF_INDX, 15, 6) + +A_CMDQ_ALLOC_MAP_(0) +/* Omitting 1~126 as not being directly called */ +A_CMDQ_ALLOC_MAP_(127) + + +/* i =3D [0, 0] */ +#define A_VINTFi_CONFIG(i) \ + REG32(VINTF##i##_CONFIG, 0x1000 + i * 0x100) \ + FIELD(VINTF##i##_CONFIG, ENABLE, 0, 1) \ + FIELD(VINTF##i##_CONFIG, VMID, 1, 16) \ + FIELD(VINTF##i##_CONFIG, HYP_OWN, 17, 1) + +A_VINTFi_CONFIG(0) + +#define A_VINTFi_STATUS(i) \ + REG32(VINTF##i##_STATUS, 0x1004 + i * 0x100) \ + FIELD(VINTF##i##_STATUS, ENABLE_OK, 0, 1) \ + FIELD(VINTF##i##_STATUS, STATUS, 1, 3) \ + FIELD(VINTF##i##_STATUS, VI_NUM_LVCMDQ, 16, 8) + +A_VINTFi_STATUS(0) + +#define V_VINTF_STATUS_NO_ERROR (0 << 1) +#define V_VINTF_STATUS_VCMDQ_EROR (1 << 1) + +/* i =3D [0, 0], j =3D [0, 3] */ +#define A_VINTFi_LVCMDQ_ERR_MAP_(i, j) \ + REG32(VINTF##i##_LVCMDQ_ERR_MAP_##j, 0x10c0 + j * 4 + i * 0x100) \ + FIELD(VINTF##i##_LVCMDQ_ERR_MAP_##j, LVCMDQ_ERR_MAP, 0, 32) + +A_VINTFi_LVCMDQ_ERR_MAP_(0, 0) +/* Omitting [0][1~2] as not being directly called */ +A_VINTFi_LVCMDQ_ERR_MAP_(0, 3) + #define VINTF_REG_PAGE_SIZE 0x10000 =20 #ifdef CONFIG_TEGRA241_CMDQV --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , Subject: [PATCH v2 11/24] hw/arm/tegra241-cmdqv: Emulate global and VINTF VCMDQ register reads Date: Fri, 6 Feb 2026 14:48:10 +0000 Message-ID: <20260206144823.80655-12-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206144823.80655-1-skolothumtho@nvidia.com> References: <20260206144823.80655-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE32:EE_|IA1PR12MB8312:EE_ X-MS-Office365-Filtering-Correlation-Id: e9edd581-e8d0-4e21-daaa-08de658f0701 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" From: Nicolin Chen Tegra241 CMDQV exposes per-VCMDQ register windows through two MMIO views: -Global VCMDQ registers at 0x10000/0x20000 -VINTF VCMDQ (VI_VCMDQ) registers at 0x30000/0x40000 The VI_VCMDQ register ranges are an alias of the global VCMDQ registers and are only meaningful when a VCMDQ is mapped to a VINTF via ioctl IOMMU_HW_QUEUE_ALLOC. Add read side emulation for both global VCMDQ and VI_VCMDQ register ranges. MMIO accesses are decoded to extract the VCMDQ instance index and normalized to a VCMDQ0_* register offset, allowing a single helper to service all VCMDQ instances. VI_VCMDQ accesses are translated to their equivalent global VCMDQ offsets and reuse the same decoding path. All VCMDQ reads are currently served from cached register state. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 75 +++++++++++++++ hw/arm/tegra241-cmdqv.h | 197 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 272 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 49fca9d536..4d447718d0 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -33,6 +33,46 @@ static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMDQ= V *cmdqv, Error **errp) return true; } =20 +/* + * Read a VCMDQ register using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + * + * All VCMDQ accesses are currently trapped. Use cached registers + */ +static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr off= set0, + int index) +{ + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + return cmdqv->vcmdq_cons_indx[index]; + case A_VCMDQ0_PROD_INDX: + return cmdqv->vcmdq_prod_indx[index]; + case A_VCMDQ0_CONFIG: + return cmdqv->vcmdq_config[index]; + case A_VCMDQ0_STATUS: + return cmdqv->vcmdq_status[index]; + case A_VCMDQ0_GERROR: + return cmdqv->vcmdq_gerror[index]; + case A_VCMDQ0_GERRORN: + return cmdqv->vcmdq_gerrorn[index]; + case A_VCMDQ0_BASE_L: + return cmdqv->vcmdq_base[index]; + case A_VCMDQ0_BASE_H: + return cmdqv->vcmdq_base[index] >> 32; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + return cmdqv->vcmdq_cons_indx_base[index]; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + return cmdqv->vcmdq_cons_indx_base[index] >> 32; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled read access at 0x%" PRIx64 "\n", + __func__, offset0); + return 0; + } +} + static uint64_t tegra241_cmdqv_read_vintf(Tegra241CMDQV *cmdqv, hwaddr off= set) { int i; @@ -56,6 +96,7 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr = offset, unsigned size) { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; Error *local_err =3D NULL; + int index; =20 if (!cmdqv->vintf_page0) { if (!tegra241_cmdqv_mmap_vintf_page0(cmdqv, &local_err)) { @@ -88,6 +129,40 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwadd= r offset, unsigned size) return cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4]; case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: return tegra241_cmdqv_read_vintf(cmdqv, offset); + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ127_GERRORN: + /* + * VI_VCMDQ registers (VINTF logical view) have the same per-VCMDQ + * layout as the global VCMDQ registers, but are based at 0x30000 + * instead of 0x10000. + * + * Subtract 0x20000 to translate a VI_VCMDQ offset into the equiva= lent + * global VCMDQ offset, then fall through to reuse the common VCMDQ + * decoding logic below. + */ + offset -=3D 0x20000; + QEMU_FALLTHROUGH; + case A_VCMDQ0_CONS_INDX ... A_VCMDQ127_GERRORN: + /* + * Decode a per-VCMDQ register access. + * + * VCMDQs are 128 identical instances, each occupying a 0x80-byte = window + * starting at 0x10000. The MMIO offset is decoded to extract the = VCMDQ + * index, and the per-instance offset is normalized to a VCMDQ0_* + * register (@offset0 =3D offset - 0x80 * index). + * + * A single helper then services all VCMDQs, with @index selecting= the + * instance. + */ + index =3D (offset - 0x10000) / 0x80; + return tegra241_cmdqv_read_vcmdq(cmdqv, offset - 0x80 * index, ind= ex); + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ127_CONS_INDX_BASE_DRAM_H: + /* Same as A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ127_GERRORN case ab= ove */ + offset -=3D 0x20000; + QEMU_FALLTHROUGH; + case A_VCMDQ0_BASE_L ... A_VCMDQ127_CONS_INDX_BASE_DRAM_H: + /* Same as A_VCMDQ0_CONS_INDX ... A_VCMDQ127_GERRORN case above */ + index =3D (offset - 0x20000) / 0x80; + return tegra241_cmdqv_read_vcmdq(cmdqv, offset - 0x80 * index, ind= ex); default: qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", __func__, offset); diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index f157c8fd24..1bc03c4f97 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -43,6 +43,14 @@ typedef struct Tegra241CMDQV { uint32_t vintf_config; uint32_t vintf_status; uint32_t vintf_cmdq_err_map[4]; + uint32_t vcmdq_cons_indx[128]; + uint32_t vcmdq_prod_indx[128]; + uint32_t vcmdq_config[128]; + uint32_t vcmdq_status[128]; + uint32_t vcmdq_gerror[128]; + uint32_t vcmdq_gerrorn[128]; + uint64_t vcmdq_base[128]; + uint64_t vcmdq_cons_indx_base[128]; } Tegra241CMDQV; =20 /* Global CMDQV MMIO registers (offset 0x00000) */ @@ -118,7 +126,196 @@ A_VINTFi_LVCMDQ_ERR_MAP_(0, 0) /* Omitting [0][1~2] as not being directly called */ A_VINTFi_LVCMDQ_ERR_MAP_(0, 3) =20 +/* + * VCMDQ register windows. + * + * Page 0 @ 0x10000: VCMDQ control and status registers + * Page 1 @ 0x20000: VCMDQ base and DRAM address registers + */ +#define A_VCMDQi_CONS_INDX(i) \ + REG32(VCMDQ##i##_CONS_INDX, 0x10000 + i * 0x80) \ + FIELD(VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +A_VCMDQi_CONS_INDX(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_CONS_INDX(127) + +#define V_VCMDQ_CONS_INDX_ERR_CERROR_NONE 0 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_OPCODE 1 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ABT 2 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ATC_INV_SYNC 3 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_ACCESS 4 + +#define A_VCMDQi_PROD_INDX(i) \ + REG32(VCMDQ##i##_PROD_INDX, 0x10000 + 0x4 + i * 0x80) \ + FIELD(VCMDQ##i##_PROD_INDX, WR, 0, 20) + +A_VCMDQi_PROD_INDX(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_PROD_INDX(127) + +#define A_VCMDQi_CONFIG(i) \ + REG32(VCMDQ##i##_CONFIG, 0x10000 + 0x8 + i * 0x80) \ + FIELD(VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +A_VCMDQi_CONFIG(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_CONFIG(127) + +#define A_VCMDQi_STATUS(i) \ + REG32(VCMDQ##i##_STATUS, 0x10000 + 0xc + i * 0x80) \ + FIELD(VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +A_VCMDQi_STATUS(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_STATUS(127) + +#define A_VCMDQi_GERROR(i) \ + REG32(VCMDQ##i##_GERROR, 0x10000 + 0x10 + i * 0x80) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +A_VCMDQi_GERROR(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_GERROR(127) + +#define A_VCMDQi_GERRORN(i) \ + REG32(VCMDQ##i##_GERRORN, 0x10000 + 0x14 + i * 0x80) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +A_VCMDQi_GERRORN(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_GERRORN(127) + +#define A_VCMDQi_BASE_L(i) \ + REG32(VCMDQ##i##_BASE_L, 0x20000 + i * 0x80) \ + FIELD(VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ + FIELD(VCMDQ##i##_BASE_L, ADDR, 5, 27) + +A_VCMDQi_BASE_L(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_BASE_L(127) + +#define A_VCMDQi_BASE_H(i) \ + REG32(VCMDQ##i##_BASE_H, 0x20000 + 0x4 + i * 0x80) \ + FIELD(VCMDQ##i##_BASE_H, ADDR, 0, 16) + +A_VCMDQi_BASE_H(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_BASE_H(127) + +#define A_VCMDQi_CONS_INDX_BASE_DRAM_L(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, 0x20000 + 0x8 + i * 0x80) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +A_VCMDQi_CONS_INDX_BASE_DRAM_L(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_CONS_INDX_BASE_DRAM_L(127) + +#define A_VCMDQi_CONS_INDX_BASE_DRAM_H(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, 0x20000 + 0xc + i * 0x80) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +A_VCMDQi_CONS_INDX_BASE_DRAM_H(0) +/* Omitting [1~126] as not being directly called */ +A_VCMDQi_CONS_INDX_BASE_DRAM_H(127) + #define VINTF_REG_PAGE_SIZE 0x10000 +/* + * VI_VCMDQ register windows (VCMDQs mapped via VINTF). + * + * Page 0 @ 0x30000: VI_VCMDQ control and status registers + * Page 1 @ 0x40000: VI_VCMDQ base and DRAM address registers + */ +#define A_VI_VCMDQi_CONS_INDX(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX, 0x30000 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +A_VI_VCMDQi_CONS_INDX(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_CONS_INDX(127) + +#define A_VI_VCMDQi_PROD_INDX(i) \ + REG32(VI_VCMDQ##i##_PROD_INDX, 0x30000 + 0x4 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_PROD_INDX, WR, 0, 20) + +A_VI_VCMDQi_PROD_INDX(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_PROD_INDX(127) + +#define A_VI_VCMDQi_CONFIG(i) \ + REG32(VI_VCMDQ##i##_CONFIG, 0x30000 + 0x8 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +A_VI_VCMDQi_CONFIG(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_CONFIG(127) + +#define A_VI_VCMDQi_STATUS(i) \ + REG32(VI_VCMDQ##i##_STATUS, 0x30000 + 0xc + i * 0x80) \ + FIELD(VI_VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +A_VI_VCMDQi_STATUS(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_STATUS(127) + +#define A_VI_VCMDQi_GERROR(i) \ + REG32(VI_VCMDQ##i##_GERROR, 0x30000 + 0x10 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +A_VI_VCMDQi_GERROR(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_GERROR(127) + +#define A_VI_VCMDQi_GERRORN(i) \ + REG32(VI_VCMDQ##i##_GERRORN, 0x30000 + 0x14 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +A_VI_VCMDQi_GERRORN(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_GERRORN(127) + +#define A_VI_VCMDQi_BASE_L(i) \ + REG32(VI_VCMDQ##i##_BASE_L, 0x40000 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ + FIELD(VI_VCMDQ##i##_BASE_L, ADDR, 5, 27) + +A_VI_VCMDQi_BASE_L(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_BASE_L(127) + +#define A_VI_VCMDQi_BASE_H(i) \ + REG32(VI_VCMDQ##i##_BASE_H, 0x40000 + 0x4 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_BASE_H, ADDR, 0, 16) + +A_VI_VCMDQi_BASE_H(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_BASE_H(127) + +#define A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, 0x40000 + 0x8 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(127) + +#define A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, 0x40000 + 0xc + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(0) +/* Omitting [1~126] as not being directly called */ +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(127) =20 #ifdef CONFIG_TEGRA241_CMDQV const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void); --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1770389502; cv=pass; d=zohomail.com; s=zohoarc; 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RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1770389503818158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen This is the write side counterpart of the VCMDQ read emulation. Add write handling for global VCMDQ and VI_VCMDQ register windows. Per-VCMDQ accesses are decoded into a VCMDQ index and normalized to VCMDQ0_* offsets, reusing the same layout assumptions as the read path. VI_VCMDQ registers are treated as a logical alias of the global VCMDQ registers and share the same decoding logic. Writes are backed by cached register state only; no hardware queue mapping is performed yet. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 84 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 4d447718d0..71f9a43bce 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -170,6 +170,71 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwad= dr offset, unsigned size) } } =20 +/* + * Write a VCMDQ register using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + */ +static void +tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, + uint64_t value, unsigned size) +{ + + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + cmdqv->vcmdq_cons_indx[index] =3D value; + return; + case A_VCMDQ0_PROD_INDX: + cmdqv->vcmdq_prod_indx[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_CONFIG: + if (value & R_VCMDQ0_CONFIG_CMDQ_EN_MASK) { + cmdqv->vcmdq_status[index] |=3D R_VCMDQ0_STATUS_CMDQ_EN_OK_MAS= K; + } else { + cmdqv->vcmdq_status[index] &=3D ~R_VCMDQ0_STATUS_CMDQ_EN_OK_MA= SK; + } + cmdqv->vcmdq_config[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_GERRORN: + cmdqv->vcmdq_gerrorn[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_BASE_L: + if (size =3D=3D 8) { + cmdqv->vcmdq_base[index] =3D value; + } else if (size =3D=3D 4) { + cmdqv->vcmdq_base[index] =3D + (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) | + (value & 0xffffffffULL); + } + return; + case A_VCMDQ0_BASE_H: + cmdqv->vcmdq_base[index] =3D + (cmdqv->vcmdq_base[index] & 0xffffffffULL) | + ((uint64_t)value << 32); + return; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + if (size =3D=3D 8) { + cmdqv->vcmdq_cons_indx_base[index] =3D value; + } else if (size =3D=3D 4) { + cmdqv->vcmdq_cons_indx_base[index] =3D + (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffff00000000UL= L) | + (value & 0xffffffffULL); + } + return; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + cmdqv->vcmdq_cons_indx_base[index] =3D + (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffffULL) | + ((uint64_t)value << 32); + return; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled write access at 0x%" PRIx64 "\n", + __func__, offset0); + return; + } +} + static void tegra241_cmdqv_write_vintf(Tegra241CMDQV *cmdqv, hwaddr offset, uint64_t value) { @@ -197,6 +262,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; Error *local_err =3D NULL; + int index; =20 if (!cmdqv->vintf_page0) { if (!tegra241_cmdqv_mmap_vintf_page0(cmdqv, &local_err)) { @@ -230,6 +296,24 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr = offset, uint64_t value, case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: tegra241_cmdqv_write_vintf(cmdqv, offset, value); break; + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ127_GERRORN: + /* Same decoding as read() case: See comments above */ + offset -=3D 0x20000; + QEMU_FALLTHROUGH; + case A_VCMDQ0_CONS_INDX ... A_VCMDQ127_GERRORN: + index =3D (offset - 0x10000) / 0x80; + tegra241_cmdqv_write_vcmdq(cmdqv, offset - 0x80 * index, index, va= lue, + size); + break; + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ127_CONS_INDX_BASE_DRAM_H: + /* Same decoding as read() case: See comments above */ + offset -=3D 0x20000; + QEMU_FALLTHROUGH; + case A_VCMDQ0_BASE_L ... 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charset="utf-8" Introduce address_space_is_ram(), a helper to determine whether a guest physical address resolves to a RAM-backed MemoryRegion within an AddressSpace. Signed-off-by: Shameer Kolothum --- include/system/memory.h | 10 ++++++++++ system/physmem.c | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/system/memory.h b/include/system/memory.h index 0562af3136..02b2e83fd7 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -2900,6 +2900,16 @@ bool address_space_access_valid(AddressSpace *as, hw= addr addr, hwaddr len, */ bool address_space_is_io(AddressSpace *as, hwaddr addr); =20 +/** + * address_space_is_ram: check whether a guest physical address whithin + * an address space is RAM. + * + * @as: #AddressSpace to be accessed + * @addr: address within that address space + */ + +bool address_space_is_ram(AddressSpace *as, hwaddr addr); + /* address_space_map: map a physical memory region into a host virtual add= ress * * May map a subset of the requested range, given by and returned in @plen. diff --git a/system/physmem.c b/system/physmem.c index 2fb0c25c93..ddcf921311 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3646,6 +3646,17 @@ bool address_space_is_io(AddressSpace *as, hwaddr ad= dr) return !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); } =20 +bool address_space_is_ram(AddressSpace *as, hwaddr addr) +{ + MemoryRegion *mr; + + RCU_READ_LOCK_GUARD(); + mr =3D address_space_translate(as, addr, &addr, NULL, false, + MEMTXATTRS_UNSPECIFIED); + + return memory_region_is_ram(mr); +} + static hwaddr flatview_extend_translation(FlatView *fv, hwaddr addr, hwaddr target_len, --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1770389513; cv=pass; d=zohomail.com; s=zohoarc; b=GHLuEQ/HWnTW0qAbVQc/44WcoAPCYRAyMOSM8/XF+YLm6obGUbpPt152ecMJmDMEjrXE3WFwEtRS6+JUef589SKpGzd3850aPRsCsdHhGbNwXLFKhlWeMV8Ee0Pv1VpfYY0HoBSI2KvMV/i3V7x1OQEVkf8Q5lCpxAtPolFvgpc= ARC-Message-Signature: i=2; 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charset="utf-8" From: Nicolin Chen Add support for allocating IOMMUFD hardware queues when VCMDQ base registers are programmed by the guest. When a VCMDQ BASE register is written with a valid RAM-backed address, allocate a corresponding IOMMUFD hardware queue for the CMDQV device. Any previously allocated queue for the VCMDQ is freed before reallocation. Writes with invalid addresses (e.g. during reset) are ignored. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 51 ++++++++++++++++++++++++++++++++++++++--- hw/arm/tegra241-cmdqv.h | 1 + 2 files changed, 49 insertions(+), 3 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 71f9a43bce..57f47a4997 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -170,6 +170,45 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwad= dr offset, unsigned size) } } =20 +static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index, + Error **errp) +{ + SMMUv3AccelState *accel =3D cmdqv->s_accel; + uint64_t base_mask =3D (uint64_t)R_VCMDQ0_BASE_L_ADDR_MASK | + (uint64_t)R_VCMDQ0_BASE_H_ADDR_MASK << 32; + uint64_t addr =3D cmdqv->vcmdq_base[index] & base_mask; + uint64_t log2 =3D cmdqv->vcmdq_base[index] & R_VCMDQ0_BASE_L_LOG2SIZE_= MASK; + uint64_t size =3D 1ULL << (log2 + 4); + IOMMUFDHWqueue *vcmdq =3D cmdqv->vcmdq[index]; + IOMMUFDViommu *viommu =3D accel->viommu; + IOMMUFDHWqueue *hw_queue; + uint32_t hw_queue_id; + + /* Ignore any invalid address. This may come as part of reset etc */ + if (!address_space_is_ram(&address_space_memory, addr)) { + return true; + } + + if (vcmdq) { + iommufd_backend_free_id(viommu->iommufd, vcmdq->hw_queue_id); + cmdqv->vcmdq[index] =3D NULL; + g_free(vcmdq); + } + + if (!iommufd_backend_alloc_hw_queue(viommu->iommufd, viommu->viommu_id, + IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV, + index, addr, size, &hw_queue_id, + errp)) { + return false; + } + hw_queue =3D g_new(IOMMUFDHWqueue, 1); + hw_queue->hw_queue_id =3D hw_queue_id; + hw_queue->viommu =3D viommu; + cmdqv->vcmdq[index] =3D hw_queue; + + return true; +} + /* * Write a VCMDQ register using VCMDQ0_* offsets. * @@ -178,7 +217,7 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwadd= r offset, unsigned size) */ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, - uint64_t value, unsigned size) + uint64_t value, unsigned size, Error **errp) { =20 switch (offset0) { @@ -207,11 +246,13 @@ tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwad= dr offset0, int index, (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) | (value & 0xffffffffULL); } + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); return; case A_VCMDQ0_BASE_H: cmdqv->vcmdq_base[index] =3D (cmdqv->vcmdq_base[index] & 0xffffffffULL) | ((uint64_t)value << 32); + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); return; case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: if (size =3D=3D 8) { @@ -303,7 +344,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, case A_VCMDQ0_CONS_INDX ... A_VCMDQ127_GERRORN: index =3D (offset - 0x10000) / 0x80; tegra241_cmdqv_write_vcmdq(cmdqv, offset - 0x80 * index, index, va= lue, - size); + size, &local_err); break; case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ127_CONS_INDX_BASE_DRAM_H: /* Same decoding as read() case: See comments above */ @@ -312,12 +353,16 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr= offset, uint64_t value, case A_VCMDQ0_BASE_L ... A_VCMDQ127_CONS_INDX_BASE_DRAM_H: index =3D (offset - 0x20000) / 0x80; tegra241_cmdqv_write_vcmdq(cmdqv, offset - 0x80 * index, index, va= lue, - size); + size, &local_err); break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", __func__, offset); } + + if (local_err) { + error_report_err(local_err); + } } =20 static void tegra241_cmdqv_free_veventq(SMMUv3State *s) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 1bc03c4f97..2f4a8ab35f 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -31,6 +31,7 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; void *vintf_page0; + IOMMUFDHWqueue *vcmdq[128]; =20 /* Register Cache */ uint32_t config; --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Nicolin Chen VINTF page0 is guest accessible and backed by host memory, so it can be mapped directly instead of being trapped and emulated. Map the VINTF0 page0 MMIO region lazily on first vCMDQ setup. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 21 +++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 2 ++ 2 files changed, 23 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 57f47a4997..153fd70edb 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -170,6 +170,26 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwad= dr offset, unsigned size) } } =20 +static void tegra241_cmdqv_map_vintf_page0(Tegra241CMDQV *cmdqv) +{ + char *name; + + if (cmdqv->vintf_page0_mapped) { + return; + } + + name =3D g_strdup_printf("%s vintf-page0", + memory_region_name(&cmdqv->mmio_cmdqv)); + memory_region_init_ram_device_ptr(&cmdqv->mmio_vintf_page0, + memory_region_owner(&cmdqv->mmio_cmd= qv), + name, VINTF_REG_PAGE_SIZE, + cmdqv->vintf_page0); + memory_region_add_subregion_overlap(&cmdqv->mmio_cmdqv, 0x30000, + &cmdqv->mmio_vintf_page0, 1); + g_free(name); + cmdqv->vintf_page0_mapped =3D true; +} + static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index, Error **errp) { @@ -206,6 +226,7 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *c= mdqv, int index, hw_queue->viommu =3D viommu; cmdqv->vcmdq[index] =3D hw_queue; =20 + tegra241_cmdqv_map_vintf_page0(cmdqv); return true; } =20 diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 2f4a8ab35f..b92c34e1d7 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -31,6 +31,8 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; void *vintf_page0; + MemoryRegion mmio_vintf_page0; + bool vintf_page0_mapped; IOMMUFDHWqueue *vcmdq[128]; =20 /* Register Cache */ --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1770389816; cv=pass; d=zohomail.com; s=zohoarc; b=Z4LOb64t3oHCztQ4iLeTtoaMZFPKGjQOZ+qvNJBg3a//dwSMyx93owskTdbfUprHWpP/7jFIeZLOPzzazW/9jX/cqciXHpyseFuUkD4DzsxiZ0nz4mQE9MfPwQloKRcOMsn3b+UTovw4QDr7NrLDDk/ezwfnJMce8tNGKIbOPok= ARC-Message-Signature: i=2; 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charset="utf-8" When a VCMDQ is mapped and VINTF page0 is available, read and write VCMDQ registers directly via the VINTF page0 backing instead of using cached register values. Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 44 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 153fd70edb..c7e70d8e1d 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -38,12 +38,32 @@ static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMD= QV *cmdqv, Error **errp) * * The caller normalizes the MMIO offset such that @offset0 always refers * to a VCMDQ0_* register, while @index selects the VCMDQ instance. - * - * All VCMDQ accesses are currently trapped. Use cached registers */ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr off= set0, int index) { + + /* + * If this VCMDQ is mapped and VINTF page0 is available, read directly + * from the VINTF page0 backing. Otherwise, fall back to cached state. + */ + if (cmdqv->vcmdq[index] && cmdqv->vintf_page0_mapped) { + uint64_t off =3D (index * 0x80) + (offset0 - 0x10000); + uint32_t *ptr =3D (uint32_t *)(cmdqv->vintf_page0 + off); + + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + case A_VCMDQ0_PROD_INDX: + case A_VCMDQ0_CONFIG: + case A_VCMDQ0_STATUS: + case A_VCMDQ0_GERROR: + case A_VCMDQ0_GERRORN: + return *ptr; + default: + break; + } + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: return cmdqv->vcmdq_cons_indx[index]; @@ -241,6 +261,26 @@ tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwadd= r offset0, int index, uint64_t value, unsigned size, Error **errp) { =20 + /* + * If this VCMDQ is mapped and VINTF page0 is available, write directly + * to the VINTF page0 backing. Otherwise, update cached state. + */ + if (cmdqv->vcmdq[index] && cmdqv->vintf_page0_mapped) { + uint64_t off =3D (index * 0x80) + (offset0 - 0x10000); + uint32_t *ptr =3D (uint32_t *)(cmdqv->vintf_page0 + off); + + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + case A_VCMDQ0_PROD_INDX: + case A_VCMDQ0_CONFIG: + case A_VCMDQ0_GERRORN: + *ptr =3D (uint32_t)value; + return; + default: + break; + } + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: cmdqv->vcmdq_cons_indx[index] =3D value; --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1770389817; cv=pass; d=zohomail.com; s=zohoarc; b=nY0l1U2LjRRjvY9OCNRahIVPpgOfJ/xlwcJhOF4+/QsQqYTLfiCN1tQe/pj8UuJatvqrv1Eb6W1n+dxzBXJdfvEhmeVbjd6tfOftEH4FbTfxKxBTQ23V69/sZ9FFKQR8OVmRw3wv+z1zzKNlHzlkRsPS9/4hDMAbjRjXzV5V9e4= ARC-Message-Signature: i=2; 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charset="utf-8" Allocate a CMDQV specific vEVENTQ via IOMMUFD, and add the corresponding teardown path to free the vEVENTQ during cleanup. Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 39 +++++++++++++++++++++++++++++++++++++-- hw/arm/tegra241-cmdqv.h | 1 + 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index c7e70d8e1d..9e0e07e85e 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -428,12 +428,47 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr= offset, uint64_t value, =20 static void tegra241_cmdqv_free_veventq(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + + if (!veventq) { + return; + } + close(veventq->veventq_fd); + iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id); + g_free(veventq); + cmdqv->veventq =3D NULL; } =20 static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + SMMUv3AccelState *accel =3D s->s_accel; + IOMMUFDViommu *viommu =3D accel->viommu; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + IOMMUFDVeventq *veventq; + uint32_t veventq_id; + uint32_t veventq_fd; + + if (cmdqv->veventq) { + return true; + } + + if (!iommufd_backend_alloc_veventq(viommu->iommufd, viommu->viommu_id, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + 1 << 16, &veventq_id, &veventq_fd, + errp)) { + error_append_hint(errp, "Tegra241 CMDQV: failed to alloc veventq"); + return false; + } + + veventq =3D g_new(IOMMUFDVeventq, 1); + veventq->veventq_id =3D veventq_id; + veventq->veventq_fd =3D veventq_fd; + veventq->viommu =3D viommu; + cmdqv->veventq =3D veventq; + + return true; } =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index b92c34e1d7..a3a1621e3a 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -34,6 +34,7 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_vintf_page0; bool vintf_page0_mapped; IOMMUFDHWqueue *vcmdq[128]; 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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE33.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4083 Received-SPF: permerror client-ip=2a01:111:f403:c105::5; envelope-from=skolothumtho@nvidia.com; helo=CH5PR02CU005.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1770389675001154100 Install an event handler on the CMDQV vEVENTQ fd to read and propagate host received CMDQV errors to the guest. The handler runs in QEMU=E2=80=99s main loop, using a non-blocking fd regis= tered via qemu_set_fd_handler(). Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 83 +++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 2 + hw/arm/trace-events | 3 ++ 3 files changed, 88 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 9e0e07e85e..3dc5315677 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -8,12 +8,76 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/log.h" +#include "trace.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/core/irq.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +static void tegra241_cmdqv_event_read(void *opaque) +{ + Tegra241CMDQV *cmdqv =3D opaque; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_tegra241_cmdqv vevent; + } buf; + uint32_t last_seq =3D cmdqv->last_event_seq; + ssize_t bytes; + + bytes =3D read(cmdqv->veventq->veventq_fd, &buf, sizeof(buf)); + if (bytes <=3D 0) { + if (errno =3D=3D EAGAIN || errno =3D=3D EINTR) { + return; + } + error_report_once("Tegra241 CMDQV: vEVENTQ: read failed (%m)"); + return; + } + + if (bytes =3D=3D sizeof(buf.hdr) && + (buf.hdr.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) { + error_report_once("Tegra241 CMDQV: vEVENTQ has lost events"); + return; + } + + if (bytes < sizeof(buf)) { + error_report_once("Tegra241 `CMDQV: vEVENTQ: incomplete read (%zd/= %zd bytes)", + bytes, sizeof(buf)); + cmdqv->event_start =3D false; + return; + } + + /* Check sequence in hdr for lost events if any */ + if (cmdqv->event_start && (buf.hdr.sequence - last_seq !=3D 1)) { + error_report_once("Tegra241 CMDQV: vEVENTQ: detected lost %u event= (s)", + buf.hdr.sequence - last_seq - 1); + } + + if (buf.vevent.lvcmdq_err_map[0] || buf.vevent.lvcmdq_err_map[1]) { + cmdqv->vintf_cmdq_err_map[0] =3D + buf.vevent.lvcmdq_err_map[0] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[1] =3D + (buf.vevent.lvcmdq_err_map[0] >> 32) & 0xffffffff; + cmdqv->vintf_cmdq_err_map[2] =3D + buf.vevent.lvcmdq_err_map[1] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[3] =3D + (buf.vevent.lvcmdq_err_map[1] >> 32) & 0xffffffff; + for (int i =3D 0; i < 4; i++) { + cmdqv->cmdq_err_map[i] =3D cmdqv->vintf_cmdq_err_map[i]; + } + cmdqv->vi_err_map[0] |=3D 0x1; + qemu_irq_pulse(cmdqv->irq); + trace_tegra241_cmdqv_err_map( + cmdqv->vintf_cmdq_err_map[3], cmdqv->vintf_cmdq_err_map[2], + cmdqv->vintf_cmdq_err_map[1], cmdqv->vintf_cmdq_err_map[0]); + } + + cmdqv->last_event_seq =3D buf.hdr.sequence; + cmdqv->event_start =3D true; +} + static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **= errp) { IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; @@ -435,6 +499,7 @@ static void tegra241_cmdqv_free_veventq(SMMUv3State *s) if (!veventq) { return; } + qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL); close(veventq->veventq_fd); iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id); g_free(veventq); @@ -449,6 +514,7 @@ static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s= , Error **errp) IOMMUFDVeventq *veventq; uint32_t veventq_id; uint32_t veventq_fd; + int flags; =20 if (cmdqv->veventq) { return true; @@ -462,13 +528,30 @@ static bool tegra241_cmdqv_alloc_veventq(SMMUv3State = *s, Error **errp) return false; } =20 + flags =3D fcntl(veventq_fd, F_GETFL); + if (flags < 0) { + error_setg(errp, "Failed to get flags for vEVENTQ fd"); + goto free_veventq; + } + if (fcntl(veventq_fd, F_SETFL, O_NONBLOCK | flags) < 0) { + error_setg(errp, "Failed to set O_NONBLOCK on vEVENTQ fd"); + goto free_veventq; + } + veventq =3D g_new(IOMMUFDVeventq, 1); veventq->veventq_id =3D veventq_id; veventq->veventq_fd =3D veventq_fd; veventq->viommu =3D viommu; cmdqv->veventq =3D veventq; =20 + /* Set up event handler for veventq fd */ + qemu_set_fd_handler(veventq_fd, tegra241_cmdqv_event_read, NULL, s); return true; + +free_veventq: + close(veventq_fd); + iommufd_backend_free_id(viommu->iommufd, veventq_id); + return false; } =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index a3a1621e3a..fddb3ac6e9 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -35,6 +35,8 @@ typedef struct Tegra241CMDQV { bool vintf_page0_mapped; IOMMUFDHWqueue *vcmdq[128]; IOMMUFDVeventq *veventq; + uint32_t last_event_seq; + bool event_start; =20 /* Register Cache */ uint32_t config; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 3457536fb0..76bda0efef 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -72,6 +72,9 @@ smmuv3_accel_unset_iommu_device(int devfn, uint32_t devid= ) "devfn=3D0x%x (idev dev smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1= , uint64_t ste_0) "vSID=3D0x%x hwpt_id=3D0x%x ste=3D%"PRIx64":%"PRIx64 smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_i= d) "vSID=3D0x%x ste type=3D%s hwpt_id=3D0x%x" =20 +# tegra241-cmdqv +tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen Introduce a reset handler for the Tegra241 CMDQV and initialize its register state. CMDQV gets initialized early during guest boot, hence the handler verifies that at least one cold-plugged device is attached to the associated vIOMMU before proceeding. This is required to retrieve host CMDQV info and to validate it against the QEMU implementation support. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 6 ++- hw/arm/tegra241-cmdqv.c | 107 ++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 6 +++ hw/arm/trace-events | 1 + 4 files changed, 119 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index b1a8ab79b5..96224a7632 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -707,7 +707,11 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, QLIST_REMOVE(accel_dev, next); trace_smmuv3_accel_unset_iommu_device(devfn, idev->devid); =20 - if (QLIST_EMPTY(&accel->device_list)) { + /* + * Keep the vIOMMU alive when CMDQV is present, as the vIOMMU to host + * SMMUv3 association cannot be changed via device hot-plug. + */ + if (QLIST_EMPTY(&accel->device_list) && !accel->cmdqv) { smmuv3_accel_free_viommu(accel); } } diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 3dc5315677..678e53d23e 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -582,8 +582,115 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMU= DeviceIOMMUFD *idev, return true; } =20 +static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) +{ + SMMUv3AccelState *s_accel =3D s->s_accel; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV; + struct iommu_hw_info_tegra241_cmdqv cmdqv_info; + SMMUv3AccelDevice *accel_dev; + Error *local_err =3D NULL; + uint64_t caps; + int i; + + if (QLIST_EMPTY(&s_accel->device_list)) { + error_report("tegra241-cmdqv=3Don: requires at least one cold-plug= ged " + "vfio-pci device"); + goto out_err; + } + + accel_dev =3D QLIST_FIRST(&s_accel->device_list); + if (!iommufd_backend_get_device_info(accel_dev->idev->iommufd, + accel_dev->idev->devid, + &data_type, &cmdqv_info, + sizeof(cmdqv_info), &caps, + NULL, &local_err)) { + error_append_hint(&local_err, "Failed to get Host CMDQV device inf= o"); + error_report_err(local_err); + goto out_err; + } + + if (data_type !=3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV) { + error_report("Wrong data type (%d) from Host CMDQV device info", + data_type); + goto out_err; + } + if (cmdqv_info.version !=3D TEGRA241_CMDQV_VERSION) { + error_report("Wrong version (%d) from Host CMDQV device info", + cmdqv_info.version); + goto out_err; + } + if (cmdqv_info.log2vcmdqs !=3D TEGRA241_CMDQV_NUM_CMDQ_LOG2) { + error_report("Wrong num of cmdqs (%d) from Host CMDQV device info", + cmdqv_info.version); + goto out_err; + } + if (cmdqv_info.log2vsids !=3D TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2) { + error_report("Wrong num of SID per VM (%d) from Host CMDQV device = info", + cmdqv_info.version); + goto out_err; + } + + cmdqv->config =3D V_CONFIG_RESET; + cmdqv->param =3D + FIELD_DP32(cmdqv->param, PARAM, CMDQV_VER, TEGRA241_CMDQV_VERSION); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_CMDQ_LOG2, + TEGRA241_CMDQV_NUM_CMDQ_LOG2); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_SID_PER_VM_= LOG2, + TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2); + trace_tegra241_cmdqv_init_regs(cmdqv->param); + cmdqv->status =3D R_STATUS_CMDQV_ENABLED_MASK; + for (i =3D 0; i < 2; i++) { + cmdqv->vi_err_map[i] =3D 0; + cmdqv->vi_int_mask[i] =3D 0; + cmdqv->cmdq_err_map[i] =3D 0; + } + cmdqv->vintf_config =3D 0; + cmdqv->vintf_status =3D 0; + for (i =3D 0; i < 4; i++) { + cmdqv->vintf_cmdq_err_map[i] =3D 0; + } + for (i =3D 0; i < 128; i++) { + cmdqv->cmdq_alloc_map[i] =3D 0; + cmdqv->vcmdq_cons_indx[i] =3D 0; + cmdqv->vcmdq_prod_indx[i] =3D 0; + cmdqv->vcmdq_config[i] =3D 0; + cmdqv->vcmdq_status[i] =3D 0; + cmdqv->vcmdq_gerror[i] =3D 0; + cmdqv->vcmdq_gerrorn[i] =3D 0; + cmdqv->vcmdq_base[i] =3D 0; + cmdqv->vcmdq_cons_indx_base[i] =3D 0; + } + return; + +out_err: + exit(1); +} + static void tegra241_cmdqv_reset(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + int i; + + if (!cmdqv) { + return; + } + + if (cmdqv->vintf_page0_mapped) { + memory_region_del_subregion(&cmdqv->mmio_cmdqv, + &cmdqv->mmio_vintf_page0); + cmdqv->vintf_page0_mapped =3D false; + } + + for (i =3D 127; i >=3D 0; i--) { + if (cmdqv->vcmdq[i]) { + iommufd_backend_free_id(accel->viommu->iommufd, + cmdqv->vcmdq[i]->hw_queue_id); + g_free(cmdqv->vcmdq[i]); + cmdqv->vcmdq[i] =3D NULL; + } + } + tegra241_cmdqv_init_regs(s, cmdqv); } =20 static const MemoryRegionOps mmio_cmdqv_ops =3D { diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index fddb3ac6e9..2aad697170 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -25,6 +25,10 @@ */ #define TEGRA241_CMDQV_IO_LEN 0x50000 =20 +#define TEGRA241_CMDQV_VERSION 0x1 +#define TEGRA241_CMDQV_NUM_CMDQ_LOG2 0x1 +#define TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2 0x4 + typedef struct Tegra241CMDQV { struct iommu_viommu_tegra241_cmdqv cmdqv_data; SMMUv3AccelState *s_accel; @@ -67,6 +71,8 @@ FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) FIELD(CONFIG, CONS_DRAM_EN, 20, 1) =20 +#define V_CONFIG_RESET 0x00020403 + REG32(PARAM, 0x4) FIELD(PARAM, CMDQV_VER, 0, 4) FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 76bda0efef..ef495c040c 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -74,6 +74,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS =20 # tegra241-cmdqv tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" +tegra241_cmdqv_init_regs(uint32_t param) "hw info received. param: 0x%04X" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , Subject: [PATCH v2 20/24] hw/arm/tegra241-cmdqv: Limit queue size based on backend page size Date: Fri, 6 Feb 2026 14:48:19 +0000 Message-ID: <20260206144823.80655-21-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206144823.80655-1-skolothumtho@nvidia.com> References: <20260206144823.80655-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|IA1PR12MB6601:EE_ X-MS-Office365-Filtering-Correlation-Id: 1579cfdb-c31d-4a06-fa7e-08de658f21da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6601 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=skolothumtho@nvidia.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1770389736986158500 From: Nicolin Chen CMDQV HW reads guest queue memory in its host physical address setup via IOMUUFD. This requires the guest queue memory isn't only contiguous in guest PA space but also in host PA space. With Tegra241 CMDQV enabled, we must only advertise a CMDQV size that the host can safely back with physically contiguous memory. Allowing a CMDQV larger than the host page size could cause the hardware to DMA across page boundaries leading to faults. Limit IDR1.CMDQS so the guest cannot configure a CMDQV that exceeds the host=E2=80=99s contiguous backing. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 678e53d23e..19fcc5b68d 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -11,10 +11,14 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "trace.h" +#include =20 #include "hw/arm/smmuv3.h" #include "hw/core/irq.h" #include "smmuv3-accel.h" +#include "smmuv3-internal.h" +#include "system/ramblock.h" +#include "system/ramlist.h" #include "tegra241-cmdqv.h" =20 static void tegra241_cmdqv_event_read(void *opaque) @@ -582,6 +586,33 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUD= eviceIOMMUFD *idev, return true; } =20 +static size_t tegra241_cmdqv_min_ram_pagesize(void) +{ + RAMBlock *rb; + size_t pg, min_pg =3D SIZE_MAX; + + RAMBLOCK_FOREACH(rb) { + MemoryRegion *mr =3D rb->mr; + + /* Only consider real RAM regions */ + if (!mr || !memory_region_is_ram(mr)) { + continue; + } + + /* Skip RAM regions that are not backed by a memory-backend */ + if (!object_dynamic_cast(mr->owner, TYPE_MEMORY_BACKEND)) { + continue; + } + + pg =3D qemu_ram_pagesize(rb); + if (pg && pg < min_pg) { + min_pg =3D pg; + } + } + + return (min_pg =3D=3D SIZE_MAX) ? qemu_real_host_page_size() : min_pg; +} + static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) { SMMUv3AccelState *s_accel =3D s->s_accel; @@ -589,7 +620,9 @@ static void tegra241_cmdqv_init_regs(SMMUv3State *s, Te= gra241CMDQV *cmdqv) struct iommu_hw_info_tegra241_cmdqv cmdqv_info; SMMUv3AccelDevice *accel_dev; Error *local_err =3D NULL; + size_t pgsize; uint64_t caps; + uint32_t val; int i; =20 if (QLIST_EMPTY(&s_accel->device_list)) { @@ -660,6 +693,16 @@ static void tegra241_cmdqv_init_regs(SMMUv3State *s, T= egra241CMDQV *cmdqv) cmdqv->vcmdq_base[i] =3D 0; cmdqv->vcmdq_cons_indx_base[i] =3D 0; } + + /* + * CMDQ must not cross a physical RAM backend page. Adjust CMDQS so the + * queue fits entirely within the smallest backend page size, ensuring + * the command queue is physically contiguous in host memory. + */ + pgsize =3D tegra241_cmdqv_min_ram_pagesize(); + val =3D FIELD_EX32(s->idr[1], IDR1, CMDQS); + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, MIN(log2(pgsize) - 4,= val)); + return; =20 out_err: --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1770389583; cv=pass; d=zohomail.com; s=zohoarc; b=hBxpogr6YQzsKMJANd+px9bnoLZbSosauhGYJeHRSLSt5u1K2ZfkYRXJ/1rOG3XhRNG1tSrBdgYwtgFexwJhXWRzLv8FJYecJHrOEM7YaaygaT5v6suDfwyhLrEhq9F6hdEgnHqRiomDSGpfQvDV0XpSqAIUUeuQCB/V3dH3UKk= ARC-Message-Signature: i=2; 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charset="utf-8" Rename struct AcpiIortSMMUv3Dev to AcpiSMMUv3Dev so that it is not specific to IORT. Subsequent Tegra241 CMDQV support patch will use the same struct to build CMDQV DSDT support as well. No functional changes intended. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 44 ++++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index c145678185..ae3b4aac52 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -339,24 +339,28 @@ static int iort_idmap_compare(gconstpointer a, gconst= pointer b) return idmap_a->input_base - idmap_b->input_base; } =20 -typedef struct AcpiIortSMMUv3Dev { +typedef struct AcpiSMMUv3Dev { int irq; hwaddr base; + + /* + * IORT-only fields. + * These are used when building IORT SMMUv3 nodes. + */ GArray *rc_smmu_idmaps; - /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ - size_t offset; + size_t offset; /* Offset of the SMMUv3 node within the IORT table */ bool accel; bool ats; -} AcpiIortSMMUv3Dev; +} AcpiSMMUv3Dev; =20 /* - * Populate the struct AcpiIortSMMUv3Dev for the legacy SMMUv3 and + * Populate the struct AcpiSMMUv3Dev for the legacy SMMUv3 and * return the total number of associated idmaps. */ static int populate_smmuv3_legacy_dev(GArray *sdev_blob) { VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); - AcpiIortSMMUv3Dev sdev =3D {0}; + AcpiSMMUv3Dev sdev =3D {0}; =20 sdev.rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); object_child_foreach_recursive(object_get_root(), iort_host_bridges, @@ -376,8 +380,8 @@ static int populate_smmuv3_legacy_dev(GArray *sdev_blob) =20 static int smmuv3_dev_idmap_compare(gconstpointer a, gconstpointer b) { - AcpiIortSMMUv3Dev *sdev_a =3D (AcpiIortSMMUv3Dev *)a; - AcpiIortSMMUv3Dev *sdev_b =3D (AcpiIortSMMUv3Dev *)b; + AcpiSMMUv3Dev *sdev_a =3D (AcpiSMMUv3Dev *)a; + AcpiSMMUv3Dev *sdev_b =3D (AcpiSMMUv3Dev *)b; AcpiIortIdMapping *map_a =3D &g_array_index(sdev_a->rc_smmu_idmaps, AcpiIortIdMapping, 0); AcpiIortIdMapping *map_b =3D &g_array_index(sdev_b->rc_smmu_idmaps, @@ -388,7 +392,7 @@ static int smmuv3_dev_idmap_compare(gconstpointer a, gc= onstpointer b) static int iort_smmuv3_devices(Object *obj, void *opaque) { VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); - AcpiIortSMMUv3Dev sdev =3D {0}; + AcpiSMMUv3Dev sdev =3D {0}; GArray *sdev_blob =3D opaque; AcpiIortIdMapping idmap; PlatformBusDevice *pbus; @@ -421,7 +425,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) } =20 /* - * Populate the struct AcpiIortSMMUv3Dev for all SMMUv3 devices and + * Populate the struct AcpiSMMUv3Dev for all SMMUv3 devices and * return the total number of idmaps. */ static int populate_smmuv3_dev(GArray *sdev_blob) @@ -442,10 +446,10 @@ static void create_rc_its_idmaps(GArray *its_idmaps, = GArray *smmuv3_devs) { AcpiIortIdMapping *idmap; AcpiIortIdMapping next_range =3D {0}; - AcpiIortSMMUv3Dev *sdev; + AcpiSMMUv3Dev *sdev; =20 for (int i =3D 0; i < smmuv3_devs->len; i++) { - sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + sdev =3D &g_array_index(smmuv3_devs, AcpiSMMUv3Dev, i); /* * Based on the RID ranges that are directed to the SMMU, determin= e the * bypassed RID ranges, i.e., the ones that are directed to the ITS @@ -479,7 +483,7 @@ static void create_rc_its_idmaps(GArray *its_idmaps, GA= rray *smmuv3_devs) static void build_iort_rmr_nodes(GArray *table_data, GArray *smmuv3_devices, uint32_t = *id) { - AcpiIortSMMUv3Dev *sdev; + AcpiSMMUv3Dev *sdev; AcpiIortIdMapping *idmap; int i; =20 @@ -487,7 +491,7 @@ build_iort_rmr_nodes(GArray *table_data, GArray *smmuv3= _devices, uint32_t *id) uint16_t rmr_len; int bdf; =20 - sdev =3D &g_array_index(smmuv3_devices, AcpiIortSMMUv3Dev, i); + sdev =3D &g_array_index(smmuv3_devices, AcpiSMMUv3Dev, i); if (!sdev->accel) { continue; } @@ -544,13 +548,13 @@ static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { int i, nb_nodes, rc_mapping_count; - AcpiIortSMMUv3Dev *sdev; + AcpiSMMUv3Dev *sdev; size_t node_size; bool ats_needed =3D false; int num_smmus =3D 0; uint32_t id =3D 0; int rc_smmu_idmaps_len =3D 0; - GArray *smmuv3_devs =3D g_array_new(false, true, sizeof(AcpiIortSMMUv3= Dev)); + GArray *smmuv3_devs =3D g_array_new(false, true, sizeof(AcpiSMMUv3Dev)= ); GArray *rc_its_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMa= pping)); =20 AcpiTable table =3D { .sig =3D "IORT", .rev =3D 5, .oem_id =3D vms->oe= m_id, @@ -581,7 +585,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } /* Calculate RMR nodes required. One per SMMUv3 with accelerated m= ode */ for (i =3D 0; i < num_smmus; i++) { - sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + sdev =3D &g_array_index(smmuv3_devs, AcpiSMMUv3Dev, i); if (sdev->ats) { ats_needed =3D true; } @@ -620,7 +624,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } =20 for (i =3D 0; i < num_smmus; i++) { - sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + sdev =3D &g_array_index(smmuv3_devs, AcpiSMMUv3Dev, i); int smmu_mapping_count, offset_to_id_array; int irq =3D sdev->irq; =20 @@ -699,7 +703,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) AcpiIortIdMapping *range; =20 for (i =3D 0; i < num_smmus; i++) { - sdev =3D &g_array_index(smmuv3_devs, AcpiIortSMMUv3Dev, i); + sdev =3D &g_array_index(smmuv3_devs, AcpiSMMUv3Dev, i); =20 /* * Map RIDs (input) from RC to SMMUv3 nodes: RC -> SMMUv3. @@ -742,7 +746,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) acpi_table_end(linker, &table); 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charset="utf-8" Add an "identifier" property to the SMMUv3 device and use it when building the ACPI IORT SMMUv3 node Identifier field. This avoids relying on enumeration order and provides a stable per-device identifier. This is useful when we add support for Tegra241 CMDQV DSDT in subsequent patch. No functional change intended. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3.c | 1 + hw/arm/virt-acpi-build.c | 4 +++- hw/arm/virt.c | 3 +++ include/hw/arm/smmuv3.h | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 7858bf2c33..7f84c87a46 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2114,6 +2114,7 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + DEFINE_PROP_UINT8("identifier", SMMUv3State, identifier, 0), DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index ae3b4aac52..046e930ca5 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -342,6 +342,7 @@ static int iort_idmap_compare(gconstpointer a, gconstpo= inter b) typedef struct AcpiSMMUv3Dev { int irq; hwaddr base; + uint8_t id; =20 /* * IORT-only fields. @@ -407,6 +408,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); + sdev.id =3D object_property_get_uint(obj, "identifier", &error_abort); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -642,7 +644,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count); build_append_int_noprefix(table_data, node_size, 2); /* Length */ build_append_int_noprefix(table_data, 4, 1); /* Revision */ - build_append_int_noprefix(table_data, id++, 4); /* Identifier */ + build_append_int_noprefix(table_data, sdev->id, 4); /* Identifier = */ /* Number of ID mappings */ build_append_int_noprefix(table_data, smmu_mapping_count, 4); /* Reference to ID Array */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 390845c503..22ee5c4a41 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3059,12 +3059,15 @@ static void virt_machine_device_pre_plug_cb(Hotplug= Handler *hotplug_dev, (vms->legacy_smmuv3_present) ? "iommu=3Dsmmuv3" : "virtio-iommu"); } else if (vms->iommu =3D=3D VIRT_IOMMU_NONE) { + static uint8_t id; + /* The new SMMUv3 device is specific to the PCI bus */ object_property_set_bool(OBJECT(dev), "smmu_per_bus", true, NU= LL); object_property_set_link(OBJECT(dev), "memory", OBJECT(vms->sysmem), NULL); object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(vms->secure_sysmem), NULL); + object_property_set_uint(OBJECT(dev), "identifier", id++, NULL= ); } if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { hwaddr db_start =3D 0; diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 87926f8cb3..39cb43506e 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -63,6 +63,7 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; char *stage; + uint8_t identifier; =20 /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; --=20 2.43.0 From nobody Sun Feb 8 16:53:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen Add ACPI DSDT support for Tegra241 CMDQV when the SMMUv3 instance is created with tegra241-cmdqv. The SMMUv3 device identifier is used as the ACPI _UID. This matches the Identifier field of the corresponding SMMUv3 IORT node, allowing the CMDQV DSDT device to be correctly associated with its SMMU. Because virt-acpi-build.c now includes CONFIG_DEVICES via the Tegra241 CMDQV header, the Meson file entry is updated to build it as part of arm_ss instead of arm_common_ss Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/meson.build | 2 +- hw/arm/trace-events | 1 + hw/arm/virt-acpi-build.c | 73 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+), 1 deletion(-) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 4ec91db50a..af0b516df1 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -1,7 +1,7 @@ arm_ss =3D ss.source_set() arm_common_ss =3D ss.source_set() arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) -arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) +arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) arm_common_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index ef495c040c..e7e3ccfe9f 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -9,6 +9,7 @@ omap1_lpg_led(const char *onoff) "omap1 LPG: LED is %s" =20 # virt-acpi-build.c virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." +virt_acpi_dsdt_tegra241_cmdqv(int smmu_id, uint64_t base, uint32_t irq) "D= SDT: add cmdqv node for (id=3D%d), base=3D0x%" PRIx64 ", irq=3D%d" =20 # smmu-common.c smmu_add_mr(const char *name) "%s" diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 046e930ca5..fe2925baaf 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -65,6 +65,8 @@ #include "target/arm/cpu.h" #include "target/arm/multiprocessing.h" =20 +#include "tegra241-cmdqv.h" + #define ARM_SPI_BASE 32 =20 #define ACPI_BUILD_TABLE_SIZE 0x20000 @@ -1121,6 +1123,75 @@ static void build_fadt_rev6(GArray *table_data, BIOS= Linker *linker, build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); } =20 +static int smmuv3_cmdqv_devices(Object *obj, void *opaque) +{ + VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); + GArray *sdev_blob =3D opaque; + PlatformBusDevice *pbus; + AcpiSMMUv3Dev sdev; + SysBusDevice *sbdev; + + if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) { + return 0; + } + + if (!object_property_get_bool(obj, "tegra241-cmdqv", NULL)) { + return 0; + } + + sdev.id =3D object_property_get_uint(obj, "identifier", &error_abort); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 1); + sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS); + sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + sdev.irq +=3D ARM_SPI_BASE; + g_array_append_val(sdev_blob, sdev); + return 0; +} + +static void acpi_dsdt_add_tegra241_cmdqv(Aml *scope, VirtMachineState *vms) +{ + GArray *smmuv3_devs =3D g_array_new(false, true, sizeof(AcpiSMMUv3Dev)= ); + int i; + + if (vms->legacy_smmuv3_present) { + return; + } + + object_child_foreach_recursive(object_get_root(), smmuv3_cmdqv_devices, + smmuv3_devs); + + for (i =3D 0; i < smmuv3_devs->len; i++) { + AcpiSMMUv3Dev *sdev; + Aml *dev, *crs, *addr; + + sdev =3D &g_array_index(smmuv3_devs, AcpiSMMUv3Dev, i); + + dev =3D aml_device("CV%.02u", sdev->id); + aml_append(dev, aml_name_decl("_HID", aml_string("NVDA200C"))); + aml_append(dev, aml_name_decl("_UID", aml_int(sdev->id))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + crs =3D aml_resource_template(); + addr =3D aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_F= IXED, + AML_CACHEABLE, AML_READ_WRITE, 0x0, sdev->= base, + sdev->base + TEGRA241_CMDQV_IO_LEN - 0x1, = 0x0, + TEGRA241_CMDQV_IO_LEN); + aml_append(crs, addr); + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_EDGE, + AML_ACTIVE_HIGH, AML_EXCLUSIVE, + (uint32_t *)&sdev->irq, 1)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + aml_append(scope, dev); + + trace_virt_acpi_dsdt_tegra241_cmdqv(sdev->id, sdev->base, sdev->ir= q); + } + g_array_free(smmuv3_devs, true); +} + /* DSDT */ static void build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) @@ -1185,6 +1256,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) acpi_dsdt_add_tpm(scope, vms); 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This is only enabled for accelerated SMMUv3 devices. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 7f84c87a46..84dc5351d1 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1956,6 +1956,12 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) } #endif =20 +#ifndef CONFIG_TEGRA241_CMDQV + if (s->tegra241_cmdqv) { + error_setg(errp, "tegra241_cmdqv=3Don support not compiled in"); + return false; + } +#endif if (!s->accel) { if (!s->ril) { error_setg(errp, "ril can only be disabled if accel=3Don"); @@ -1973,6 +1979,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ssidsize can only be set if accel=3Don"); return false; } + if (s->tegra241_cmdqv) { + error_setg(errp, "tegra241_cmdqv can only be enabled if accel= =3Don"); + return false; + } return true; } =20 @@ -2123,6 +2133,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), + DEFINE_PROP_BOOL("tegra241-cmdqv", SMMUv3State, tegra241_cmdqv, false), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2162,6 +2173,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Valid range is 0-20, where 0 disables SubstreamID support. " "Defaults to 0. A value greater than 0 is required to enable " "PASID support."); + object_class_property_set_description(klass, "tegra241-cmdqv", + "Enable/disable Tegra241 CMDQ-Virtualisation support (for accel=3D= on)"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, --=20 2.43.0