From: Arpit Kumar <arpit1.kumar@samsung.com>
Add a new cxl/cxl_ports.h header for field definitions related only to port
commands. Bring field naming up to date with spec as 'version' bitmasks
have been replaced with bitmasks of the specific features.
Fix a small issue where a reserved value for USP was set to 2 rather
than 0.
Signed-off-by: Arpit Kumar <arpit1.kumar@samsung.com>
Co-developed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
This is effectively lifted out of Arpit's orginal rework.
Arpit please confirm you are fine with keeping authorship on this one.
---
include/hw/cxl/cxl_port.h | 53 ++++++++++++++++++++++++++++++++++++++
hw/cxl/cxl-mailbox-utils.c | 31 ++++++++++++++--------
2 files changed, 73 insertions(+), 11 deletions(-)
diff --git a/include/hw/cxl/cxl_port.h b/include/hw/cxl/cxl_port.h
new file mode 100644
index 000000000000..04db60f7bc23
--- /dev/null
+++ b/include/hw/cxl/cxl_port.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef CXL_PORT_H
+#define CXL_PORT_H
+
+/* CXL r3.2 Table 7-19: Get Physical Port State Port Information Block Format */
+#define CXL_PORT_CONFIG_STATE_DISABLED 0x0
+#define CXL_PORT_CONFIG_STATE_BIND_IN_PROGRESS 0x1
+#define CXL_PORT_CONFIG_STATE_UNBIND_IN_PROGRESS 0x2
+#define CXL_PORT_CONFIG_STATE_DSP 0x3
+#define CXL_PORT_CONFIG_STATE_USP 0x4
+#define CXL_PORT_CONFIG_STATE_FABRIC_PORT 0x5
+#define CXL_PORT_CONFIG_STATE_INVALID_PORT_ID 0xF
+
+#define CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN 0x00
+#define CXL_PORT_CONNECTED_DEV_MODE_RCD 0x01
+#define CXL_PORT_CONNECTED_DEV_MODE_68B_VH 0x02
+#define CXL_PORT_CONNECTED_DEV_MODE_256B 0x03
+#define CXL_PORT_CONNECTED_DEV_MODE_LO_256B 0x04
+#define CXL_PORT_CONNECTED_DEV_MODE_PBR 0x05
+
+#define CXL_PORT_CONNECTED_DEV_TYPE_NONE 0x00
+#define CXL_PORT_CONNECTED_DEV_TYPE_PCIE 0x01
+#define CXL_PORT_CONNECTED_DEV_TYPE_1 0x02
+#define CXL_PORT_CONNECTED_DEV_TYPE_2_OR_HBR_SWITCH 0x03
+#define CXL_PORT_CONNECTED_DEV_TYPE_3_SLD 0x04
+#define CXL_PORT_CONNECTED_DEV_TYPE_3_MLD 0x05
+#define CXL_PORT_CONNECTED_DEV_PBR_COMPONENT 0x06
+
+#define CXL_PORT_SUPPORTS_RCD BIT(0)
+#define CXL_PORT_SUPPORTS_68B_VH BIT(1)
+#define CXL_PORT_SUPPORTS_256B BIT(2)
+#define CXL_PORT_SUPPORTS_LO_256B BIT(3)
+#define CXL_PORT_SUPPORTS_PBR BIT(4)
+
+#define CXL_PORT_LTSSM_DETECT 0x00
+#define CXL_PORT_LTSSM_POLLING 0x01
+#define CXL_PORT_LTSSM_CONFIGURATION 0x02
+#define CXL_PORT_LTSSM_RECOVERY 0x03
+#define CXL_PORT_LTSSM_L0 0x04
+#define CXL_PORT_LTSSM_L0S 0x05
+#define CXL_PORT_LTSSM_L1 0x06
+#define CXL_PORT_LTSSM_L2 0x07
+#define CXL_PORT_LTSSM_DISABLED 0x08
+#define CXL_PORT_LTSSM_LOOPBACK 0x09
+#define CXL_PORT_LTSSM_HOT_RESET 0x0A
+
+#define CXL_PORT_LINK_STATE_FLAG_LANE_REVERSED BIT(0)
+#define CXL_PORT_LINK_STATE_FLAG_PERST_ASSERTED BIT(1)
+#define CXL_PORT_LINK_STATE_FLAG_PRSNT BIT(2)
+#define CXL_PORT_LINK_STATE_FLAG_POWER_OFF BIT(3)
+
+#endif /* CXL_PORT_H */
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index 2f449980cdc0..1c8cbe0f682d 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -15,6 +15,7 @@
#include "hw/cxl/cxl.h"
#include "hw/cxl/cxl_events.h"
#include "hw/cxl/cxl_mailbox.h"
+#include "hw/cxl/cxl_port.h"
#include "hw/pci/pci.h"
#include "hw/pci-bridge/cxl_upstream_port.h"
#include "qemu/cutils.h"
@@ -565,16 +566,16 @@ static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd,
} QEMU_PACKED *in;
/*
- * CXL r3.1 Table 7-19: Get Physical Port State Port Information Block
+ * CXL r3.2 Table 7-19: Get Physical Port State Port Information Block
* Format
*/
struct cxl_fmapi_port_state_info_block {
uint8_t port_id;
uint8_t config_state;
- uint8_t connected_device_cxl_version;
+ uint8_t connected_device_mode;
uint8_t rsv1;
uint8_t connected_device_type;
- uint8_t port_cxl_version_bitmask;
+ uint8_t supported_cxl_mode_bitmask;
uint8_t max_link_width;
uint8_t negotiated_link_width;
uint8_t supported_link_speeds_vector;
@@ -623,21 +624,30 @@ static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd,
if (port_dev) { /* DSP */
PCIDevice *ds_dev = pci_bridge_get_sec_bus(PCI_BRIDGE(port_dev))
->devices[0];
- port->config_state = 3;
+ port->config_state = CXL_PORT_CONFIG_STATE_DSP;
if (ds_dev) {
if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) {
- port->connected_device_type = 5; /* Assume MLD for now */
+ /* Assume MLD for now */
+ port->connected_device_type =
+ CXL_PORT_CONNECTED_DEV_TYPE_3_MLD;
} else {
- port->connected_device_type = 1;
+ port->connected_device_type =
+ CXL_PORT_CONNECTED_DEV_TYPE_PCIE;
+ port->connected_device_mode =
+ CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN;
+
}
} else {
- port->connected_device_type = 0;
+ port->connected_device_type = CXL_PORT_CONNECTED_DEV_TYPE_NONE;
+ port->connected_device_mode =
+ CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN;
}
port->supported_ld_count = 3;
} else if (usp->port == in->ports[i]) { /* USP */
port_dev = PCI_DEVICE(usp);
- port->config_state = 4;
- port->connected_device_type = 0;
+ port->config_state = CXL_PORT_CONFIG_STATE_USP;
+ port->connected_device_type = 0; /* Reserved for USP */
+ port->connected_device_mode = 0; /* Reserved for USP */
} else {
return CXL_MBOX_INVALID_INPUT;
}
@@ -667,8 +677,7 @@ static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd,
port->ltssm_state = 0x7;
port->first_lane_num = 0;
port->link_state = 0;
- port->port_cxl_version_bitmask = 0x2;
- port->connected_device_cxl_version = 0x2;
+ port->supported_cxl_mode_bitmask = CXL_PORT_SUPPORTS_68B_VH;
}
pl_size = sizeof(*out) + sizeof(*out->ports) * in->num_ports;
--
2.51.0© 2016 - 2026 Red Hat, Inc.