From nobody Mon Feb 9 18:43:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770226405; cv=none; d=zohomail.com; s=zohoarc; b=TITaNBbLpaq0gEke5qV7SdSFtOFXjK5aA6YwEJGyK6f0VJQXq8uojYXzTfh03DY89IZfod6MPeEEUowmQK7zxjV22OcTIAFmx6wtbOMU+WO0BNfSnbWzQu2LxE0+mWAqD2sLVbGiDWrtgCbTFxWcf0X4JwplVqU/+hHaGbbxhKM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770226405; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=XdoEK8xZfC8fLTddYnPLKBxPIj3WpbgcrFk0vjF8Rkg=; b=i6cwzrKdQKgb8XM2JYBAd2uMyYrDdPlZ+tDLoW+fGiop110KPVEtS2p/W9s45Rr5wf/uqIhAnzjYhlfFlEcethAtp+9NB36PjaXFvcnkIYUG81+mWD43aUMEwcdQaf2m/RnwI5+jlkuT+KST+c90sCR2ESheI1sIe0NSfhsuOF4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770226405175625.7102017278; Wed, 4 Feb 2026 09:33:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vngkP-00070u-U0; Wed, 04 Feb 2026 12:33:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vngkO-00070l-JS for qemu-devel@nongnu.org; Wed, 04 Feb 2026 12:33:00 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vngkM-0005Ll-Ql for qemu-devel@nongnu.org; Wed, 04 Feb 2026 12:33:00 -0500 Received: from mail.maildlp.com (unknown [172.18.224.83]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4f5nTy6KBXzJ46FB; Thu, 5 Feb 2026 01:32:06 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id 3CE0D40569; Thu, 5 Feb 2026 01:32:56 +0800 (CST) Received: from SecurePC-101-06.huawei.com (10.122.19.247) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Feb 2026 17:32:55 +0000 To: Michael Tsirkin , , Arpit Kumar CC: , , Ravi Shankar , Marcel Apfelbaum , Michael Roth Subject: [PATCH qemu v5 1/3] hw/cxl: Physical Port Info FMAPI - update to current spec and add defines. Date: Wed, 4 Feb 2026 17:32:21 +0000 Message-ID: <20260204173223.44122-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204173223.44122-1-Jonathan.Cameron@huawei.com> References: <20260204173223.44122-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml500011.china.huawei.com (7.191.174.215) To dubpeml500005.china.huawei.com (7.214.145.207) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770226407944154100 Content-Type: text/plain; charset="utf-8" From: Arpit Kumar Add a new cxl/cxl_ports.h header for field definitions related only to port commands. Bring field naming up to date with spec as 'version' bitmasks have been replaced with bitmasks of the specific features. Fix a small issue where a reserved value for USP was set to 2 rather than 0. Signed-off-by: Arpit Kumar Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron --- This is effectively lifted out of Arpit's orginal rework. Arpit please confirm you are fine with keeping authorship on this one. --- include/hw/cxl/cxl_port.h | 53 ++++++++++++++++++++++++++++++++++++++ hw/cxl/cxl-mailbox-utils.c | 31 ++++++++++++++-------- 2 files changed, 73 insertions(+), 11 deletions(-) diff --git a/include/hw/cxl/cxl_port.h b/include/hw/cxl/cxl_port.h new file mode 100644 index 000000000000..04db60f7bc23 --- /dev/null +++ b/include/hw/cxl/cxl_port.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef CXL_PORT_H +#define CXL_PORT_H + +/* CXL r3.2 Table 7-19: Get Physical Port State Port Information Block For= mat */ +#define CXL_PORT_CONFIG_STATE_DISABLED 0x0 +#define CXL_PORT_CONFIG_STATE_BIND_IN_PROGRESS 0x1 +#define CXL_PORT_CONFIG_STATE_UNBIND_IN_PROGRESS 0x2 +#define CXL_PORT_CONFIG_STATE_DSP 0x3 +#define CXL_PORT_CONFIG_STATE_USP 0x4 +#define CXL_PORT_CONFIG_STATE_FABRIC_PORT 0x5 +#define CXL_PORT_CONFIG_STATE_INVALID_PORT_ID 0xF + +#define CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN 0x00 +#define CXL_PORT_CONNECTED_DEV_MODE_RCD 0x01 +#define CXL_PORT_CONNECTED_DEV_MODE_68B_VH 0x02 +#define CXL_PORT_CONNECTED_DEV_MODE_256B 0x03 +#define CXL_PORT_CONNECTED_DEV_MODE_LO_256B 0x04 +#define CXL_PORT_CONNECTED_DEV_MODE_PBR 0x05 + +#define CXL_PORT_CONNECTED_DEV_TYPE_NONE 0x00 +#define CXL_PORT_CONNECTED_DEV_TYPE_PCIE 0x01 +#define CXL_PORT_CONNECTED_DEV_TYPE_1 0x02 +#define CXL_PORT_CONNECTED_DEV_TYPE_2_OR_HBR_SWITCH 0x03 +#define CXL_PORT_CONNECTED_DEV_TYPE_3_SLD 0x04 +#define CXL_PORT_CONNECTED_DEV_TYPE_3_MLD 0x05 +#define CXL_PORT_CONNECTED_DEV_PBR_COMPONENT 0x06 + +#define CXL_PORT_SUPPORTS_RCD BIT(0) +#define CXL_PORT_SUPPORTS_68B_VH BIT(1) +#define CXL_PORT_SUPPORTS_256B BIT(2) +#define CXL_PORT_SUPPORTS_LO_256B BIT(3) +#define CXL_PORT_SUPPORTS_PBR BIT(4) + +#define CXL_PORT_LTSSM_DETECT 0x00 +#define CXL_PORT_LTSSM_POLLING 0x01 +#define CXL_PORT_LTSSM_CONFIGURATION 0x02 +#define CXL_PORT_LTSSM_RECOVERY 0x03 +#define CXL_PORT_LTSSM_L0 0x04 +#define CXL_PORT_LTSSM_L0S 0x05 +#define CXL_PORT_LTSSM_L1 0x06 +#define CXL_PORT_LTSSM_L2 0x07 +#define CXL_PORT_LTSSM_DISABLED 0x08 +#define CXL_PORT_LTSSM_LOOPBACK 0x09 +#define CXL_PORT_LTSSM_HOT_RESET 0x0A + +#define CXL_PORT_LINK_STATE_FLAG_LANE_REVERSED BIT(0) +#define CXL_PORT_LINK_STATE_FLAG_PERST_ASSERTED BIT(1) +#define CXL_PORT_LINK_STATE_FLAG_PRSNT BIT(2) +#define CXL_PORT_LINK_STATE_FLAG_POWER_OFF BIT(3) + +#endif /* CXL_PORT_H */ diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 2f449980cdc0..1c8cbe0f682d 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -15,6 +15,7 @@ #include "hw/cxl/cxl.h" #include "hw/cxl/cxl_events.h" #include "hw/cxl/cxl_mailbox.h" +#include "hw/cxl/cxl_port.h" #include "hw/pci/pci.h" #include "hw/pci-bridge/cxl_upstream_port.h" #include "qemu/cutils.h" @@ -565,16 +566,16 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, } QEMU_PACKED *in; =20 /* - * CXL r3.1 Table 7-19: Get Physical Port State Port Information Block + * CXL r3.2 Table 7-19: Get Physical Port State Port Information Block * Format */ struct cxl_fmapi_port_state_info_block { uint8_t port_id; uint8_t config_state; - uint8_t connected_device_cxl_version; + uint8_t connected_device_mode; uint8_t rsv1; uint8_t connected_device_type; - uint8_t port_cxl_version_bitmask; + uint8_t supported_cxl_mode_bitmask; uint8_t max_link_width; uint8_t negotiated_link_width; uint8_t supported_link_speeds_vector; @@ -623,21 +624,30 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, if (port_dev) { /* DSP */ PCIDevice *ds_dev =3D pci_bridge_get_sec_bus(PCI_BRIDGE(port_d= ev)) ->devices[0]; - port->config_state =3D 3; + port->config_state =3D CXL_PORT_CONFIG_STATE_DSP; if (ds_dev) { if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) { - port->connected_device_type =3D 5; /* Assume MLD for n= ow */ + /* Assume MLD for now */ + port->connected_device_type =3D + CXL_PORT_CONNECTED_DEV_TYPE_3_MLD; } else { - port->connected_device_type =3D 1; + port->connected_device_type =3D + CXL_PORT_CONNECTED_DEV_TYPE_PCIE; + port->connected_device_mode =3D + CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN; + } } else { - port->connected_device_type =3D 0; + port->connected_device_type =3D CXL_PORT_CONNECTED_DEV_TYP= E_NONE; + port->connected_device_mode =3D + CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN; } port->supported_ld_count =3D 3; } else if (usp->port =3D=3D in->ports[i]) { /* USP */ port_dev =3D PCI_DEVICE(usp); - port->config_state =3D 4; - port->connected_device_type =3D 0; + port->config_state =3D CXL_PORT_CONFIG_STATE_USP; + port->connected_device_type =3D 0; /* Reserved for USP */ + port->connected_device_mode =3D 0; /* Reserved for USP */ } else { return CXL_MBOX_INVALID_INPUT; } @@ -667,8 +677,7 @@ static CXLRetCode cmd_get_physical_port_state(const str= uct cxl_cmd *cmd, port->ltssm_state =3D 0x7; port->first_lane_num =3D 0; port->link_state =3D 0; - port->port_cxl_version_bitmask =3D 0x2; - port->connected_device_cxl_version =3D 0x2; + port->supported_cxl_mode_bitmask =3D CXL_PORT_SUPPORTS_68B_VH; } =20 pl_size =3D sizeof(*out) + sizeof(*out->ports) * in->num_ports; --=20 2.51.0