The following changes since commit b377abc220fc53e9cab2aac3c73fc20be6d85eea:

  Merge tag 'hw-misc-20260202' of https://github.com/philmd/qemu into staging (2026-02-03 07:52:04 +1000)

are available in the Git repository at:

  https://github.com/philmd/qemu.git tags/single-binary-20260203

for you to fetch changes up to a63b90ca6ce8d00dee5150b84bbc65428519ef2b:

  disas: Have disas_set_info() take a const CPUState (2026-02-03 14:57:34 +0100)

----------------------------------------------------------------
Various patches related to single binary effort:

- Endianness cleanups on various targets (PPC in particular)
- Few cleanups around target_ulong type on Alpha
- Have CPUClass::disas_set_info() take a const CPUState
----------------------------------------------------------------

Philippe Mathieu-Daudé (29):
  target/ppc: Inline cpu_ldl_data_ra() calls in ICBI helpers
  target/ppc: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers
  target/ppc: Inline cpu_ld/st_data_ra() calls in do_hash()
  target/ppc: Expect page translation hash addresses to be aligned
  target/ppc: Introduce ppc_data_endian_env() helper
  target/ppc: Introduce ppc_code_endian_dc() helper
  target/ppc: Inline need_byteswap() and replace translator_ldl_swap()
  target/ppc: Check endianness via env in ppc_disas_set_info()
  target/ppc: Introduce ppc_env_is_little_endian() helper
  target/ppc: Check endianness at runtime in ppc_data_endian_env()
  target/ppc: Inline cpu_ldl_code() call in ppc_ldl_code()
  target/riscv: Inline cpu_ld[lq]_code() calls
  target/riscv: Inline translator_ld[uw,l,q]() calls
  target/i386: Inline translator_ld[uw,l,q]() calls
  target/m68k: Inline translator_ld[uw,l,q]() calls
  target/alpha: Avoid target-specific migration headers in machine.c
  target/alpha: Build system units in common source set
  target/alpha: Replace target_ulong -> uint64_t in gdb_write_register()
  target/alpha: Do not use target_ulong for trap arguments
  target/alpha: Do not use target_ulong for page table entries / indexes
  target/alpha: Remove target_ulong uses in get_physical_address()
  target/alpha: Expand TCGv type for 64-bit target
  target/arm: Have arm_feature() take a const @env argument
  target/arm: Have cpu_isar_feature() use a const ARMCPU object
  target/arm: Have is_64() take a const @env argument
  target/arm: Have arm_sctlr_b() take a const @env argument
  disas/riscv: Make rv_decode::cfg const
  disas: Make disassemble_info::target_info field const
  disas: Have disas_set_info() take a const CPUState

Pierrick Bouvier (1):
  target-info: add target_base_ppc, target_ppc and target_ppc64

 disas/riscv.h                    |   2 +-
 include/disas/dis-asm.h          |   2 +-
 include/hw/core/cpu.h            |   2 +-
 include/qemu/target-info.h       |  21 +++
 target/arm/cpu-features.h        |   2 +-
 target/arm/cpu.h                 |   6 +-
 target/ppc/internal.h            |  17 +++
 disas/riscv.c                    |   5 +-
 target-info.c                    |  21 +++
 target/alpha/cpu.c               |   3 +-
 target/alpha/gdbstub.c           |   2 +-
 target/alpha/helper.c            |  17 +--
 target/alpha/machine.c           |   3 +-
 target/alpha/translate.c         | 228 ++++++++++++++++---------------
 target/arm/cpu.c                 |   6 +-
 target/avr/cpu.c                 |   2 +-
 target/hexagon/cpu.c             |   3 +-
 target/hppa/cpu.c                |   2 +-
 target/i386/cpu.c                |   6 +-
 target/loongarch/cpu.c           |   3 +-
 target/m68k/cpu.c                |   2 +-
 target/m68k/translate.c          |   6 +-
 target/microblaze/cpu.c          |   2 +-
 target/mips/cpu.c                |   7 +-
 target/openrisc/cpu.c            |   2 +-
 target/ppc/cpu_init.c            |  14 +-
 target/ppc/gdbstub.c             |   2 +-
 target/ppc/mem_helper.c          |  60 +++++---
 target/ppc/tcg-excp_helper.c     |  27 ++--
 target/ppc/translate.c           |  21 +--
 target/riscv/cpu.c               |   7 +-
 target/riscv/translate.c         |  18 ++-
 target/riscv/zce_helper.c        |   8 +-
 target/rx/cpu.c                  |   2 +-
 target/s390x/cpu.c               |   2 +-
 target/sh4/cpu.c                 |   3 +-
 target/sparc/cpu.c               |   3 +-
 target/xtensa/cpu.c              |   3 +-
 target/i386/tcg/decode-new.c.inc |   6 +-
 target/alpha/meson.build         |   2 +-
 40 files changed, 329 insertions(+), 221 deletions(-)

-- 
2.52.0

On 2/4/26 01:04, Philippe Mathieu-Daudé wrote:
> The following changes since commit b377abc220fc53e9cab2aac3c73fc20be6d85eea:
> 
>    Merge tag 'hw-misc-20260202' ofhttps://github.com/philmd/qemu into staging (2026-02-03 07:52:04 +1000)
> 
> are available in the Git repository at:
> 
>    https://github.com/philmd/qemu.git tags/single-binary-20260203
> 
> for you to fetch changes up to a63b90ca6ce8d00dee5150b84bbc65428519ef2b:
> 
>    disas: Have disas_set_info() take a const CPUState (2026-02-03 14:57:34 +0100)
> 
> ----------------------------------------------------------------
> Various patches related to single binary effort:
> 
> - Endianness cleanups on various targets (PPC in particular)
> - Few cleanups around target_ulong type on Alpha
> - HaveCPUClass::disas_set_info() take a const CPUState

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/11.0 as appropriate.

r~