These patches add support to TCG for a CPU with SME but not SVE.  We
originally prevented users from doing that in the run-up to a
release, in commit f7767ca30179 ("target/arm: Disable SME if SVE is
disabled") by forcing SME to off if SVE wasn't implemented.  This was
a simple way to avoid users hitting an assertion failure.

Doing something more than "basically no testing" led me to
realize that we needed also to fix a lot of places in
translate-sve.c that currently check the aa64_sve CPU feature
but which ought to be checking for "SVE || SME". I also spotted
a few more issues in the process of doing that work, some of
which are only relevant on an SME-only CPU and some of which
are bugs that show up even with an SVE+SME CPU. Those fixes are
at the front of the series and cc: to stable.

Changes since v2:
 * new patch 3 fixing a bug where we were checking arm_sve but
   should have been checking arm_sve2
 * new patch 4 fixing a bug where we forgot to allow RAX1 in
   streaming mode for SME2p1 and above
 * new patch 5 fixing a bug where "sme=on" accidentally downgrades an
   SME2 CPU to SME1
 * new patches 8 - 12 which correct various feature checks
   in translate-sve.c Patch 9 is big but somewhat mechanical
   (and IMHO best reviewed by checking the post-patch source file)
 * new patch 13 which corrects the existing "clear AA64ZFR0 if
   CPU doesn't have SVE" to only clear the SVE-specific fields;
   we clear the whole register only when we have neither SVE
   nor SME

Patches 1, 2, 6, 7, 14, 15 have been reviewed; patches 3, 4, 5, 8 - 13
need review.

thanks
-- PMM

Peter Maydell (15):
  target/arm: Account for SME in aarch64_sve_narrow_vq() assertion
  target/arm: Report correct vector width in gdbstub when SME present
  target/arm: Fix feature check in DO_SVE2_RRX, DO_SVE2_RRX_TB
  target/arm/tcg: Allow SVE RAX1 in SME2p1 streaming mode
  target/arm: Don't let 'sme=on' downgrade SME
  target/arm: Handle SME-only CPUs in sve_vqm1_for_el_sm()
  target/arm: Handle SME-without-SVE on change of EL
  target/arm: Add aa64_sme_or_sve, aa64_sme_or_sve2 features
  target/arm/tcg: Drop unnecessary aa64_sve check from do_trans_pmull()
  target/arm/tcg: Use "or SME" feature checks where needed
  target/arm/tcg: Correct SVE/SME I8MM checks
  target/arm/tcg: Correct SVE/SME BF16 checks
  target/arm: Don't squash all ID_AA64ZFR0_EL1 fields for non-SVE
  target/arm: Squash FEAT_SME_FA64 if FEAT_SVE is not present
  target/arm: Permit configurations with SME but not SVE

 docs/system/arm/cpu-features.rst |  20 +-
 target/arm/cpu-features.h        |  27 +-
 target/arm/cpu.c                 |  10 -
 target/arm/cpu64.c               |  36 +-
 target/arm/gdbstub64.c           |  12 +-
 target/arm/helper.c              |  14 +-
 target/arm/internals.h           |   9 +
 target/arm/tcg/translate-sve.c   | 891 ++++++++++++++++---------------
 8 files changed, 551 insertions(+), 468 deletions(-)

-- 
2.43.0