From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039350; cv=none; d=zohomail.com; s=zohoarc; b=a5wCcum+SBWdyOPcjrSw4/Bvw/+vSjrWreCiyfdyUpyznx/zzCOzuSC/FtTjQiA0rF4YTclW28N5o/Gpu4hYT5qPuozLR9UOlSi/8DXqtcFJKHhQayTl5V4mbKFQdwEctXoPx3Y8LOwxyZ9zrE9rQSPKH3QXzcfRjmNP+ldBYXc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039350; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yDml/3LbO2JMFRFM4BlBDbVveOOqyhxoiv/BC5ZJtJI=; b=CDlKpAE4HNEkIvipX4QT5WRaeeldP12YZgEzgFckpzMUTDDygCdwT8GhY5Kgn46iDusRegNgazaBI3xAT3O5h19vLOWB0icTPkHt3yXAxa1vaQvSZCRgx4Z5BJ8BnBM4jHPX+HOGgvBSocaIoZ29m3xSgWkV8Q81y8PJjD3MpLw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039350033145.23105119644345; Mon, 2 Feb 2026 05:35:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu41-0006jo-2r; Mon, 02 Feb 2026 08:34:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu3z-0006ir-UE for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:33:59 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu3x-0002Z6-R0 for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:33:59 -0500 Received: by mail-wm1-x343.google.com with SMTP id 5b1f17b1804b1-4806dffc64cso33790445e9.1 for ; Mon, 02 Feb 2026 05:33:57 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c42895sm478054495e9.14.2026.02.02.05.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 05:33:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770039236; x=1770644036; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yDml/3LbO2JMFRFM4BlBDbVveOOqyhxoiv/BC5ZJtJI=; b=VvQ8spOkgdkAWL1+wkthNpGG+T40UkCnLlLLooqC9eYk9Se7KQs4YlpJZshnrDIoQW 8EWG49TnDb9JZo7xU6RTpMN5FZQ0M3Vtwbd0e7HFB+deuzTmFnXQi1DdMj8aMMFKiLOG NYyQOs8SUqZAL6H4s8+AsdDkXVlkzfGZhSUX+OL9STZz3A2E4lVSGDA4PzSz4FsWMzu4 Jn7j+9chMljljyF/XHaLZH3qlw9vUskHd5LjbyekcGOXuX6ixnBjZilQ198EyxmuTw/V Cd/xhV1fyGaUVJPsrAI8YaWgBwfW5hgrxVsdJu/yXZRX5nY/mGY58x3dBmnk50PakQmv 1lTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770039236; x=1770644036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=yDml/3LbO2JMFRFM4BlBDbVveOOqyhxoiv/BC5ZJtJI=; b=UtvQaLPytoQJ7xMdhAE7A1B8lZJZIgmlz1mjPrO0NSqqEKlRvg2lXA3aqdMZxZejvk ycyJHMtp20+dOo7EeZU9cdP64QpLdMEjoMl1Z0YbDK8J5IiV3cI+qepWuTcMEoFhPltA g44BExscFnT0VV0Y4Ehwm3dV2p39EnOOIoQ3EyVsaNoxD0Km3Z1UmC1YUAMrMUG0nAk7 tOpa1Xj6+TzoZUDOp2RUI5vaJI4C+CpxEJPNKFFPMFflYCufRz9j2XV6r6dNFP96mXDG 0Ahdj/3RyFx1KKsmbEViX5AeI7Lyo9r7cR8Fb6SuN+7ZonAVG6gRsagtcGaSXsNG77dB 4bzw== X-Forwarded-Encrypted: i=1; AJvYcCWSXd1mQwtU7A7+516ZKxOYWLgjU/UXD/Fuc9GFfS7tV7+mM655iRrE9GvCBKBrgNuYgOIASkP1BWBX@nongnu.org X-Gm-Message-State: AOJu0Yzsm8LabWNIR614N4SJoYgTD4FTswGQkm7zrAaZXEJVKA+FsFEJ fWmY7Mj4BgpxOjBE3AI/CxKOOvC9oB+93uaOIJ4gaeCl1TeZvQA9pa4Ek1iM+qv2L0U= X-Gm-Gg: AZuq6aJ9HVqKA0EJTe7Et43S1LitUk20ZSdbSbKzLlo9hEoR9xMbc1kJx6or2gy1yRH UYrJ3s89fg5zZgw3SnRxzG+ygfkyDiSpofXCXaUZSGXFIVsnc85NkZ7OzfefK0vpKcAe8dH9jBy MUVcuGzCQA1h48sB3n1mxEfqId9IMgrNct4EImY71q+gRskxVl+4fKy9aXRwypgtXBojo4FsfRs n03d59GXwCdnbZTePrqvByZ1zJ8LSGnQdBpOcFoAWSmJgE1/kIOja8WgTGOK+EimxaQUEz5raIw o7x75q2qCyXyrdLl4Z/H/WUoFyTiTHMh3qKcCOb1UHCy7BGhMi2EYqB1cHEvykaYIB0x5EccI/D Q/+7PIsMZy3jL4uFjNEJmtCHO+H7H8QN5TDy+Dp2JPcP0wV3r9MzHcC0Kqn8ciRhLhAA4y1v/jB /8fAJby4l7ycssb4mNK/v6/a/o+RfPz4cbTaq/IETP X-Received: by 2002:a05:600c:b99:b0:480:1e40:3d2 with SMTP id 5b1f17b1804b1-482db49a4a6mr164780935e9.29.1770039236266; Mon, 02 Feb 2026 05:33:56 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , Manos Pitsidianakis , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v3 01/15] target/arm: Account for SME in aarch64_sve_narrow_vq() assertion Date: Mon, 2 Feb 2026 13:33:39 +0000 Message-ID: <20260202133353.2231685-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260202133353.2231685-1-peter.maydell@linaro.org> References: <20260202133353.2231685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770039352417158500 In aarch64_sve_narrow_vq() we assert that the new VQ is within the maximum supported range for the CPU. We forgot to update this to account for SME, which might have a different maximum. Update the assert to permit any VQ which is valid for either SVE or SME. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- CC stable on this one, because it might also be a problem for a CPU with both SME and SVE but where the SVE max VL is less than the SME max VL. --- target/arm/helper.c | 2 +- target/arm/internals.h | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e86ceb130c..e7aa5ec2f2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10079,7 +10079,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsign= ed vq) uint64_t pmask; =20 assert(vq >=3D 1 && vq <=3D ARM_MAX_VQ); - assert(vq <=3D env_archcpu(env)->sve_max_vq); + assert(vq <=3D arm_max_vq(env_archcpu(env))); =20 /* Zap the high bits of the zregs. */ for (i =3D 0; i < 32; i++) { diff --git a/target/arm/internals.h b/target/arm/internals.h index f7b641342a..8ec2750847 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1808,6 +1808,15 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState = *env) ((1 << (1 - 1)) | (1 << (2 - 1)) | \ (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) =20 +/* + * Return the maximum SVE/SME VQ for this CPU. This defines + * the maximum possible size of the Zn vector registers. + */ +static inline int arm_max_vq(ARMCPU *cpu) +{ + return MAX(cpu->sve_max_vq, cpu->sme_max_vq); +} + /* * Return true if it is possible to take a fine-grained-trap to EL2. */ --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039524; cv=none; d=zohomail.com; s=zohoarc; b=cLlRXnOZK0SJWdoDH5cUFurF+SFXhdE/9dK5MwONFGNUmQ6XMYY+LPz/C8rp31O+Dx3ZXpygziYBUGBy/xODY4u51kAcxTeTO3HwWnIEpgPmvriIUmYJy8JEuSeRHIWebgBFYrROfbw4i6R9jYNKhGKaNARqWMrChDNk7+SWt9M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039524; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZSrmdhiUgq2SNEfimuA2mrbtB8VoeGQdLMz68iV2+VQ=; b=ZFO5hik+poNcnOOI9JJBSzeJGpLtGiPc2Gx+OLgx7KkQXTufXr/5FOTA7118sVweMDWsni1r/tGnPluc8jjHEA5wvr103GlXoq1NAOT5qEtk55o1UGYWeMnPE7KxWkMptzvB+Ak6Njlfryhnsme3PY0dI/O+N2wLgSBlujNqw1c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039524792620.8596281093273; Mon, 2 Feb 2026 05:38:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu42-0006kt-DX; Mon, 02 Feb 2026 08:34:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu40-0006jg-RY for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:00 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu3y-0002ZL-Vk for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:00 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4806f3fc50bso45950815e9.0 for ; Mon, 02 Feb 2026 05:33:58 -0800 (PST) Received: from lanath.. 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We always report the Zn vector registers with a width based on the maximum SVE vector register size, even though SME's maximum size could be larger. This is particularly bad in the case of a CPU with SME but not SVE, because there the SVE vector width will be zero. If we report the Zn registers in the XML as having a zero width then gdb falls over with an internal error: (gdb) target remote :1234 Remote debugging using :1234 /build/gdb-1WjiBe/gdb-15.0.50.20240403/gdb/aarch64-tdep.c:3066: internal-e= rror: aarch64_pseudo_register_type: bad register number 160 A problem internal to GDB has been detected, further debugging may prove unreliable. Report the Zn registers with their correct size. This matches how we already handle the 'vg' pseudoregister in org.gnu.gdb.aarch64.sve: we call sve_vqm1_for_el(), which returns the vector size accounting for SME, not the pure SVE vector size. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- We should make sure we have agreement on the gdb side about the interpretation of this bit of the protocol. See this gdb mailing list email: https://sourceware.org/pipermail/gdb/2026-January/052056.html --- target/arm/gdbstub64.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index c584e5b4e6..b71666c3a1 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -158,7 +158,7 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *b= uf, int reg) case 0 ... 31: { int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { + for (vq =3D 0; vq < arm_max_vq(cpu); vq++) { len +=3D gdb_get_reg128(buf, env->vfp.zregs[reg].d[vq * 2 + 1], env->vfp.zregs[reg].d[vq * 2]); @@ -174,7 +174,7 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *b= uf, int reg) { int preg =3D reg - 34; int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { + for (vq =3D 0; vq < arm_max_vq(cpu); vq =3D vq + 4) { len +=3D gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); } return len; @@ -208,7 +208,7 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf,= int reg) case 0 ... 31: { int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { + for (vq =3D 0; vq < arm_max_vq(cpu); vq++) { if (target_big_endian()) { env->vfp.zregs[reg].d[vq * 2 + 1] =3D ldq_p(buf); buf +=3D 8; @@ -233,7 +233,7 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf,= int reg) { int preg =3D reg - 34; int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { + for (vq =3D 0; vq < arm_max_vq(cpu); vq =3D vq + 4) { env->vfp.pregs[preg].p[vq / 4] =3D ldq_p(buf); buf +=3D 8; len +=3D 8; @@ -540,8 +540,8 @@ static void output_vector_union_type(GDBFeatureBuilder = *builder, int reg_width, GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg) { ARMCPU *cpu =3D ARM_CPU(cs); - int reg_width =3D cpu->sve_max_vq * 128; - int pred_width =3D cpu->sve_max_vq * 16; + int reg_width =3D arm_max_vq(cpu) * 128; + int pred_width =3D arm_max_vq(cpu) * 16; GDBFeatureBuilder builder; char *name; int reg =3D 0; --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039381; cv=none; d=zohomail.com; s=zohoarc; b=YXeLprNG97Z0UQAYxPSpb5JGxYF4c42NbMrfMIp5iLSAMdJyOwq0pq7nEpOKdyI0xYgaFqZPn/0tMZbr+fxGVxlY+l1qWe/uQaJxhBI/v+0gkKQjEk42/64pUEeh17mCZ9pNIkyYWNBM+qeBmjsVV+Rwx2/fFsMXrdLDjhwKwYY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039381; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ozYHqfgk0X+sYeYUfUg6SMvjxSTGckHgPzq9y9VW0U0=; b=F8I0Obvq2rXHRjXZDabwVhmWaPC1IVD2g1NnmBlSngvXBcDMNBPeUk6SbU3hgz6L7WzGvSClDOk0n4p0U6sWYGqJ7yaa0wPoi0YklyIqn6q7dmfzwRxzvr0ra43X+iHXcNnVRT/XQUPN0hWeWgZeZUrPnwDJ1t/W7n4ZToz0j94= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039381329175.754291304459; Mon, 2 Feb 2026 05:36:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu44-0006mK-Ug; Mon, 02 Feb 2026 08:34:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu42-0006kw-FA for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:02 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu40-0002aL-TY for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:02 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4806fbc6bf3so47830195e9.2 for ; Mon, 02 Feb 2026 05:34:00 -0800 (PST) Received: from lanath.. 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Use aa64_sve2 instead, so they UNDEF on an SVE1-only CPU as they should. Strictly, the condition here should be "SVE2 or SME"; but we will correct that in a following commit with all the other missing "or SME" checks. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 64adb5c1ce..81f487152c 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3769,7 +3769,7 @@ TRANS_FEAT(UDOT_zzxw_2s, aa64_sme2_or_sve2p1, gen_gve= c_ool_arg_zzxz, gen_helper_gvec_udot_idx_2h, a) =20 #define DO_SVE2_RRX(NAME, FUNC) \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzz, FUNC, \ a->rd, a->rn, a->rm, a->index) =20 DO_SVE2_RRX(MUL_zzx_h, gen_helper_gvec_mul_idx_h) @@ -3787,7 +3787,7 @@ DO_SVE2_RRX(SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_= idx_d) #undef DO_SVE2_RRX =20 #define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzz, FUNC, \ a->rd, a->rn, a->rm, (a->index << 1) | TOP) =20 DO_SVE2_RRX_TB(SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false) --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039274; cv=none; d=zohomail.com; s=zohoarc; b=RoOksZpW7LwAPlxsRHqVtYknDtur3z2if1HufOAlZmde9/vgQ6DYpOB3EhTJ8bi4EAVvIUgH3WWAmO3vPzCHFbYmZa8gyTnBK1SfU4BoYqV2v57D2W1660qe9BYIj0+j5Xl2IcfOCqViWthageUqO47KvZ6iykxqTKsid3jV2uw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039274; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ay+tH20ip5bhixA+bYgnF6LAzF+PwWUB9/hETGcO/pE=; b=ZVT2n2TjkIWcIKcR0FctvOoCZKzAaXumIvq0/G614lsAxnTncwYo7D8bM67zC4JlMN0TcHg8ILbMTdAEEykVASKLNMTV3gn9c51MCxaMl9BpYV8MIsQgc8LQj9d8OhxYFggsNplDik+GGLOt3mVMIIP4PutDQApukY40dQ+HDiI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039274278460.6849205323467; Mon, 2 Feb 2026 05:34:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu46-0006nb-JL; Mon, 02 Feb 2026 08:34:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu43-0006lg-Ka for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:03 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu41-0002c4-O7 for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:03 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4801bc32725so33485955e9.0 for ; Mon, 02 Feb 2026 05:34:01 -0800 (PST) Received: from lanath.. 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We forgot to allow this relaxation when we implemented SME2p1. Cc: qemu-stable@nongnu.org Fixes: 7b1613a1020d2 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 81f487152c..e853b4dd0a 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -7803,8 +7803,17 @@ TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gve= c_ool_arg_zzz, TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, gen_helper_crypto_sm4ekey, a, 0) =20 -TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, - gen_gvec_rax1, a) +static bool trans_RAX1(DisasContext *s, arg_RAX1 *a) +{ + if (!dc_isar_feature(aa64_sve2_sha3, s)) { + return false; + } + if (!dc_isar_feature(aa64_sme2p1, s)) { + /* SME2p1 adds this as valid in streaming SVE mode */ + s->is_nonstreaming =3D true; + } + return gen_gvec_fn_arg_zzz(s, gen_gvec_rax1, a); +} =20 TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039259; cv=none; d=zohomail.com; s=zohoarc; b=H5x8urVr/KI/zjoRa+HAOc17+XWxTYZBc7O7MWTJYhrGAwe83Gd5VWz/MQ2ce/usJwfdHsXkxEJru0YbpfsAaUEVHiaU+rdAPrVOj/QxNH5YbXe3EjDnXHNv8NTN5rSDvhdELIz2SANh+hhFNOfdeit2ibhUzy5RsbYgbVZ0PAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039259; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=am4mHMPcOaDWpeUBgMJCWJAj5MoT8YrEI2sYfgIQm8s=; b=JHCyKVMhyftLps+6vkpgU9C1u2pb0jVJkfaVQvj0CPO+3r/Fcc8uE1whDwm15ZF/dF+pygxaJ2BLO/zKaV97ZAN9SqM6kh2L3rWinDkBxt1jCeXfJx50gAzluW3CqS94fe1CrbOO9EK8Ki7zddTY4sJVo2aGmhkO/1bLO4FUxMM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039259031365.62969605529406; Mon, 2 Feb 2026 05:34:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu46-0006nc-PN; Mon, 02 Feb 2026 08:34:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu44-0006mI-ST for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:04 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu43-0002cj-6g for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:04 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4806f80cac9so23351865e9.1 for ; Mon, 02 Feb 2026 05:34:02 -0800 (PST) Received: from lanath.. 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This worked when the only valid values in that field were 0 (for no SME) and 1 (for SME1). However, with the addition of SME2 the SME field can now also read 2. This means that "-cpu max,sme=3Don" will result in an inconsistent set of ID registers, where ID_AA64PFR1_EL1.SME claims SME1 but ID_AA64SMFR0_EL1.SMEver claims SME2p1. This isn't a valid thing to report, and confuses Linux into reporting SME2 to userspace but not actually enabling userspace access for it. Fix this bug by having arm_cpu_sme_finalize() fix up the ID_AA64PFR1_EL1.SME field to match ID_AA64SMFR0.SMEver. This means the "sme" property's semantics are "off" for "no SME" and "on" for "enable at whatever the default SME version this CPU provides is". Update the documentation to clarify what 'sve=3Don' and 'sme=3Don' do. (We don't have the equivalent bug for 'sve=3Don' because ID_AA64PFR0_EL1.SVE only has 0 and 1 as valid values, but the semantics of the property are the same.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Manos Pitsidianakis Reviewed-by: Richard Henderson --- docs/system/arm/cpu-features.rst | 10 ++++++++++ target/arm/cpu64.c | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 37d5dfd15b..024119449c 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -318,6 +318,11 @@ SVE CPU Property Parsing Semantics provided an error will be generated. To avoid this error, one must enable at least one vector length prior to enabling SVE. =20 + 10) Enabling SVE (with ``sve=3Don`` or by default) enables all the SVE + sub-features that the CPU supports (for example, it may also + enable SVE2). There are not generally any lower-level controls + for disabling specific SVE sub-features. + SVE CPU Property Examples ------------------------- =20 @@ -430,6 +435,11 @@ and all vector lengths must be powers of 2. The maxim= um vector length supported by qemu is 2048 bits. Otherwise, there are no additional constraints on the set of vector lengths supported by SME. =20 +As with SVE, ``sme=3Don`` enables all the SME sub-features the CPU +supports (for example, it may also enable SME2), and there are +no lower-level controls for fine-grained disabling of specific +SME sub-features. + SME User-mode Default Vector Length Property -------------------------------------------- =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4dfc03973e..26873a39b4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -363,6 +363,16 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) =20 cpu->sme_vq.map =3D vq_map; cpu->sme_max_vq =3D 32 - clz32(vq_map); + + /* + * The "sme" property setter writes a bool value into ID_AA64PFR1_EL1.= SME + * (and at this point we know it's not 0). Correct that value to report + * the same SME version as ID_AA64SMFR0_EL1.SMEver. + */ + if (FIELD_EX64_IDREG(&cpu->isar, ID_AA64SMFR0, SMEVER) !=3D 0) { + /* SME2 or better */ + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, 2); + } } =20 static bool cpu_arm_get_sme(Object *obj, Error **errp) @@ -375,6 +385,11 @@ static void cpu_arm_set_sme(Object *obj, bool value, E= rror **errp) { ARMCPU *cpu =3D ARM_CPU(obj); =20 + /* + * For now, write 0 for "off" and 1 for "on" into the PFR1 field. + * We will correct this value to report the right SME + * level (SME vs SME2) in arm_cpu_sme_finalize() later. + */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value); } =20 --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039551; cv=none; d=zohomail.com; s=zohoarc; b=GriuuorAHMq0r68/1dxjDWm3ZPEy++xS2YhqjFlolkqgw8a1yxibRehj2MeObZ58+76KyUDAO1oy66mx+RyP0qNQZtySlW3Y3GHeL0NDCgfuldHhGhg5H+es4uLYLkgX+ktUIED1gUX6nF1hK+zSNNVDFFSEbP48GWgh3KNqeP8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039551; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aIgmMwISMpLwftLkUcpbNnEzoo+JvfxNkgOo0yRxeX4=; b=B3VrP5w6ehRQsGXfhPI6w7iS6Va6zyvZ2f6RvTZaeQue2o9ufz5LpX7uZ4XTUY+xbkKdGpxSxhZRloc2VNTc8KI/90l/aKt4gmjFvzEa4GuTaMLPBPG0ZdczubzrldPG0HoN5/RhiLaSEeGFNSBGadDXW/xjjSv70eVRtEfTs5c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039551305214.11349202972224; Mon, 2 Feb 2026 05:39:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu47-0006ns-88; Mon, 02 Feb 2026 08:34:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu45-0006mt-Uv for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:05 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu44-0002e1-Bn for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:05 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4801bc32725so33486425e9.0 for ; Mon, 02 Feb 2026 05:34:03 -0800 (PST) Received: from lanath.. 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This hits the "assert(sm)" at the bettom of the function in an SME-only CPU where sve_vq.map is zero. Add code to handle the "SME-only CPU not in streaming mode" case: we report an effective VL of 128 bits, which is what the architecture rule R_KXKNK says should be used when SVE instructions are disabled or trapped but floating point instructions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e7aa5ec2f2..e4a6ff17b1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4766,7 +4766,7 @@ int sme_exception_el(CPUARMState *env, int el) } =20 /* - * Given that SVE is enabled, return the vector length for EL. + * Given that SVE or SME is enabled, return the vector length for EL. */ uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm) { @@ -4778,6 +4778,12 @@ uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el= , bool sm) if (sm) { cr =3D env->vfp.smcr_el; map =3D cpu->sme_vq.map; + } else if (map =3D=3D 0) { + /* + * SME-only CPU not in streaming mode: effective VL + * is 128 bits, per R_KXKNK. + */ + return 0; } =20 if (el <=3D 1 && !el_is_in_host(env, el)) { --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039431; cv=none; d=zohomail.com; s=zohoarc; b=eZ7DzhbMADmAwczsYkL4r+qcpMgQw25S+Jt4zvkxMr74i7CVNl74HvCjKhByCt5QXgqNJcqo5nYSDTarSIs+cleQiwlUOcdMyIz1ua+aCBC6jcCQTs8Yp72yzZA97toLyIpuLgxhjPfF98drjbpnlXttJbfzguqXIWv4WvPqe1s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039431; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=56LjXDb4PPVvm50DRB3MZU7UUhroOyPSOJBt/6QB3aQ=; b=FEe5VL0PZvl+LP6M+r7DWVCednHxO+QYR6v3RSFgWfEXMYM6VhAXer98Oh0lA8osgwBANAqCYQuZO368VlxwMeO6wBmgt4zsfOLjQm8jU1/jul7J6+WvxQ0rPuBdGfpdsQj6crrygZeOXIRb+TJJfb7sNcrEQ5f9Rmio1lIrxBY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039431466493.63078797591197; Mon, 2 Feb 2026 05:37:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu48-0006oI-42; Mon, 02 Feb 2026 08:34:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu46-0006nd-PO for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:06 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu45-0002eM-8A for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:06 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4806f9e61f9so22649865e9.1 for ; Mon, 02 Feb 2026 05:34:04 -0800 (PST) Received: from lanath.. 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Update it to handle SME also. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e4a6ff17b1..390ea32c21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10130,8 +10130,8 @@ void aarch64_sve_change_el(CPUARMState *env, int ol= d_el, int old_len, new_len; bool old_a64, new_a64, sm; =20 - /* Nothing to do if no SVE. */ - if (!cpu_isar_feature(aa64_sve, cpu)) { + /* Nothing to do if no SVE or SME. */ + if (!cpu_isar_feature(aa64_sve, cpu) && !cpu_isar_feature(aa64_sme, cp= u)) { return; } =20 --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039261; cv=none; d=zohomail.com; s=zohoarc; b=HzYi5xVQsQgtpJb9/J5zOc3ayb1/T/wrfnthwWxxH/uoyY0EMFCR1zF5Qgjbuqb1aJ3m1U5WDk91wDSV0+/5wxXGoJXEMEJ7V2uZ+GK9a9UhlVqsxwViZ6XyvaQxTTbTHZuLMKHtwzU0Dm2zAHTFATo8faURx23BMF3ivTko8Hc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039261; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ru5XJrKtZr7yAFEWv9O9zNrT2SKiQUCPS6FnhctwJEI=; b=dnrSikwMCEzGe2d80ZV07pEUXC8K47TGOZWT4GdexPSvVbZn/HYuBvKIlS61lZhvH/6olIBjd38R2XEV1Qw0qWwi3fwYmdPQuh5cf4Kt2NVY2vzH91b+5wFTnUaIFamqRZ2wYRjIu6yz2lOtX6XNLfLRxSeYrZM3Zr9UuIP8OT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177003926141611.775234129011096; Mon, 2 Feb 2026 05:34:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu49-0006qL-U3; Mon, 02 Feb 2026 08:34:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu47-0006o1-UC for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:07 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu46-0002fU-BE for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:07 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-47ee0291921so42281505e9.3 for ; Mon, 02 Feb 2026 05:34:05 -0800 (PST) Received: from lanath.. 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We correctly handle this when the emulated CPU has both FEAT_SVE and FEAT_SME, because sve_access_check() includes the logic for this, matching the pseudocode CheckSVEEnabled(). However if the emulated CPU only implement FEAT_SME, it will fail the initial dc_isar_feature(aa64_sve, s) feature check, because this doesn't match the check in the per-instruction decode pseudocode, which is typically: !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) Add a new aa64_sme_or_sve feature function that we can use to update the relevant uses of aa64_sve, and similarly aa64_sme_or_sve2 for where we need to check FEAT_SVE2 || FEAT_SME. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index a7ca410dcb..40393d88f0 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1507,6 +1507,16 @@ static inline bool isar_feature_aa64_sme2p1(const AR= MISARegisters *id) /* * Combinations of feature tests, for ease of use with TRANS_FEAT. */ +static inline bool isar_feature_aa64_sme_or_sve(const ARMISARegisters *id) +{ + return isar_feature_aa64_sme(id) || isar_feature_aa64_sve(id); +} + +static inline bool isar_feature_aa64_sme_or_sve2(const ARMISARegisters *id) +{ + return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2(id); +} + static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *= id) { return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id); --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039257; cv=none; d=zohomail.com; s=zohoarc; b=HmjDkhig0k3XINwpAqfD6xu15WZfcxB6PTCTf3RVud7A5ViICg+vjEtyE3xYiULwn4KgJRqxoopf1D2cisw1e7E5JThx5gvqlesX8KytYKZcQBTSPcTpb97OtJOhHse7Rj97GtDXzvn0gdP/jIcYDtI6MBtp/hutppOx4oLSIrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039257; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=TSL0DRobOJUmxitsc5wiwq+Lq6G445z8884Xbak4UEA=; b=VhL3PKSrHuBWC75E5mL/zZbNREnO86Ta3ytYxsLqsbjiV2gI+057hEjetInBexXQgwsAMvLyvubJIyaxNdLQjGHzfTqkEpuAYVr82ZoPWJaRags9RFs7amiMWgxxvscFIKzcWj+8ClwhuXp3BMNcCw9qsIdVb58ydJnEtptz2oM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039257773551.1267406986266; Mon, 2 Feb 2026 05:34:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu4A-0006qf-PH; Mon, 02 Feb 2026 08:34:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu49-0006pl-51 for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:09 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu47-0002g4-NC for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:08 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4806bf39419so32953385e9.1 for ; Mon, 02 Feb 2026 05:34:07 -0800 (PST) Received: from lanath.. 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This is currently a redundant check because we only invoke this function via the macro invocation TRANS_FEAT(..., aa64_sve2, do_trans_pmull, ...) and it's actively wrong for an SME-only CPU, because these insns are also available via SME. Remove the unnecessary logic. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index e853b4dd0a..fe59126d2b 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -6782,8 +6782,6 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_e= sz *a, bool sel) return false; } s->is_nonstreaming =3D true; - } else if (!dc_isar_feature(aa64_sve, s)) { - return false; } return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); } --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039403; cv=none; d=zohomail.com; s=zohoarc; b=L9FxvBwg2bB0o1jiiph5p/XpjN5mLjBqOqUfheRT7EIu+iOw2CE+Z+dM58A9gTdXJdEyrcgz8Mp8tjj+rIEesknHuvRS6Wsw9yFS+k+w9mtD4QY/PMMUa4vhmjKfHDOM1JpOQrToE+lhCugR0ZRHoHcKyPSxLwoW4/g/DAtgGD0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039403; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hvFsqIvKxr/fKcWZDcUiBAaU7bhM8cl1WfDojNJqED8=; b=D4EK7wwMyUR8NovRUrn3Ghd2pxD2mSfG9DO9DbqEscMenYsMUJzroHW4zNoW+cIE7pzRcvWLjU4+qGlB/FKnXrR0RusvRu429NSY6BcTp60fQPJ7LgQxdQ83ZOAVh5o6R1/VIryaNGKNA74NnLkhNVrRmjnwj0zf2M6716Qy0Y0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177003940315032.57401296071487; Mon, 2 Feb 2026 05:36:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu4G-00076W-95; Mon, 02 Feb 2026 08:34:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu4E-00074T-4l for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:14 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu49-0002gi-CF for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:13 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-47ee0291921so42282355e9.3 for ; Mon, 02 Feb 2026 05:34:08 -0800 (PST) Received: from lanath.. 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Currently we largely check only for features aa64_sve or aa64_sve2. This happens to work because we forbid creation of a CPU with SME but not SVE. To allow users to create SME-only CPUs we need to update the conditions to use the "or SME" versions of the feature tests instead. This commit was created by going through translate-sve.c from top to bottom looking for aa64_sve feature tests and cross checking those against the instruction descriptions in the Arm ARM, which will say "(FEAT_SVE || FEAT_SME)" for instructions that are provided for both features, and "(FEAT_SME)" for the rarer instructions that are SME only. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- This is a large commit, but pretty mechanical. My suggestion for review is to look at translate-sve.c after it: the only remaining uses of the plain aa64_sve and aa64_sve2 feature checks should be in "nonstreaming" instructions, which are mostly handled via the TRANS_FEAT_NONSTREAMING macro and in some cases with open-coding of setting is_nonstreaming. --- target/arm/tcg/translate-sve.c | 854 ++++++++++++++++----------------- 1 file changed, 427 insertions(+), 427 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index fe59126d2b..44eda7b07d 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -570,14 +570,14 @@ static bool trans_INVALID(DisasContext *s, arg_INVALI= D *a) *** SVE Logical - Unpredicated Group */ =20 -TRANS_FEAT(AND_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and, a) -TRANS_FEAT(ORR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or, a) -TRANS_FEAT(EOR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor, a) -TRANS_FEAT(BIC_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_andc, a) +TRANS_FEAT(AND_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and= , a) +TRANS_FEAT(ORR_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or,= a) +TRANS_FEAT(EOR_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor= , a) +TRANS_FEAT(BIC_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and= c, a) =20 static bool trans_XAR(DisasContext *s, arg_rrri_esz *a) { - if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { + if (a->esz < 0 || !dc_isar_feature(aa64_sme_or_sve2, s)) { return false; } if (sve_access_check(s)) { @@ -589,8 +589,8 @@ static bool trans_XAR(DisasContext *s, arg_rrri_esz *a) return true; } =20 -TRANS_FEAT(EOR3, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_gvec_eor3, a) -TRANS_FEAT(BCAX, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_gvec_bcax, a) +TRANS_FEAT(EOR3, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_gvec_eor3, a) +TRANS_FEAT(BCAX, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_gvec_bcax, a) =20 static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m, uint32_t a, uint32_t oprsz, uint32_t maxsz) @@ -599,7 +599,7 @@ static void gen_bsl(unsigned vece, uint32_t d, uint32_t= n, uint32_t m, tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz); } =20 -TRANS_FEAT(BSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a) +TRANS_FEAT(BSL, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a) =20 static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) { @@ -628,7 +628,7 @@ static void gen_bsl1n(unsigned vece, uint32_t d, uint32= _t n, uint32_t m, tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } =20 -TRANS_FEAT(BSL1N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a) +TRANS_FEAT(BSL1N, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a) =20 static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) { @@ -666,7 +666,7 @@ static void gen_bsl2n(unsigned vece, uint32_t d, uint32= _t n, uint32_t m, tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } =20 -TRANS_FEAT(BSL2N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a) +TRANS_FEAT(BSL2N, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a) =20 static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) { @@ -695,18 +695,18 @@ static void gen_nbsl(unsigned vece, uint32_t d, uint3= 2_t n, uint32_t m, tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } =20 -TRANS_FEAT(NBSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a) +TRANS_FEAT(NBSL, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a) =20 /* *** SVE Integer Arithmetic - Unpredicated Group */ =20 -TRANS_FEAT(ADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add, a) -TRANS_FEAT(SUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub, a) -TRANS_FEAT(SQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ssadd, a) -TRANS_FEAT(SQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sssub, a) -TRANS_FEAT(UQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_usadd, a) -TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a) +TRANS_FEAT(ADD_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add= , a) +TRANS_FEAT(SUB_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub= , a) +TRANS_FEAT(SQADD_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_s= sadd, a) +TRANS_FEAT(SQSUB_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_s= ssub, a) +TRANS_FEAT(UQADD_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_u= sadd, a) +TRANS_FEAT(UQSUB_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_u= ssub, a) =20 /* *** SVE Integer Arithmetic - Binary Predicated Group @@ -732,40 +732,40 @@ static bool do_sel_z(DisasContext *s, int rd, int rn,= int rm, int pg, int esz) TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpzz, \ name##_zpzz_fns[a->esz], a, 0) =20 -DO_ZPZZ(AND_zpzz, aa64_sve, sve_and) -DO_ZPZZ(EOR_zpzz, aa64_sve, sve_eor) -DO_ZPZZ(ORR_zpzz, aa64_sve, sve_orr) -DO_ZPZZ(BIC_zpzz, aa64_sve, sve_bic) +DO_ZPZZ(AND_zpzz, aa64_sme_or_sve, sve_and) +DO_ZPZZ(EOR_zpzz, aa64_sme_or_sve, sve_eor) +DO_ZPZZ(ORR_zpzz, aa64_sme_or_sve, sve_orr) +DO_ZPZZ(BIC_zpzz, aa64_sme_or_sve, sve_bic) =20 -DO_ZPZZ(ADD_zpzz, aa64_sve, sve_add) -DO_ZPZZ(SUB_zpzz, aa64_sve, sve_sub) +DO_ZPZZ(ADD_zpzz, aa64_sme_or_sve, sve_add) +DO_ZPZZ(SUB_zpzz, aa64_sme_or_sve, sve_sub) =20 -DO_ZPZZ(SMAX_zpzz, aa64_sve, sve_smax) -DO_ZPZZ(UMAX_zpzz, aa64_sve, sve_umax) -DO_ZPZZ(SMIN_zpzz, aa64_sve, sve_smin) -DO_ZPZZ(UMIN_zpzz, aa64_sve, sve_umin) -DO_ZPZZ(SABD_zpzz, aa64_sve, sve_sabd) -DO_ZPZZ(UABD_zpzz, aa64_sve, sve_uabd) +DO_ZPZZ(SMAX_zpzz, aa64_sme_or_sve, sve_smax) +DO_ZPZZ(UMAX_zpzz, aa64_sme_or_sve, sve_umax) +DO_ZPZZ(SMIN_zpzz, aa64_sme_or_sve, sve_smin) +DO_ZPZZ(UMIN_zpzz, aa64_sme_or_sve, sve_umin) +DO_ZPZZ(SABD_zpzz, aa64_sme_or_sve, sve_sabd) +DO_ZPZZ(UABD_zpzz, aa64_sme_or_sve, sve_uabd) =20 -DO_ZPZZ(MUL_zpzz, aa64_sve, sve_mul) -DO_ZPZZ(SMULH_zpzz, aa64_sve, sve_smulh) -DO_ZPZZ(UMULH_zpzz, aa64_sve, sve_umulh) +DO_ZPZZ(MUL_zpzz, aa64_sme_or_sve, sve_mul) +DO_ZPZZ(SMULH_zpzz, aa64_sme_or_sve, sve_smulh) +DO_ZPZZ(UMULH_zpzz, aa64_sme_or_sve, sve_umulh) =20 -DO_ZPZZ(ASR_zpzz, aa64_sve, sve_asr) -DO_ZPZZ(LSR_zpzz, aa64_sve, sve_lsr) -DO_ZPZZ(LSL_zpzz, aa64_sve, sve_lsl) +DO_ZPZZ(ASR_zpzz, aa64_sme_or_sve, sve_asr) +DO_ZPZZ(LSR_zpzz, aa64_sme_or_sve, sve_lsr) +DO_ZPZZ(LSL_zpzz, aa64_sme_or_sve, sve_lsl) =20 static gen_helper_gvec_4 * const sdiv_fns[4] =3D { NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d }; -TRANS_FEAT(SDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, sdiv_fns[a->esz], a= , 0) +TRANS_FEAT(SDIV_zpzz, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, sdiv_fns[a->= esz], a, 0) =20 static gen_helper_gvec_4 * const udiv_fns[4] =3D { NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d }; -TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a= , 0) +TRANS_FEAT(UDIV_zpzz, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->= esz], a, 0) =20 -TRANS_FEAT(SEL_zpzz, aa64_sve, do_sel_z, a->rd, a->rn, a->rm, a->pg, a->es= z) +TRANS_FEAT(SEL_zpzz, aa64_sme_or_sve, do_sel_z, a->rd, a->rn, a->rm, a->pg= , a->esz) =20 /* *** SVE Integer Arithmetic - Unary Predicated Group @@ -778,14 +778,14 @@ TRANS_FEAT(SEL_zpzz, aa64_sve, do_sel_z, a->rd, a->rn= , a->rm, a->pg, a->esz) }; \ TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0) =20 -DO_ZPZ(CLS, aa64_sve, sve_cls) -DO_ZPZ(CLZ, aa64_sve, sve_clz) -DO_ZPZ(CNT_zpz, aa64_sve, sve_cnt_zpz) -DO_ZPZ(CNOT, aa64_sve, sve_cnot) -DO_ZPZ(NOT_zpz, aa64_sve, sve_not_zpz) -DO_ZPZ(ABS, aa64_sve, sve_abs) -DO_ZPZ(NEG, aa64_sve, sve_neg) -DO_ZPZ(RBIT, aa64_sve, sve_rbit) +DO_ZPZ(CLS, aa64_sme_or_sve, sve_cls) +DO_ZPZ(CLZ, aa64_sme_or_sve, sve_clz) +DO_ZPZ(CNT_zpz, aa64_sme_or_sve, sve_cnt_zpz) +DO_ZPZ(CNOT, aa64_sme_or_sve, sve_cnot) +DO_ZPZ(NOT_zpz, aa64_sme_or_sve, sve_not_zpz) +DO_ZPZ(ABS, aa64_sme_or_sve, sve_abs) +DO_ZPZ(NEG, aa64_sme_or_sve, sve_neg) +DO_ZPZ(RBIT, aa64_sme_or_sve, sve_rbit) DO_ZPZ(ORQV, aa64_sme2p1_or_sve2p1, sve2p1_orqv) DO_ZPZ(EORQV, aa64_sme2p1_or_sve2p1, sve2p1_eorqv) DO_ZPZ(ANDQV, aa64_sme2p1_or_sve2p1, sve2p1_andqv) @@ -798,7 +798,7 @@ static gen_helper_gvec_3 * const fabs_ah_fns[4] =3D { NULL, gen_helper_sve_ah_fabs_h, gen_helper_sve_ah_fabs_s, gen_helper_sve_ah_fabs_d, }; -TRANS_FEAT(FABS, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(FABS, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fabs_ah_fns[a->esz] : fabs_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const fneg_fns[4] =3D { @@ -809,34 +809,34 @@ static gen_helper_gvec_3 * const fneg_ah_fns[4] =3D { NULL, gen_helper_sve_ah_fneg_h, gen_helper_sve_ah_fneg_s, gen_helper_sve_ah_fneg_d, }; -TRANS_FEAT(FNEG, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(FNEG, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fneg_ah_fns[a->esz] : fneg_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const sxtb_fns[4] =3D { NULL, gen_helper_sve_sxtb_h, gen_helper_sve_sxtb_s, gen_helper_sve_sxtb_d, }; -TRANS_FEAT(SXTB, aa64_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], a, 0) +TRANS_FEAT(SXTB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], = a, 0) =20 static gen_helper_gvec_3 * const uxtb_fns[4] =3D { NULL, gen_helper_sve_uxtb_h, gen_helper_sve_uxtb_s, gen_helper_sve_uxtb_d, }; -TRANS_FEAT(UXTB, aa64_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], a, 0) +TRANS_FEAT(UXTB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], = a, 0) =20 static gen_helper_gvec_3 * const sxth_fns[4] =3D { NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d }; -TRANS_FEAT(SXTH, aa64_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], a, 0) +TRANS_FEAT(SXTH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], = a, 0) =20 static gen_helper_gvec_3 * const uxth_fns[4] =3D { NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d }; -TRANS_FEAT(UXTH, aa64_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], a, 0) +TRANS_FEAT(UXTH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], = a, 0) =20 -TRANS_FEAT(SXTW, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(SXTW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_sxtw_d : NULL, a, 0) -TRANS_FEAT(UXTW, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(UXTW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_uxtw_d : NULL, a, 0) =20 static gen_helper_gvec_3 * const addqv_fns[4] =3D { @@ -912,7 +912,7 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_vpz_ool, a, name##_fns[a->esz]) + TRANS_FEAT(NAME, aa64_sme_or_sve, do_vpz_ool, a, name##_fns[a->esz]) =20 DO_VPZ(ORV, orv) DO_VPZ(ANDV, andv) @@ -928,7 +928,7 @@ static gen_helper_gvec_reduc * const saddv_fns[4] =3D { gen_helper_sve_saddv_b, gen_helper_sve_saddv_h, gen_helper_sve_saddv_s, NULL }; -TRANS_FEAT(SADDV, aa64_sve, do_vpz_ool, a, saddv_fns[a->esz]) +TRANS_FEAT(SADDV, aa64_sme_or_sve, do_vpz_ool, a, saddv_fns[a->esz]) =20 #undef DO_VPZ =20 @@ -980,59 +980,59 @@ static gen_helper_gvec_3 * const asr_zpzi_fns[4] =3D { gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h, gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d, }; -TRANS_FEAT(ASR_zpzi, aa64_sve, do_shift_zpzi, a, true, asr_zpzi_fns) +TRANS_FEAT(ASR_zpzi, aa64_sme_or_sve, do_shift_zpzi, a, true, asr_zpzi_fns) =20 static gen_helper_gvec_3 * const lsr_zpzi_fns[4] =3D { gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h, gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d, }; -TRANS_FEAT(LSR_zpzi, aa64_sve, do_shift_zpzi, a, false, lsr_zpzi_fns) +TRANS_FEAT(LSR_zpzi, aa64_sme_or_sve, do_shift_zpzi, a, false, lsr_zpzi_fn= s) =20 static gen_helper_gvec_3 * const lsl_zpzi_fns[4] =3D { gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h, gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d, }; -TRANS_FEAT(LSL_zpzi, aa64_sve, do_shift_zpzi, a, false, lsl_zpzi_fns) +TRANS_FEAT(LSL_zpzi, aa64_sme_or_sve, do_shift_zpzi, a, false, lsl_zpzi_fn= s) =20 static gen_helper_gvec_3 * const asrd_fns[4] =3D { gen_helper_sve_asrd_b, gen_helper_sve_asrd_h, gen_helper_sve_asrd_s, gen_helper_sve_asrd_d, }; -TRANS_FEAT(ASRD, aa64_sve, do_shift_zpzi, a, false, asrd_fns) +TRANS_FEAT(ASRD, aa64_sme_or_sve, do_shift_zpzi, a, false, asrd_fns) =20 static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] =3D { gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h, gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d, }; -TRANS_FEAT(SQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(SQSHL_zpzi, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : sqshl_zpzi_fns[a->esz], a) =20 static gen_helper_gvec_3 * const uqshl_zpzi_fns[4] =3D { gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h, gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d, }; -TRANS_FEAT(UQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(UQSHL_zpzi, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : uqshl_zpzi_fns[a->esz], a) =20 static gen_helper_gvec_3 * const srshr_fns[4] =3D { gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h, gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d, }; -TRANS_FEAT(SRSHR, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(SRSHR, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : srshr_fns[a->esz], a) =20 static gen_helper_gvec_3 * const urshr_fns[4] =3D { gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h, gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d, }; -TRANS_FEAT(URSHR, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(URSHR, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : urshr_fns[a->esz], a) =20 static gen_helper_gvec_3 * const sqshlu_fns[4] =3D { gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h, gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d, }; -TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(SQSHLU, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : sqshlu_fns[a->esz], a) =20 /* @@ -1044,7 +1044,7 @@ TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi, gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ gen_helper_sve_##name##_zpzw_s, NULL \ }; \ - TRANS_FEAT(NAME##_zpzw, aa64_sve, gen_gvec_ool_arg_zpzz, \ + TRANS_FEAT(NAME##_zpzw, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, = \ a->esz < 0 ? NULL : name##_zpzw_fns[a->esz], a, 0) =20 DO_ZPZW(ASR, asr) @@ -1084,16 +1084,16 @@ static bool do_shift_imm(DisasContext *s, arg_rri_e= sz *a, bool asr, return true; } =20 -TRANS_FEAT(ASR_zzi, aa64_sve, do_shift_imm, a, true, tcg_gen_gvec_sari) -TRANS_FEAT(LSR_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shri) -TRANS_FEAT(LSL_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shli) +TRANS_FEAT(ASR_zzi, aa64_sme_or_sve, do_shift_imm, a, true, tcg_gen_gvec_s= ari) +TRANS_FEAT(LSR_zzi, aa64_sme_or_sve, do_shift_imm, a, false, tcg_gen_gvec_= shri) +TRANS_FEAT(LSL_zzi, aa64_sme_or_sve, do_shift_imm, a, false, tcg_gen_gvec_= shli) =20 #define DO_ZZW(NAME, name) \ static gen_helper_gvec_3 * const name##_zzw_fns[4] =3D { = \ gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \ gen_helper_sve_##name##_zzw_s, NULL \ }; \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_arg_zzz, \ + TRANS_FEAT(NAME, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, = \ name##_zzw_fns[a->esz], a, 0) =20 DO_ZZW(ASR_zzw, asr) @@ -1125,13 +1125,13 @@ static gen_helper_gvec_5 * const mla_fns[4] =3D { gen_helper_sve_mla_b, gen_helper_sve_mla_h, gen_helper_sve_mla_s, gen_helper_sve_mla_d, }; -TRANS_FEAT(MLA, aa64_sve, do_zpzzz_ool, a, mla_fns[a->esz]) +TRANS_FEAT(MLA, aa64_sme_or_sve, do_zpzzz_ool, a, mla_fns[a->esz]) =20 static gen_helper_gvec_5 * const mls_fns[4] =3D { gen_helper_sve_mls_b, gen_helper_sve_mls_h, gen_helper_sve_mls_s, gen_helper_sve_mls_d, }; -TRANS_FEAT(MLS, aa64_sve, do_zpzzz_ool, a, mls_fns[a->esz]) +TRANS_FEAT(MLS, aa64_sme_or_sve, do_zpzzz_ool, a, mls_fns[a->esz]) =20 /* *** SVE Index Generation Group @@ -1172,13 +1172,13 @@ static bool do_index(DisasContext *s, int esz, int = rd, return true; } =20 -TRANS_FEAT(INDEX_ii, aa64_sve, do_index, a->esz, a->rd, +TRANS_FEAT(INDEX_ii, aa64_sme_or_sve, do_index, a->esz, a->rd, tcg_constant_i64(a->imm1), tcg_constant_i64(a->imm2)) -TRANS_FEAT(INDEX_ir, aa64_sve, do_index, a->esz, a->rd, +TRANS_FEAT(INDEX_ir, aa64_sme_or_sve, do_index, a->esz, a->rd, tcg_constant_i64(a->imm), cpu_reg(s, a->rm)) -TRANS_FEAT(INDEX_ri, aa64_sve, do_index, a->esz, a->rd, +TRANS_FEAT(INDEX_ri, aa64_sme_or_sve, do_index, a->esz, a->rd, cpu_reg(s, a->rn), tcg_constant_i64(a->imm)) -TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->rd, +TRANS_FEAT(INDEX_rr, aa64_sme_or_sve, do_index, a->esz, a->rd, cpu_reg(s, a->rn), cpu_reg(s, a->rm)) =20 /* @@ -1187,7 +1187,7 @@ TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->r= d, =20 static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1213,7 +1213,7 @@ static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL = *a) =20 static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1239,7 +1239,7 @@ static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL = *a) =20 static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1370,7 +1370,7 @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!a->s) { @@ -1408,7 +1408,7 @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!a->s && a->pg =3D=3D a->rn) { @@ -1439,7 +1439,7 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } /* Alias NOT (predicate) is EOR Pd.B, Pg/Z, Pn.B, Pg.B */ @@ -1451,7 +1451,7 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_= s *a) =20 static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a) { - if (a->s || !dc_isar_feature(aa64_sve, s)) { + if (a->s || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1486,7 +1486,7 @@ static bool trans_ORR_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!a->s && a->pg =3D=3D a->rn && a->rn =3D=3D a->rm) { @@ -1517,7 +1517,7 @@ static bool trans_ORN_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } return do_pppp_flags(s, a, &op); @@ -1545,7 +1545,7 @@ static bool trans_NOR_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } return do_pppp_flags(s, a, &op); @@ -1573,7 +1573,7 @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr= _s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } return do_pppp_flags(s, a, &op); @@ -1585,7 +1585,7 @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr= _s *a) =20 static bool trans_PTEST(DisasContext *s, arg_PTEST *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1723,7 +1723,7 @@ static bool do_predset(DisasContext *s, int esz, int = rd, int pat, bool setflag) return true; } =20 -TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s) +TRANS_FEAT(PTRUE, aa64_sme_or_sve, do_predset, a->esz, a->rd, a->pat, a->s) =20 static bool trans_PTRUE_cnt(DisasContext *s, arg_PTRUE_cnt *a) { @@ -1746,7 +1746,7 @@ TRANS_FEAT_NONSTREAMING(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false) =20 /* Note pat =3D=3D 32 is #unimp, to set no elements. */ -TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false) +TRANS_FEAT(PFALSE, aa64_sme_or_sve, do_predset, 0, a->rd, 32, false) =20 static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a) { @@ -1791,8 +1791,8 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_e= sz *a, return true; } =20 -TRANS_FEAT(PFIRST, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pfirst) -TRANS_FEAT(PNEXT, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pnext) +TRANS_FEAT(PFIRST, aa64_sme_or_sve, do_pfirst_pnext, a, gen_helper_sve_pfi= rst) +TRANS_FEAT(PNEXT, aa64_sme_or_sve, do_pfirst_pnext, a, gen_helper_sve_pnex= t) =20 /* *** SVE Element Count Group @@ -1946,7 +1946,7 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, =20 static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1959,7 +1959,7 @@ static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) =20 static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1975,7 +1975,7 @@ static bool trans_INCDEC_r(DisasContext *s, arg_incde= c_cnt *a) =20 static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!sve_access_check(s)) { @@ -2002,7 +2002,7 @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_i= ncdec_cnt *a) =20 static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!sve_access_check(s)) { @@ -2022,7 +2022,7 @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_i= ncdec_cnt *a) =20 static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } =20 @@ -2045,7 +2045,7 @@ static bool trans_INCDEC_v(DisasContext *s, arg_incde= c2_cnt *a) =20 static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } =20 @@ -2079,15 +2079,15 @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *= a, GVecGen2iFn *gvec_fn) return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm); } =20 -TRANS_FEAT(AND_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_andi) -TRANS_FEAT(ORR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_ori) -TRANS_FEAT(EOR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_xori) +TRANS_FEAT(AND_zzi, aa64_sme_or_sve, do_zz_dbm, a, tcg_gen_gvec_andi) +TRANS_FEAT(ORR_zzi, aa64_sme_or_sve, do_zz_dbm, a, tcg_gen_gvec_ori) +TRANS_FEAT(EOR_zzi, aa64_sme_or_sve, do_zz_dbm, a, tcg_gen_gvec_xori) =20 static bool trans_DUPM(DisasContext *s, arg_DUPM *a) { uint64_t imm; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), @@ -2131,7 +2131,7 @@ static void do_cpy_m(DisasContext *s, int esz, int rd= , int rn, int pg, =20 static bool trans_FCPY(DisasContext *s, arg_FCPY *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2144,7 +2144,7 @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a) =20 static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2160,7 +2160,7 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_= i *a) gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2207,8 +2207,8 @@ static bool do_EXT(DisasContext *s, int rd, int rn, i= nt rm, int imm) return true; } =20 -TRANS_FEAT(EXT, aa64_sve, do_EXT, a->rd, a->rn, a->rm, a->imm) -TRANS_FEAT(EXT_sve2, aa64_sve2, do_EXT, a->rd, a->rn, (a->rn + 1) % 32, a-= >imm) +TRANS_FEAT(EXT, aa64_sme_or_sve, do_EXT, a->rd, a->rn, a->rm, a->imm) +TRANS_FEAT(EXT_sve2, aa64_sme_or_sve2, do_EXT, a->rd, a->rn, (a->rn + 1) %= 32, a->imm) =20 static bool trans_EXTQ(DisasContext *s, arg_EXTQ *a) { @@ -2265,7 +2265,7 @@ static bool trans_EXTQ(DisasContext *s, arg_EXTQ *a) =20 static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2278,7 +2278,7 @@ static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a) =20 static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if ((a->imm & 0x1f) =3D=3D 0) { @@ -2347,7 +2347,7 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz = *a, TCGv_i64 val) =20 static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2360,7 +2360,7 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz= *a) =20 static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2373,19 +2373,19 @@ static gen_helper_gvec_2 * const rev_fns[4] =3D { gen_helper_sve_rev_b, gen_helper_sve_rev_h, gen_helper_sve_rev_s, gen_helper_sve_rev_d }; -TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn= , 0) +TRANS_FEAT(REV_v, aa64_sme_or_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd= , a->rn, 0) =20 static gen_helper_gvec_3 * const sve_tbl_fns[4] =3D { gen_helper_sve_tbl_b, gen_helper_sve_tbl_h, gen_helper_sve_tbl_s, gen_helper_sve_tbl_d }; -TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0) +TRANS_FEAT(TBL, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz]= , a, 0) =20 static gen_helper_gvec_4 * const sve2_tbl_fns[4] =3D { gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h, gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d }; -TRANS_FEAT(TBL_sve2, aa64_sve2, gen_gvec_ool_zzzz, sve2_tbl_fns[a->esz], +TRANS_FEAT(TBL_sve2, aa64_sme_or_sve2, gen_gvec_ool_zzzz, sve2_tbl_fns[a->= esz], a->rd, a->rn, (a->rn + 1) % 32, a->rm, 0) =20 static gen_helper_gvec_3 * const tblq_fns[4] =3D { @@ -2399,7 +2399,7 @@ static gen_helper_gvec_3 * const tbx_fns[4] =3D { gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h, gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d }; -TRANS_FEAT(TBX, aa64_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a, 0) +TRANS_FEAT(TBX, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a= , 0) =20 static gen_helper_gvec_3 * const tbxq_fns[4] =3D { gen_helper_sve2p1_tbxq_b, gen_helper_sve2p1_tbxq_h, @@ -2515,7 +2515,7 @@ static bool trans_UNPK(DisasContext *s, arg_UNPK *a) { gen_helper_sve_sunpk_d, gen_helper_sve_uunpk_d }, }; =20 - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2581,16 +2581,16 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_e= sz *a, bool high_odd, return true; } =20 -TRANS_FEAT(ZIP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_zip_p) -TRANS_FEAT(ZIP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_zip_p) -TRANS_FEAT(UZP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_uzp_p) -TRANS_FEAT(UZP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_uzp_p) -TRANS_FEAT(TRN1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_trn_p) -TRANS_FEAT(TRN2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_trn_p) +TRANS_FEAT(ZIP1_p, aa64_sme_or_sve, do_perm_pred3, a, 0, gen_helper_sve_zi= p_p) +TRANS_FEAT(ZIP2_p, aa64_sme_or_sve, do_perm_pred3, a, 1, gen_helper_sve_zi= p_p) +TRANS_FEAT(UZP1_p, aa64_sme_or_sve, do_perm_pred3, a, 0, gen_helper_sve_uz= p_p) +TRANS_FEAT(UZP2_p, aa64_sme_or_sve, do_perm_pred3, a, 1, gen_helper_sve_uz= p_p) +TRANS_FEAT(TRN1_p, aa64_sme_or_sve, do_perm_pred3, a, 0, gen_helper_sve_tr= n_p) +TRANS_FEAT(TRN2_p, aa64_sme_or_sve, do_perm_pred3, a, 1, gen_helper_sve_tr= n_p) =20 -TRANS_FEAT(REV_p, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_rev_p) -TRANS_FEAT(PUNPKLO, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_punpk_p) -TRANS_FEAT(PUNPKHI, aa64_sve, do_perm_pred2, a, 1, gen_helper_sve_punpk_p) +TRANS_FEAT(REV_p, aa64_sme_or_sve, do_perm_pred2, a, 0, gen_helper_sve_rev= _p) +TRANS_FEAT(PUNPKLO, aa64_sme_or_sve, do_perm_pred2, a, 0, gen_helper_sve_p= unpk_p) +TRANS_FEAT(PUNPKHI, aa64_sme_or_sve, do_perm_pred2, a, 1, gen_helper_sve_p= unpk_p) =20 /* *** SVE Permute - Interleaving Group @@ -2617,9 +2617,9 @@ static gen_helper_gvec_3 * const zip_fns[4] =3D { gen_helper_sve_zip_b, gen_helper_sve_zip_h, gen_helper_sve_zip_s, gen_helper_sve_zip_d, }; -TRANS_FEAT(ZIP1_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(ZIP1_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, zip_fns[a->esz], a, 0) -TRANS_FEAT(ZIP2_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(ZIP2_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, zip_fns[a->esz], a, vec_full_reg_size(s) / 2) =20 TRANS_FEAT_NONSTREAMING(ZIP1_q, aa64_sve_f64mm, do_interleave_q, @@ -2641,9 +2641,9 @@ static gen_helper_gvec_3 * const uzp_fns[4] =3D { gen_helper_sve_uzp_b, gen_helper_sve_uzp_h, gen_helper_sve_uzp_s, gen_helper_sve_uzp_d, }; -TRANS_FEAT(UZP1_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UZP1_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, uzp_fns[a->esz], a, 0) -TRANS_FEAT(UZP2_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UZP2_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, uzp_fns[a->esz], a, 1 << a->esz) =20 TRANS_FEAT_NONSTREAMING(UZP1_q, aa64_sve_f64mm, do_interleave_q, @@ -2665,9 +2665,9 @@ static gen_helper_gvec_3 * const trn_fns[4] =3D { gen_helper_sve_trn_s, gen_helper_sve_trn_d, }; =20 -TRANS_FEAT(TRN1_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(TRN1_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, trn_fns[a->esz], a, 0) -TRANS_FEAT(TRN2_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(TRN2_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, trn_fns[a->esz], a, 1 << a->esz) =20 TRANS_FEAT_NONSTREAMING(TRN1_q, aa64_sve_f64mm, do_interleave_q, @@ -2828,8 +2828,8 @@ static bool do_clast_vector(DisasContext *s, arg_rprr= _esz *a, bool before) return true; } =20 -TRANS_FEAT(CLASTA_z, aa64_sve, do_clast_vector, a, false) -TRANS_FEAT(CLASTB_z, aa64_sve, do_clast_vector, a, true) +TRANS_FEAT(CLASTA_z, aa64_sme_or_sve, do_clast_vector, a, false) +TRANS_FEAT(CLASTB_z, aa64_sme_or_sve, do_clast_vector, a, true) =20 /* Compute CLAST for a scalar. */ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm, @@ -2873,8 +2873,8 @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz = *a, bool before) return true; } =20 -TRANS_FEAT(CLASTA_v, aa64_sve, do_clast_fp, a, false) -TRANS_FEAT(CLASTB_v, aa64_sve, do_clast_fp, a, true) +TRANS_FEAT(CLASTA_v, aa64_sme_or_sve, do_clast_fp, a, false) +TRANS_FEAT(CLASTB_v, aa64_sme_or_sve, do_clast_fp, a, true) =20 /* Compute CLAST for a Xreg. */ static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before) @@ -2906,8 +2906,8 @@ static bool do_clast_general(DisasContext *s, arg_rpr= _esz *a, bool before) return true; } =20 -TRANS_FEAT(CLASTA_r, aa64_sve, do_clast_general, a, false) -TRANS_FEAT(CLASTB_r, aa64_sve, do_clast_general, a, true) +TRANS_FEAT(CLASTA_r, aa64_sme_or_sve, do_clast_general, a, false) +TRANS_FEAT(CLASTB_r, aa64_sme_or_sve, do_clast_general, a, true) =20 /* Compute LAST for a scalar. */ static TCGv_i64 do_last_scalar(DisasContext *s, int esz, @@ -2935,8 +2935,8 @@ static bool do_last_fp(DisasContext *s, arg_rpr_esz *= a, bool before) return true; } =20 -TRANS_FEAT(LASTA_v, aa64_sve, do_last_fp, a, false) -TRANS_FEAT(LASTB_v, aa64_sve, do_last_fp, a, true) +TRANS_FEAT(LASTA_v, aa64_sme_or_sve, do_last_fp, a, false) +TRANS_FEAT(LASTB_v, aa64_sme_or_sve, do_last_fp, a, true) =20 /* Compute LAST for a Xreg. */ static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before) @@ -2948,12 +2948,12 @@ static bool do_last_general(DisasContext *s, arg_rp= r_esz *a, bool before) return true; } =20 -TRANS_FEAT(LASTA_r, aa64_sve, do_last_general, a, false) -TRANS_FEAT(LASTB_r, aa64_sve, do_last_general, a, true) +TRANS_FEAT(LASTA_r, aa64_sme_or_sve, do_last_general, a, false) +TRANS_FEAT(LASTB_r, aa64_sme_or_sve, do_last_general, a, true) =20 static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2964,7 +2964,7 @@ static bool trans_CPY_m_r(DisasContext *s, arg_rpr_es= z *a) =20 static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2979,22 +2979,22 @@ static gen_helper_gvec_3 * const revb_fns[4] =3D { NULL, gen_helper_sve_revb_h, gen_helper_sve_revb_s, gen_helper_sve_revb_d, }; -TRANS_FEAT(REVB, aa64_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], a, 0) +TRANS_FEAT(REVB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], = a, 0) =20 static gen_helper_gvec_3 * const revh_fns[4] =3D { NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d, }; -TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0) +TRANS_FEAT(REVH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], = a, 0) =20 -TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(REVW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_revw_d : NULL, a, 0) =20 TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a,= 0) =20 -TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, +TRANS_FEAT(SPLICE, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, gen_helper_sve_splice, a, a->esz) =20 -TRANS_FEAT(SPLICE_sve2, aa64_sve2, gen_gvec_ool_zzzp, gen_helper_sve_splic= e, +TRANS_FEAT(SPLICE_sve2, aa64_sme_or_sve2, gen_gvec_ool_zzzp, gen_helper_sv= e_splice, a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz) =20 /* @@ -3038,7 +3038,7 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_e= sz *a, gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \ gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \ }; \ - TRANS_FEAT(NAME##_ppzz, aa64_sve, do_ppzz_flags, \ + TRANS_FEAT(NAME##_ppzz, aa64_sme_or_sve, do_ppzz_flags, = \ a, name##_ppzz_fns[a->esz]) =20 DO_PPZZ(CMPEQ, cmpeq) @@ -3055,7 +3055,7 @@ DO_PPZZ(CMPHS, cmphs) gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \ gen_helper_sve_##name##_ppzw_s, NULL \ }; \ - TRANS_FEAT(NAME##_ppzw, aa64_sve, do_ppzz_flags, \ + TRANS_FEAT(NAME##_ppzw, aa64_sme_or_sve, do_ppzz_flags, = \ a, name##_ppzw_fns[a->esz]) =20 DO_PPZW(CMPEQ, cmpeq) @@ -3110,7 +3110,7 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_e= sz *a, gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \ gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \ }; \ - TRANS_FEAT(NAME##_ppzi, aa64_sve, do_ppzi_flags, a, \ + TRANS_FEAT(NAME##_ppzi, aa64_sme_or_sve, do_ppzi_flags, a, = \ name##_ppzi_fns[a->esz]) =20 DO_PPZI(CMPEQ, cmpeq) @@ -3190,22 +3190,22 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a, return true; } =20 -TRANS_FEAT(BRKPA, aa64_sve, do_brk3, a, +TRANS_FEAT(BRKPA, aa64_sme_or_sve, do_brk3, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas) -TRANS_FEAT(BRKPB, aa64_sve, do_brk3, a, +TRANS_FEAT(BRKPB, aa64_sme_or_sve, do_brk3, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs) =20 -TRANS_FEAT(BRKA_m, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKA_m, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m) -TRANS_FEAT(BRKB_m, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKB_m, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m) =20 -TRANS_FEAT(BRKA_z, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKA_z, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z) -TRANS_FEAT(BRKB_z, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKB_z, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z) =20 -TRANS_FEAT(BRKN, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKN, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brkn, gen_helper_sve_brkns) =20 /* @@ -3250,7 +3250,7 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, in= t esz, int pn, int pg) =20 static bool trans_CNTP(DisasContext *s, arg_CNTP *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3291,7 +3291,7 @@ static bool trans_CNTP_c(DisasContext *s, arg_CNTP_c = *a) =20 static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3310,7 +3310,7 @@ static bool trans_INCDECP_r(DisasContext *s, arg_incd= ec_pred *a) =20 static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3327,7 +3327,7 @@ static bool trans_INCDECP_z(DisasContext *s, arg_incd= ec2_pred *a) =20 static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3342,7 +3342,7 @@ static bool trans_SINCDECP_r_32(DisasContext *s, arg_= incdec_pred *a) =20 static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3357,7 +3357,7 @@ static bool trans_SINCDECP_r_64(DisasContext *s, arg_= incdec_pred *a) =20 static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3374,7 +3374,7 @@ static bool trans_SINCDECP_z(DisasContext *s, arg_inc= dec2_pred *a) =20 static bool trans_CTERM(DisasContext *s, arg_CTERM *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!sve_access_check(s)) { @@ -3498,9 +3498,9 @@ static bool do_WHILE(DisasContext *s, arg_while *a, return true; } =20 -TRANS_FEAT(WHILE_lt, aa64_sve, do_WHILE, +TRANS_FEAT(WHILE_lt, aa64_sme_or_sve, do_WHILE, a, true, 0, 0, gen_helper_sve_whilel) -TRANS_FEAT(WHILE_gt, aa64_sve2, do_WHILE, +TRANS_FEAT(WHILE_gt, aa64_sme_or_sve2, do_WHILE, a, false, 0, 0, gen_helper_sve_whileg) =20 TRANS_FEAT(WHILE_lt_pair, aa64_sme2_or_sve2p1, do_WHILE, @@ -3525,7 +3525,7 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) unsigned vsz =3D vec_full_reg_size(s); unsigned desc =3D 0; =20 - if (!dc_isar_feature(aa64_sve2, s)) { + if (!dc_isar_feature(aa64_sme_or_sve2, s)) { return false; } if (!sve_access_check(s)) { @@ -3618,7 +3618,7 @@ TRANS_FEAT(PEXT_2, aa64_sme2_or_sve2p1, do_pext, a, 2) =20 static bool trans_FDUP(DisasContext *s, arg_FDUP *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3635,7 +3635,7 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a) =20 static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3646,7 +3646,7 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) return true; } =20 -TRANS_FEAT(ADD_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_addi, a) +TRANS_FEAT(ADD_zzi, aa64_sme_or_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_add= i, a) =20 static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a) { @@ -3685,7 +3685,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_e= sz *a) .scalar_first =3D true } }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3697,7 +3697,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_e= sz *a) return true; } =20 -TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a) +TRANS_FEAT(MUL_zzi, aa64_sme_or_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_mul= i, a) =20 static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d) { @@ -3708,10 +3708,10 @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz= *a, bool u, bool d) return true; } =20 -TRANS_FEAT(SQADD_zzi, aa64_sve, do_zzi_sat, a, false, false) -TRANS_FEAT(UQADD_zzi, aa64_sve, do_zzi_sat, a, true, false) -TRANS_FEAT(SQSUB_zzi, aa64_sve, do_zzi_sat, a, false, true) -TRANS_FEAT(UQSUB_zzi, aa64_sve, do_zzi_sat, a, true, true) +TRANS_FEAT(SQADD_zzi, aa64_sme_or_sve, do_zzi_sat, a, false, false) +TRANS_FEAT(UQADD_zzi, aa64_sme_or_sve, do_zzi_sat, a, true, false) +TRANS_FEAT(SQSUB_zzi, aa64_sme_or_sve, do_zzi_sat, a, false, true) +TRANS_FEAT(UQSUB_zzi, aa64_sme_or_sve, do_zzi_sat, a, true, true) =20 static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i= *fn) { @@ -3729,7 +3729,7 @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *= a, gen_helper_gvec_2i *fn) gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \ gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \ }; \ - TRANS_FEAT(NAME##_zzi, aa64_sve, do_zzi_ool, a, name##i_fns[a->esz]) + TRANS_FEAT(NAME##_zzi, aa64_sme_or_sve, do_zzi_ool, a, name##i_fns[a->= esz]) =20 DO_ZZI(SMAX, smax) DO_ZZI(UMAX, umax) @@ -3742,20 +3742,20 @@ static gen_helper_gvec_4 * const dot_fns[2][2] =3D { { gen_helper_gvec_sdot_4b, gen_helper_gvec_sdot_4h }, { gen_helper_gvec_udot_4b, gen_helper_gvec_udot_4h } }; -TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz, +TRANS_FEAT(DOT_zzzz, aa64_sme_or_sve, gen_gvec_ool_zzzz, dot_fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0) =20 /* * SVE Multiply - Indexed */ =20 -TRANS_FEAT(SDOT_zzxw_4s, aa64_sve, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(SDOT_zzxw_4s, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_sdot_idx_4b, a) -TRANS_FEAT(SDOT_zzxw_4d, aa64_sve, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(SDOT_zzxw_4d, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_sdot_idx_4h, a) -TRANS_FEAT(UDOT_zzxw_4s, aa64_sve, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(UDOT_zzxw_4s, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_udot_idx_4b, a) -TRANS_FEAT(UDOT_zzxw_4d, aa64_sve, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(UDOT_zzxw_4d, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_udot_idx_4h, a) =20 TRANS_FEAT(SUDOT_zzxw_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, @@ -3769,7 +3769,7 @@ TRANS_FEAT(UDOT_zzxw_2s, aa64_sme2_or_sve2p1, gen_gve= c_ool_arg_zzxz, gen_helper_gvec_udot_idx_2h, a) =20 #define DO_SVE2_RRX(NAME, FUNC) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_zzz, FUNC, \ a->rd, a->rn, a->rm, a->index) =20 DO_SVE2_RRX(MUL_zzx_h, gen_helper_gvec_mul_idx_h) @@ -3787,7 +3787,7 @@ DO_SVE2_RRX(SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_= idx_d) #undef DO_SVE2_RRX =20 #define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_zzz, FUNC, \ a->rd, a->rn, a->rm, (a->index << 1) | TOP) =20 DO_SVE2_RRX_TB(SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false) @@ -3808,7 +3808,7 @@ DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_id= x_d, true) #undef DO_SVE2_RRX_TB =20 #define DO_SVE2_RRXR(NAME, FUNC) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a) + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_arg_zzxz, FUNC, a) =20 DO_SVE2_RRXR(MLA_zzxz_h, gen_helper_gvec_mla_idx_h) DO_SVE2_RRXR(MLA_zzxz_s, gen_helper_gvec_mla_idx_s) @@ -3829,7 +3829,7 @@ DO_SVE2_RRXR(SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmls= h_idx_d) #undef DO_SVE2_RRXR =20 #define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_zzzz, FUNC, \ a->rd, a->rn, a->rm, a->ra, (a->index << 1) | TOP) =20 DO_SVE2_RRXR_TB(SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false) @@ -3865,7 +3865,7 @@ DO_SVE2_RRXR_TB(UMLSLT_zzxw_d, gen_helper_sve2_umlsl_= idx_d, true) #undef DO_SVE2_RRXR_TB =20 #define DO_SVE2_RRXR_ROT(NAME, FUNC) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_zzzz, FUNC, \ a->rd, a->rn, a->rm, a->ra, (a->index << 2) | a->rot) =20 DO_SVE2_RRXR_ROT(CMLA_zzxz_h, gen_helper_sve2_cmla_idx_h) @@ -3898,7 +3898,7 @@ static gen_helper_gvec_4_ptr * const fmla_idx_fns[4] = =3D { gen_helper_gvec_bfmla_idx, gen_helper_gvec_fmla_idx_h, gen_helper_gvec_fmla_idx_s, gen_helper_gvec_fmla_idx_d }; -TRANS_FEAT(FMLA_zzxz, aa64_sve, do_fmla_zzxz, a, fmla_idx_fns[a->esz]) +TRANS_FEAT(FMLA_zzxz, aa64_sme_or_sve, do_fmla_zzxz, a, fmla_idx_fns[a->es= z]) =20 static gen_helper_gvec_4_ptr * const fmls_idx_fns[4][2] =3D { { gen_helper_gvec_bfmls_idx, gen_helper_gvec_ah_bfmls_idx }, @@ -3906,7 +3906,7 @@ static gen_helper_gvec_4_ptr * const fmls_idx_fns[4][= 2] =3D { { gen_helper_gvec_fmls_idx_s, gen_helper_gvec_ah_fmls_idx_s }, { gen_helper_gvec_fmls_idx_d, gen_helper_gvec_ah_fmls_idx_d }, }; -TRANS_FEAT(FMLS_zzxz, aa64_sve, do_fmla_zzxz, a, +TRANS_FEAT(FMLS_zzxz, aa64_sme_or_sve, do_fmla_zzxz, a, fmls_idx_fns[a->esz][s->fpcr_ah]) =20 /* @@ -3917,7 +3917,7 @@ static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = =3D { gen_helper_gvec_fmul_idx_b16, gen_helper_gvec_fmul_idx_h, gen_helper_gvec_fmul_idx_s, gen_helper_gvec_fmul_idx_d, }; -TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz, +TRANS_FEAT(FMUL_zzx, aa64_sme_or_sve, gen_gvec_fpst_zzz, fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 @@ -3965,7 +3965,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a, NULL, gen_helper_sve_##name##_h, \ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_reduce, a, name##_fns[a->esz]) + TRANS_FEAT(NAME, aa64_sme_or_sve, do_reduce, a, name##_fns[a->esz]) =20 #define DO_VPZ_AH(NAME, name) \ static gen_helper_fp_reduce * const name##_fns[4] =3D { = \ @@ -3976,7 +3976,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a, NULL, gen_helper_sve_ah_##name##_h, \ gen_helper_sve_ah_##name##_s, gen_helper_sve_ah_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_reduce, a, \ + TRANS_FEAT(NAME, aa64_sme_or_sve, do_reduce, a, = \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz]) =20 DO_VPZ(FADDV, faddv) @@ -4047,7 +4047,7 @@ static gen_helper_gvec_2_ptr * const frecpe_rpres_fns= [] =3D { NULL, gen_helper_gvec_frecpe_h, gen_helper_gvec_frecpe_rpres_s, gen_helper_gvec_frecpe_d, }; -TRANS_FEAT(FRECPE, aa64_sve, gen_gvec_fpst_ah_arg_zz, +TRANS_FEAT(FRECPE, aa64_sme_or_sve, gen_gvec_fpst_ah_arg_zz, s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ? frecpe_rpres_fns[a->esz] : frecpe_fns[a->esz], a, 0) =20 @@ -4059,7 +4059,7 @@ static gen_helper_gvec_2_ptr * const frsqrte_rpres_fn= s[] =3D { NULL, gen_helper_gvec_frsqrte_h, gen_helper_gvec_frsqrte_rpres_s, gen_helper_gvec_frsqrte_d, }; -TRANS_FEAT(FRSQRTE, aa64_sve, gen_gvec_fpst_ah_arg_zz, +TRANS_FEAT(FRSQRTE, aa64_sme_or_sve, gen_gvec_fpst_ah_arg_zz, s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ? frsqrte_rpres_fns[a->esz] : frsqrte_fns[a->esz], a, 0) =20 @@ -4091,7 +4091,7 @@ static bool do_ppz_fp(DisasContext *s, arg_rpr_esz *a, NULL, gen_helper_sve_##name##_h, \ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_ppz_fp, a, name##_fns[a->esz]) + TRANS_FEAT(NAME, aa64_sme_or_sve, do_ppz_fp, a, name##_fns[a->esz]) =20 DO_PPZ(FCMGE_ppz0, fcmge0) DO_PPZ(FCMGT_ppz0, fcmgt0) @@ -4164,7 +4164,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz= *a) gen_helper_gvec_##name##_b16, gen_helper_gvec_##name##_h, \ gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \ }; \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_arg_zzz, name##_fns[a->esz], = a, 0) + TRANS_FEAT(NAME, aa64_sme_or_sve, gen_gvec_fpst_arg_zzz, name##_fns[a-= >esz], a, 0) =20 #define DO_FP3_AH(NAME, name) \ static gen_helper_gvec_3_ptr * const name##_fns[4] =3D { \ @@ -4175,7 +4175,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz= *a) NULL, gen_helper_gvec_ah_##name##_h, \ gen_helper_gvec_ah_##name##_s, gen_helper_gvec_ah_##name##_d \ }; \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_ah_arg_zzz, \ + TRANS_FEAT(NAME, aa64_sme_or_sve, gen_gvec_fpst_ah_arg_zzz, \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz], a,= 0) =20 DO_FP3(FADD_zzz, fadd) @@ -4238,17 +4238,17 @@ TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_= fpst_arg_zzz, s->fpcr_ah ? name##_ah_zpzz_fns[a->esz] : \ name##_zpzz_fns[a->esz], a) =20 -DO_ZPZZ_FP_B16(FADD_zpzz, aa64_sve, sve_fadd) -DO_ZPZZ_FP_B16(FSUB_zpzz, aa64_sve, sve_fsub) -DO_ZPZZ_FP_B16(FMUL_zpzz, aa64_sve, sve_fmul) -DO_ZPZZ_AH_FP_B16(FMIN_zpzz, aa64_sve, sve_fmin, sve_ah_fmin) -DO_ZPZZ_AH_FP_B16(FMAX_zpzz, aa64_sve, sve_fmax, sve_ah_fmax) -DO_ZPZZ_FP_B16(FMINNM_zpzz, aa64_sve, sve_fminnum) -DO_ZPZZ_FP_B16(FMAXNM_zpzz, aa64_sve, sve_fmaxnum) -DO_ZPZZ_AH_FP(FABD, aa64_sve, sve_fabd, sve_ah_fabd) -DO_ZPZZ_FP(FSCALE, aa64_sve, sve_fscalbn) -DO_ZPZZ_FP(FDIV, aa64_sve, sve_fdiv) -DO_ZPZZ_FP(FMULX, aa64_sve, sve_fmulx) +DO_ZPZZ_FP_B16(FADD_zpzz, aa64_sme_or_sve, sve_fadd) +DO_ZPZZ_FP_B16(FSUB_zpzz, aa64_sme_or_sve, sve_fsub) +DO_ZPZZ_FP_B16(FMUL_zpzz, aa64_sme_or_sve, sve_fmul) +DO_ZPZZ_AH_FP_B16(FMIN_zpzz, aa64_sme_or_sve, sve_fmin, sve_ah_fmin) +DO_ZPZZ_AH_FP_B16(FMAX_zpzz, aa64_sme_or_sve, sve_fmax, sve_ah_fmax) +DO_ZPZZ_FP_B16(FMINNM_zpzz, aa64_sme_or_sve, sve_fminnum) +DO_ZPZZ_FP_B16(FMAXNM_zpzz, aa64_sme_or_sve, sve_fmaxnum) +DO_ZPZZ_AH_FP(FABD, aa64_sme_or_sve, sve_fabd, sve_ah_fabd) +DO_ZPZZ_FP(FSCALE, aa64_sme_or_sve, sve_fscalbn) +DO_ZPZZ_FP(FDIV, aa64_sme_or_sve, sve_fdiv) +DO_ZPZZ_FP(FMULX, aa64_sme_or_sve, sve_fmulx) =20 typedef void gen_helper_sve_fp2scalar(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr, TCGv_i32); @@ -4297,7 +4297,7 @@ static bool do_fp_imm(DisasContext *s, arg_rpri_esz *= a, uint64_t imm, { float32_##const0, float32_##const1 }, \ { float64_##const0, float64_##const1 }, \ }; \ - TRANS_FEAT(NAME##_zpzi, aa64_sve, do_fp_imm, a, \ + TRANS_FEAT(NAME##_zpzi, aa64_sme_or_sve, do_fp_imm, a, = \ name##_const[a->esz][a->imm], name##_fns[a->esz]) =20 #define DO_FP_AH_IMM(NAME, name, const0, const1) \ @@ -4317,7 +4317,7 @@ static bool do_fp_imm(DisasContext *s, arg_rpri_esz *= a, uint64_t imm, { float32_##const0, float32_##const1 }, \ { float64_##const0, float64_##const1 }, \ }; \ - TRANS_FEAT(NAME##_zpzi, aa64_sve, do_fp_imm, a, \ + TRANS_FEAT(NAME##_zpzi, aa64_sme_or_sve, do_fp_imm, a, = \ name##_const[a->esz][a->imm], \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz]) =20 @@ -4355,7 +4355,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *= a, NULL, gen_helper_sve_##name##_h, \ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ }; \ - TRANS_FEAT(NAME##_ppzz, aa64_sve, do_fp_cmp, a, name##_fns[a->esz]) + TRANS_FEAT(NAME##_ppzz, aa64_sme_or_sve, do_fp_cmp, a, name##_fns[a->e= sz]) =20 DO_FPCMP(FCMGE, fcmge) DO_FPCMP(FCMGT, fcmgt) @@ -4371,7 +4371,7 @@ static gen_helper_gvec_4_ptr * const fcadd_fns[] =3D { NULL, gen_helper_sve_fcadd_h, gen_helper_sve_fcadd_s, gen_helper_sve_fcadd_d, }; -TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz], +TRANS_FEAT(FCADD, aa64_sme_or_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz], a->rd, a->rn, a->rm, a->pg, a->rot | (s->fpcr_ah << 1), a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 @@ -4395,7 +4395,7 @@ static bool do_fmla_zpzzz(DisasContext *s, arg_rprrr_= esz *a, gen_helper_sve_##ah_name##_b16, gen_helper_sve_##ah_name##_h, \ gen_helper_sve_##ah_name##_s, gen_helper_sve_##ah_name##_d \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_fmla_zpzzz, a, \ + TRANS_FEAT(NAME, aa64_sme_or_sve, do_fmla_zpzzz, a, = \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz]) =20 /* We don't need an ah_fmla_zpzzz because fmla doesn't negate anything */ @@ -4410,14 +4410,14 @@ static gen_helper_gvec_5_ptr * const fcmla_fns[4] = =3D { NULL, gen_helper_sve_fcmla_zpzzz_h, gen_helper_sve_fcmla_zpzzz_s, gen_helper_sve_fcmla_zpzzz_d, }; -TRANS_FEAT(FCMLA_zpzzz, aa64_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a->esz], +TRANS_FEAT(FCMLA_zpzzz, aa64_sme_or_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a-= >esz], a->rd, a->rn, a->rm, a->ra, a->pg, a->rot | (s->fpcr_ah << 2), a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static gen_helper_gvec_4_ptr * const fcmla_idx_fns[4] =3D { NULL, gen_helper_gvec_fcmlah_idx, gen_helper_gvec_fcmlas_idx, NULL }; -TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz], +TRANS_FEAT(FCMLA_zzxz, aa64_sme_or_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[= a->esz], a->rd, a->rn, a->rm, a->ra, a->index * 4 + a->rot, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 @@ -4425,53 +4425,53 @@ TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz= , fcmla_idx_fns[a->esz], *** SVE Floating Point Unary Operations Predicated Group */ =20 -TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sh, a, 0, FPST_A64) -TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16) =20 TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 -TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_dh, a, 0, FPST_A64) -TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hd, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_ds, a, 0, FPST_A64) -TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sd, a, 0, FPST_A64) =20 -TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZU_hh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZS_hs, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hs, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZU_hs, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hs, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZS_hd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hd, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hd, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_ss, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_ss, a, 0, FPST_A64) -TRANS_FEAT(FCVTZS_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_sd, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_sd, a, 0, FPST_A64) -TRANS_FEAT(FCVTZS_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_ds, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(FCVTZS_dd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_dd, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_dd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_dd, a, 0, FPST_A64) =20 static gen_helper_gvec_3_ptr * const frint_fns[] =3D { @@ -4480,7 +4480,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[] =3D { gen_helper_sve_frint_s, gen_helper_sve_frint_d }; -TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz], +TRANS_FEAT(FRINTI, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->es= z], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static gen_helper_gvec_3_ptr * const frintx_fns[] =3D { @@ -4489,7 +4489,7 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] =3D= { gen_helper_sve_frintx_s, gen_helper_sve_frintx_d }; -TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz], +TRANS_FEAT(FRINTX, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->e= sz], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); =20 static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, @@ -4519,63 +4519,63 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_= esz *a, return true; } =20 -TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTN, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_TIEEVEN, frint_fns[a->esz]) -TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTP, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_POSINF, frint_fns[a->esz]) -TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTM, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_NEGINF, frint_fns[a->esz]) -TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTZ, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_ZERO, frint_fns[a->esz]) -TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTA, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_TIEAWAY, frint_fns[a->esz]) =20 static gen_helper_gvec_3_ptr * const frecpx_fns[] =3D { NULL, gen_helper_sve_frecpx_h, gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d, }; -TRANS_FEAT(FRECPX, aa64_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz], +TRANS_FEAT(FRECPX, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->e= sz], a, 0, select_ah_fpst(s, a->esz)) =20 static gen_helper_gvec_3_ptr * const fsqrt_fns[] =3D { NULL, gen_helper_sve_fsqrt_h, gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d, }; -TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz], +TRANS_FEAT(FSQRT, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz= ], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 -TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(SCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_sh, a, 0, FPST_A64_F16) -TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_dh, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_ss, a, 0, FPST_A64) -TRANS_FEAT(SCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(SCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_sd, a, 0, FPST_A64) -TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_dd, a, 0, FPST_A64) =20 -TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(UCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_sh, a, 0, FPST_A64_F16) -TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_dh, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_ss, a, 0, FPST_A64) -TRANS_FEAT(UCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_ds, a, 0, FPST_A64) -TRANS_FEAT(UCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_sd, a, 0, FPST_A64) =20 -TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_dd, a, 0, FPST_A64) =20 /* @@ -4803,7 +4803,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int = vofs, =20 static bool trans_LDR_zri(DisasContext *s, arg_rri *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -4817,7 +4817,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) =20 static bool trans_LDR_pri(DisasContext *s, arg_rri *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -4831,7 +4831,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) =20 static bool trans_STR_zri(DisasContext *s, arg_rri *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -4845,7 +4845,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) =20 static bool trans_STR_pri(DisasContext *s, arg_rri *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -5101,7 +5101,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_l= oad *a) /* dtypes 16-18 are artificial, representing 128-bit element */ switch (a->dtype) { case 0 ... 15: - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } break; @@ -5134,7 +5134,7 @@ static bool trans_LD_zpri(DisasContext *s, arg_rpri_l= oad *a) /* dtypes 16-18 are artificial, representing 128-bit element */ switch (a->dtype) { case 0 ... 15: - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } break; @@ -5420,7 +5420,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int dtype) =20 static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a) { - if (a->rm =3D=3D 31 || !dc_isar_feature(aa64_sve, s)) { + if (a->rm =3D=3D 31 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -5435,7 +5435,7 @@ static bool trans_LD1RQ_zprr(DisasContext *s, arg_rpr= r_load *a) =20 static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -5554,7 +5554,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri= _load *a) TCGv_i64 temp, clean_addr; MemOp memop; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!sve_access_check(s)) { @@ -5746,7 +5746,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_s= tore *a) } switch (a->esz) { case MO_8 ... MO_64: - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } break; @@ -5783,7 +5783,7 @@ static bool trans_ST_zpri(DisasContext *s, arg_rpri_s= tore *a) } switch (a->esz) { case MO_8 ... MO_64: - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } break; @@ -6525,7 +6525,7 @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1= _zprz *a) =20 static bool trans_PRF(DisasContext *s, arg_PRF *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } /* Prefetch is a nop within QEMU. */ @@ -6535,7 +6535,7 @@ static bool trans_PRF(DisasContext *s, arg_PRF *a) =20 static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a) { - if (a->rm =3D=3D 31 || !dc_isar_feature(aa64_sve, s)) { + if (a->rm =3D=3D 31 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } /* Prefetch is a nop within QEMU. */ @@ -6568,39 +6568,39 @@ static bool trans_PRF_ns(DisasContext *s, arg_PRF_n= s *a) * In the meantime, just emit the moves. */ =20 -TRANS_FEAT(MOVPRFX, aa64_sve, do_mov_z, a->rd, a->rn) -TRANS_FEAT(MOVPRFX_m, aa64_sve, do_sel_z, a->rd, a->rn, a->rd, a->pg, a->e= sz) -TRANS_FEAT(MOVPRFX_z, aa64_sve, do_movz_zpz, a->rd, a->rn, a->pg, a->esz, = false) +TRANS_FEAT(MOVPRFX, aa64_sme_or_sve, do_mov_z, a->rd, a->rn) +TRANS_FEAT(MOVPRFX_m, aa64_sme_or_sve, do_sel_z, a->rd, a->rn, a->rd, a->p= g, a->esz) +TRANS_FEAT(MOVPRFX_z, aa64_sme_or_sve, do_movz_zpz, a->rd, a->rn, a->pg, a= ->esz, false) =20 /* * SVE2 Integer Multiply - Unpredicated */ =20 -TRANS_FEAT(MUL_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mul, a) -TRANS_FEAT(SQDMULH_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_sve2_sqdm= ulh, a) +TRANS_FEAT(MUL_zzz, aa64_sme_or_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mu= l, a) +TRANS_FEAT(SQDMULH_zzz, aa64_sme_or_sve2, gen_gvec_fn_arg_zzz, gen_gvec_sv= e2_sqdmulh, a) =20 static gen_helper_gvec_3 * const smulh_zzz_fns[4] =3D { gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h, gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d, }; -TRANS_FEAT(SMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SMULH_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, smulh_zzz_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const umulh_zzz_fns[4] =3D { gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h, gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d, }; -TRANS_FEAT(UMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UMULH_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, umulh_zzz_fns[a->esz], a, 0) =20 -TRANS_FEAT(PMUL_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(PMUL_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, gen_helper_gvec_pmul_b, a, 0) =20 static gen_helper_gvec_3 * const sqrdmulh_zzz_fns[4] =3D { gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h, gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d, }; -TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQRDMULH_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqrdmulh_zzz_fns[a->esz], a, 0) =20 /* @@ -6611,66 +6611,66 @@ static gen_helper_gvec_4 * const sadlp_fns[4] =3D { NULL, gen_helper_sve2_sadalp_zpzz_h, gen_helper_sve2_sadalp_zpzz_s, gen_helper_sve2_sadalp_zpzz_d, }; -TRANS_FEAT(SADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz, +TRANS_FEAT(SADALP_zpzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzz, sadlp_fns[a->esz], a, 0) =20 static gen_helper_gvec_4 * const uadlp_fns[4] =3D { NULL, gen_helper_sve2_uadalp_zpzz_h, gen_helper_sve2_uadalp_zpzz_s, gen_helper_sve2_uadalp_zpzz_d, }; -TRANS_FEAT(UADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz, +TRANS_FEAT(UADALP_zpzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzz, uadlp_fns[a->esz], a, 0) =20 /* * SVE2 integer unary operations (predicated) */ =20 -TRANS_FEAT(URECPE, aa64_sve2, gen_gvec_ool_arg_zpz, +TRANS_FEAT(URECPE, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, a->esz =3D=3D 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0) =20 -TRANS_FEAT(URSQRTE, aa64_sve2, gen_gvec_ool_arg_zpz, +TRANS_FEAT(URSQRTE, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, a->esz =3D=3D 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0) =20 static gen_helper_gvec_3 * const sqabs_fns[4] =3D { gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h, gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d, }; -TRANS_FEAT(SQABS, aa64_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz], a, 0) +TRANS_FEAT(SQABS, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz= ], a, 0) =20 static gen_helper_gvec_3 * const sqneg_fns[4] =3D { gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h, gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d, }; -TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0) +TRANS_FEAT(SQNEG, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz= ], a, 0) =20 -DO_ZPZZ(SQSHL, aa64_sve2, sve2_sqshl) -DO_ZPZZ(SQRSHL, aa64_sve2, sve2_sqrshl) -DO_ZPZZ(SRSHL, aa64_sve2, sve2_srshl) +DO_ZPZZ(SQSHL, aa64_sme_or_sve2, sve2_sqshl) +DO_ZPZZ(SQRSHL, aa64_sme_or_sve2, sve2_sqrshl) +DO_ZPZZ(SRSHL, aa64_sme_or_sve2, sve2_srshl) =20 -DO_ZPZZ(UQSHL, aa64_sve2, sve2_uqshl) -DO_ZPZZ(UQRSHL, aa64_sve2, sve2_uqrshl) -DO_ZPZZ(URSHL, aa64_sve2, sve2_urshl) +DO_ZPZZ(UQSHL, aa64_sme_or_sve2, sve2_uqshl) +DO_ZPZZ(UQRSHL, aa64_sme_or_sve2, sve2_uqrshl) +DO_ZPZZ(URSHL, aa64_sme_or_sve2, sve2_urshl) =20 -DO_ZPZZ(SHADD, aa64_sve2, sve2_shadd) -DO_ZPZZ(SRHADD, aa64_sve2, sve2_srhadd) -DO_ZPZZ(SHSUB, aa64_sve2, sve2_shsub) +DO_ZPZZ(SHADD, aa64_sme_or_sve2, sve2_shadd) +DO_ZPZZ(SRHADD, aa64_sme_or_sve2, sve2_srhadd) +DO_ZPZZ(SHSUB, aa64_sme_or_sve2, sve2_shsub) =20 -DO_ZPZZ(UHADD, aa64_sve2, sve2_uhadd) -DO_ZPZZ(URHADD, aa64_sve2, sve2_urhadd) -DO_ZPZZ(UHSUB, aa64_sve2, sve2_uhsub) +DO_ZPZZ(UHADD, aa64_sme_or_sve2, sve2_uhadd) +DO_ZPZZ(URHADD, aa64_sme_or_sve2, sve2_urhadd) +DO_ZPZZ(UHSUB, aa64_sme_or_sve2, sve2_uhsub) =20 -DO_ZPZZ(ADDP, aa64_sve2, sve2_addp) -DO_ZPZZ(SMAXP, aa64_sve2, sve2_smaxp) -DO_ZPZZ(UMAXP, aa64_sve2, sve2_umaxp) -DO_ZPZZ(SMINP, aa64_sve2, sve2_sminp) -DO_ZPZZ(UMINP, aa64_sve2, sve2_uminp) +DO_ZPZZ(ADDP, aa64_sme_or_sve2, sve2_addp) +DO_ZPZZ(SMAXP, aa64_sme_or_sve2, sve2_smaxp) +DO_ZPZZ(UMAXP, aa64_sme_or_sve2, sve2_umaxp) +DO_ZPZZ(SMINP, aa64_sme_or_sve2, sve2_sminp) +DO_ZPZZ(UMINP, aa64_sme_or_sve2, sve2_uminp) =20 -DO_ZPZZ(SQADD_zpzz, aa64_sve2, sve2_sqadd) -DO_ZPZZ(UQADD_zpzz, aa64_sve2, sve2_uqadd) -DO_ZPZZ(SQSUB_zpzz, aa64_sve2, sve2_sqsub) -DO_ZPZZ(UQSUB_zpzz, aa64_sve2, sve2_uqsub) -DO_ZPZZ(SUQADD, aa64_sve2, sve2_suqadd) -DO_ZPZZ(USQADD, aa64_sve2, sve2_usqadd) +DO_ZPZZ(SQADD_zpzz, aa64_sme_or_sve2, sve2_sqadd) +DO_ZPZZ(UQADD_zpzz, aa64_sme_or_sve2, sve2_uqadd) +DO_ZPZZ(SQSUB_zpzz, aa64_sme_or_sve2, sve2_sqsub) +DO_ZPZZ(UQSUB_zpzz, aa64_sme_or_sve2, sve2_uqsub) +DO_ZPZZ(SUQADD, aa64_sme_or_sve2, sve2_suqadd) +DO_ZPZZ(USQADD, aa64_sme_or_sve2, sve2_usqadd) =20 /* * SVE2 Widening Integer Arithmetic @@ -6680,95 +6680,95 @@ static gen_helper_gvec_3 * const saddl_fns[4] =3D { NULL, gen_helper_sve2_saddl_h, gen_helper_sve2_saddl_s, gen_helper_sve2_saddl_d, }; -TRANS_FEAT(SADDLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SADDLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddl_fns[a->esz], a, 0) -TRANS_FEAT(SADDLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SADDLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddl_fns[a->esz], a, 3) -TRANS_FEAT(SADDLBT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SADDLBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddl_fns[a->esz], a, 2) =20 static gen_helper_gvec_3 * const ssubl_fns[4] =3D { NULL, gen_helper_sve2_ssubl_h, gen_helper_sve2_ssubl_s, gen_helper_sve2_ssubl_d, }; -TRANS_FEAT(SSUBLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SSUBLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubl_fns[a->esz], a, 0) -TRANS_FEAT(SSUBLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SSUBLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubl_fns[a->esz], a, 3) -TRANS_FEAT(SSUBLBT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SSUBLBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubl_fns[a->esz], a, 2) -TRANS_FEAT(SSUBLTB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SSUBLTB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubl_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sabdl_fns[4] =3D { NULL, gen_helper_sve2_sabdl_h, gen_helper_sve2_sabdl_s, gen_helper_sve2_sabdl_d, }; -TRANS_FEAT(SABDLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SABDLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sabdl_fns[a->esz], a, 0) -TRANS_FEAT(SABDLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SABDLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sabdl_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const uaddl_fns[4] =3D { NULL, gen_helper_sve2_uaddl_h, gen_helper_sve2_uaddl_s, gen_helper_sve2_uaddl_d, }; -TRANS_FEAT(UADDLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UADDLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uaddl_fns[a->esz], a, 0) -TRANS_FEAT(UADDLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UADDLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uaddl_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const usubl_fns[4] =3D { NULL, gen_helper_sve2_usubl_h, gen_helper_sve2_usubl_s, gen_helper_sve2_usubl_d, }; -TRANS_FEAT(USUBLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(USUBLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, usubl_fns[a->esz], a, 0) -TRANS_FEAT(USUBLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(USUBLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, usubl_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const uabdl_fns[4] =3D { NULL, gen_helper_sve2_uabdl_h, gen_helper_sve2_uabdl_s, gen_helper_sve2_uabdl_d, }; -TRANS_FEAT(UABDLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UABDLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uabdl_fns[a->esz], a, 0) -TRANS_FEAT(UABDLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UABDLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uabdl_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const sqdmull_fns[4] =3D { NULL, gen_helper_sve2_sqdmull_zzz_h, gen_helper_sve2_sqdmull_zzz_s, gen_helper_sve2_sqdmull_zzz_d, }; -TRANS_FEAT(SQDMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQDMULLB_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqdmull_fns[a->esz], a, 0) -TRANS_FEAT(SQDMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQDMULLT_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqdmull_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const smull_fns[4] =3D { NULL, gen_helper_sve2_smull_zzz_h, gen_helper_sve2_smull_zzz_s, gen_helper_sve2_smull_zzz_d, }; -TRANS_FEAT(SMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SMULLB_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, smull_fns[a->esz], a, 0) -TRANS_FEAT(SMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SMULLT_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, smull_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const umull_fns[4] =3D { NULL, gen_helper_sve2_umull_zzz_h, gen_helper_sve2_umull_zzz_s, gen_helper_sve2_umull_zzz_d, }; -TRANS_FEAT(UMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UMULLB_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, umull_fns[a->esz], a, 0) -TRANS_FEAT(UMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UMULLT_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, umull_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const eoril_fns[4] =3D { gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h, gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d, }; -TRANS_FEAT(EORBT, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 2) -TRANS_FEAT(EORTB, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 1) +TRANS_FEAT(EORBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz= ], a, 2) +TRANS_FEAT(EORTB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz= ], a, 1) =20 static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel) { @@ -6786,36 +6786,36 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr= _esz *a, bool sel) return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); } =20 -TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false) -TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true) +TRANS_FEAT(PMULLB, aa64_sme_or_sve2, do_trans_pmull, a, false) +TRANS_FEAT(PMULLT, aa64_sme_or_sve2, do_trans_pmull, a, true) =20 static gen_helper_gvec_3 * const saddw_fns[4] =3D { NULL, gen_helper_sve2_saddw_h, gen_helper_sve2_saddw_s, gen_helper_sve2_saddw_d, }; -TRANS_FEAT(SADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, = 0) -TRANS_FEAT(SADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, = 1) +TRANS_FEAT(SADDWB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->es= z], a, 0) +TRANS_FEAT(SADDWT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->es= z], a, 1) =20 static gen_helper_gvec_3 * const ssubw_fns[4] =3D { NULL, gen_helper_sve2_ssubw_h, gen_helper_sve2_ssubw_s, gen_helper_sve2_ssubw_d, }; -TRANS_FEAT(SSUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, = 0) -TRANS_FEAT(SSUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, = 1) +TRANS_FEAT(SSUBWB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->es= z], a, 0) +TRANS_FEAT(SSUBWT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->es= z], a, 1) =20 static gen_helper_gvec_3 * const uaddw_fns[4] =3D { NULL, gen_helper_sve2_uaddw_h, gen_helper_sve2_uaddw_s, gen_helper_sve2_uaddw_d, }; -TRANS_FEAT(UADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, = 0) -TRANS_FEAT(UADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, = 1) +TRANS_FEAT(UADDWB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->es= z], a, 0) +TRANS_FEAT(UADDWT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->es= z], a, 1) =20 static gen_helper_gvec_3 * const usubw_fns[4] =3D { NULL, gen_helper_sve2_usubw_h, gen_helper_sve2_usubw_s, gen_helper_sve2_usubw_d, }; -TRANS_FEAT(USUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, = 0) -TRANS_FEAT(USUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, = 1) +TRANS_FEAT(USUBWB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->es= z], a, 0) +TRANS_FEAT(USUBWT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->es= z], a, 1) =20 static void gen_sshll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t i= mm) { @@ -6935,8 +6935,8 @@ static const GVecGen2i sshll_ops[3] =3D { .fno =3D gen_helper_sve2_sshll_d, .vece =3D MO_64 } }; -TRANS_FEAT(SSHLLB, aa64_sve2, do_shll_tb, a, sshll_ops, false) -TRANS_FEAT(SSHLLT, aa64_sve2, do_shll_tb, a, sshll_ops, true) +TRANS_FEAT(SSHLLB, aa64_sme_or_sve2, do_shll_tb, a, sshll_ops, false) +TRANS_FEAT(SSHLLT, aa64_sme_or_sve2, do_shll_tb, a, sshll_ops, true) =20 static const TCGOpcode ushll_list[] =3D { INDEX_op_shli_vec, INDEX_op_shri_vec, 0 @@ -6958,8 +6958,8 @@ static const GVecGen2i ushll_ops[3] =3D { .fno =3D gen_helper_sve2_ushll_d, .vece =3D MO_64 }, }; -TRANS_FEAT(USHLLB, aa64_sve2, do_shll_tb, a, ushll_ops, false) -TRANS_FEAT(USHLLT, aa64_sve2, do_shll_tb, a, ushll_ops, true) +TRANS_FEAT(USHLLB, aa64_sme_or_sve2, do_shll_tb, a, ushll_ops, false) +TRANS_FEAT(USHLLT, aa64_sme_or_sve2, do_shll_tb, a, ushll_ops, true) =20 static gen_helper_gvec_3 * const bext_fns[4] =3D { gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, @@ -6986,33 +6986,33 @@ static gen_helper_gvec_3 * const cadd_fns[4] =3D { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d, }; -TRANS_FEAT(CADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(CADD_rot90, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, cadd_fns[a->esz], a, 0) -TRANS_FEAT(CADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(CADD_rot270, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, cadd_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sqcadd_fns[4] =3D { gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h, gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d, }; -TRANS_FEAT(SQCADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQCADD_rot90, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqcadd_fns[a->esz], a, 0) -TRANS_FEAT(SQCADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQCADD_rot270, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqcadd_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const sabal_fns[4] =3D { NULL, gen_helper_sve2_sabal_h, gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d, }; -TRANS_FEAT(SABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a,= 0) -TRANS_FEAT(SABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a,= 1) +TRANS_FEAT(SABALB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->e= sz], a, 0) +TRANS_FEAT(SABALT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->e= sz], a, 1) =20 static gen_helper_gvec_4 * const uabal_fns[4] =3D { NULL, gen_helper_sve2_uabal_h, gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d, }; -TRANS_FEAT(UABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a,= 0) -TRANS_FEAT(UABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a,= 1) +TRANS_FEAT(UABALB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->e= sz], a, 0) +TRANS_FEAT(UABALT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->e= sz], a, 1) =20 static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel) { @@ -7027,18 +7027,18 @@ static bool do_adcl(DisasContext *s, arg_rrrr_esz *= a, bool sel) return gen_gvec_ool_arg_zzzz(s, fns[a->esz & 1], a, (a->esz & 2) | sel= ); } =20 -TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false) -TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true) +TRANS_FEAT(ADCLB, aa64_sme_or_sve2, do_adcl, a, false) +TRANS_FEAT(ADCLT, aa64_sme_or_sve2, do_adcl, a, true) =20 -TRANS_FEAT(SSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ssra, a) -TRANS_FEAT(USRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_usra, a) -TRANS_FEAT(SRSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_srsra, a) -TRANS_FEAT(URSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ursra, a) -TRANS_FEAT(SRI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sri, a) -TRANS_FEAT(SLI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sli, a) +TRANS_FEAT(SSRA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ssra, a) +TRANS_FEAT(USRA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_usra, a) +TRANS_FEAT(SRSRA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_srsra, a) +TRANS_FEAT(URSRA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ursra, a) +TRANS_FEAT(SRI, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sri, a) +TRANS_FEAT(SLI, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sli, a) =20 -TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a) -TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a) +TRANS_FEAT(SABA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a) +TRANS_FEAT(UABA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a) =20 static bool do_narrow_extract(DisasContext *s, arg_rri_esz *a, const GVecGen2 ops[3]) @@ -7085,7 +7085,7 @@ static const GVecGen2 sqxtnb_ops[3] =3D { .fno =3D gen_helper_sve2_sqxtnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQXTNB, aa64_sve2, do_narrow_extract, a, sqxtnb_ops) +TRANS_FEAT(SQXTNB, aa64_sme_or_sve2, do_narrow_extract, a, sqxtnb_ops) =20 static void gen_sqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { @@ -7117,7 +7117,7 @@ static const GVecGen2 sqxtnt_ops[3] =3D { .fno =3D gen_helper_sve2_sqxtnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQXTNT, aa64_sve2, do_narrow_extract, a, sqxtnt_ops) +TRANS_FEAT(SQXTNT, aa64_sme_or_sve2, do_narrow_extract, a, sqxtnt_ops) =20 static const TCGOpcode uqxtn_list[] =3D { INDEX_op_shli_vec, INDEX_op_umin_vec, 0 @@ -7145,7 +7145,7 @@ static const GVecGen2 uqxtnb_ops[3] =3D { .fno =3D gen_helper_sve2_uqxtnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(UQXTNB, aa64_sve2, do_narrow_extract, a, uqxtnb_ops) +TRANS_FEAT(UQXTNB, aa64_sme_or_sve2, do_narrow_extract, a, uqxtnb_ops) =20 static void gen_uqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { @@ -7175,7 +7175,7 @@ static const GVecGen2 uqxtnt_ops[3] =3D { .fno =3D gen_helper_sve2_uqxtnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(UQXTNT, aa64_sve2, do_narrow_extract, a, uqxtnt_ops) +TRANS_FEAT(UQXTNT, aa64_sme_or_sve2, do_narrow_extract, a, uqxtnt_ops) =20 static const TCGOpcode sqxtun_list[] =3D { INDEX_op_shli_vec, INDEX_op_umin_vec, INDEX_op_smax_vec, 0 @@ -7204,7 +7204,7 @@ static const GVecGen2 sqxtunb_ops[3] =3D { .fno =3D gen_helper_sve2_sqxtunb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQXTUNB, aa64_sve2, do_narrow_extract, a, sqxtunb_ops) +TRANS_FEAT(SQXTUNB, aa64_sme_or_sve2, do_narrow_extract, a, sqxtunb_ops) =20 static void gen_sqxtunt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { @@ -7235,7 +7235,7 @@ static const GVecGen2 sqxtunt_ops[3] =3D { .fno =3D gen_helper_sve2_sqxtunt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQXTUNT, aa64_sve2, do_narrow_extract, a, sqxtunt_ops) +TRANS_FEAT(SQXTUNT, aa64_sme_or_sve2, do_narrow_extract, a, sqxtunt_ops) =20 static bool do_shr_narrow(DisasContext *s, arg_rri_esz *a, const GVecGen2i ops[3]) @@ -7304,7 +7304,7 @@ static const GVecGen2i shrnb_ops[3] =3D { .fno =3D gen_helper_sve2_shrnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SHRNB, aa64_sve2, do_shr_narrow, a, shrnb_ops) +TRANS_FEAT(SHRNB, aa64_sme_or_sve2, do_shr_narrow, a, shrnb_ops) =20 static void gen_shrnt_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr) { @@ -7363,21 +7363,21 @@ static const GVecGen2i shrnt_ops[3] =3D { .fno =3D gen_helper_sve2_shrnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SHRNT, aa64_sve2, do_shr_narrow, a, shrnt_ops) +TRANS_FEAT(SHRNT, aa64_sme_or_sve2, do_shr_narrow, a, shrnt_ops) =20 static const GVecGen2i rshrnb_ops[3] =3D { { .fno =3D gen_helper_sve2_rshrnb_h }, { .fno =3D gen_helper_sve2_rshrnb_s }, { .fno =3D gen_helper_sve2_rshrnb_d }, }; -TRANS_FEAT(RSHRNB, aa64_sve2, do_shr_narrow, a, rshrnb_ops) +TRANS_FEAT(RSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, rshrnb_ops) =20 static const GVecGen2i rshrnt_ops[3] =3D { { .fno =3D gen_helper_sve2_rshrnt_h }, { .fno =3D gen_helper_sve2_rshrnt_s }, { .fno =3D gen_helper_sve2_rshrnt_d }, }; -TRANS_FEAT(RSHRNT, aa64_sve2, do_shr_narrow, a, rshrnt_ops) +TRANS_FEAT(RSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, rshrnt_ops) =20 static void gen_sqshrunb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7407,7 +7407,7 @@ static const GVecGen2i sqshrunb_ops[3] =3D { .fno =3D gen_helper_sve2_sqshrunb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQSHRUNB, aa64_sve2, do_shr_narrow, a, sqshrunb_ops) +TRANS_FEAT(SQSHRUNB, aa64_sme_or_sve2, do_shr_narrow, a, sqshrunb_ops) =20 static void gen_sqshrunt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7444,21 +7444,21 @@ static const GVecGen2i sqshrunt_ops[3] =3D { .fno =3D gen_helper_sve2_sqshrunt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQSHRUNT, aa64_sve2, do_shr_narrow, a, sqshrunt_ops) +TRANS_FEAT(SQSHRUNT, aa64_sme_or_sve2, do_shr_narrow, a, sqshrunt_ops) =20 static const GVecGen2i sqrshrunb_ops[3] =3D { { .fno =3D gen_helper_sve2_sqrshrunb_h }, { .fno =3D gen_helper_sve2_sqrshrunb_s }, { .fno =3D gen_helper_sve2_sqrshrunb_d }, }; -TRANS_FEAT(SQRSHRUNB, aa64_sve2, do_shr_narrow, a, sqrshrunb_ops) +TRANS_FEAT(SQRSHRUNB, aa64_sme_or_sve2, do_shr_narrow, a, sqrshrunb_ops) =20 static const GVecGen2i sqrshrunt_ops[3] =3D { { .fno =3D gen_helper_sve2_sqrshrunt_h }, { .fno =3D gen_helper_sve2_sqrshrunt_s }, { .fno =3D gen_helper_sve2_sqrshrunt_d }, }; -TRANS_FEAT(SQRSHRUNT, aa64_sve2, do_shr_narrow, a, sqrshrunt_ops) +TRANS_FEAT(SQRSHRUNT, aa64_sme_or_sve2, do_shr_narrow, a, sqrshrunt_ops) =20 static void gen_sqshrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7491,7 +7491,7 @@ static const GVecGen2i sqshrnb_ops[3] =3D { .fno =3D gen_helper_sve2_sqshrnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQSHRNB, aa64_sve2, do_shr_narrow, a, sqshrnb_ops) +TRANS_FEAT(SQSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, sqshrnb_ops) =20 static void gen_sqshrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7529,21 +7529,21 @@ static const GVecGen2i sqshrnt_ops[3] =3D { .fno =3D gen_helper_sve2_sqshrnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQSHRNT, aa64_sve2, do_shr_narrow, a, sqshrnt_ops) +TRANS_FEAT(SQSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, sqshrnt_ops) =20 static const GVecGen2i sqrshrnb_ops[3] =3D { { .fno =3D gen_helper_sve2_sqrshrnb_h }, { .fno =3D gen_helper_sve2_sqrshrnb_s }, { .fno =3D gen_helper_sve2_sqrshrnb_d }, }; -TRANS_FEAT(SQRSHRNB, aa64_sve2, do_shr_narrow, a, sqrshrnb_ops) +TRANS_FEAT(SQRSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, sqrshrnb_ops) =20 static const GVecGen2i sqrshrnt_ops[3] =3D { { .fno =3D gen_helper_sve2_sqrshrnt_h }, { .fno =3D gen_helper_sve2_sqrshrnt_s }, { .fno =3D gen_helper_sve2_sqrshrnt_d }, }; -TRANS_FEAT(SQRSHRNT, aa64_sve2, do_shr_narrow, a, sqrshrnt_ops) +TRANS_FEAT(SQRSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, sqrshrnt_ops) =20 static void gen_uqshrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7572,7 +7572,7 @@ static const GVecGen2i uqshrnb_ops[3] =3D { .fno =3D gen_helper_sve2_uqshrnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(UQSHRNB, aa64_sve2, do_shr_narrow, a, uqshrnb_ops) +TRANS_FEAT(UQSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, uqshrnb_ops) =20 static void gen_uqshrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7607,28 +7607,28 @@ static const GVecGen2i uqshrnt_ops[3] =3D { .fno =3D gen_helper_sve2_uqshrnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(UQSHRNT, aa64_sve2, do_shr_narrow, a, uqshrnt_ops) +TRANS_FEAT(UQSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, uqshrnt_ops) =20 static const GVecGen2i uqrshrnb_ops[3] =3D { { .fno =3D gen_helper_sve2_uqrshrnb_h }, { .fno =3D gen_helper_sve2_uqrshrnb_s }, { .fno =3D gen_helper_sve2_uqrshrnb_d }, }; -TRANS_FEAT(UQRSHRNB, aa64_sve2, do_shr_narrow, a, uqrshrnb_ops) +TRANS_FEAT(UQRSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, uqrshrnb_ops) =20 static const GVecGen2i uqrshrnt_ops[3] =3D { { .fno =3D gen_helper_sve2_uqrshrnt_h }, { .fno =3D gen_helper_sve2_uqrshrnt_s }, { .fno =3D gen_helper_sve2_uqrshrnt_d }, }; -TRANS_FEAT(UQRSHRNT, aa64_sve2, do_shr_narrow, a, uqrshrnt_ops) +TRANS_FEAT(UQRSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, uqrshrnt_ops) =20 #define DO_SVE2_ZZZ_NARROW(NAME, name) \ static gen_helper_gvec_3 * const name##_fns[4] =3D { = \ NULL, gen_helper_sve2_##name##_h, \ gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzz, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, = \ name##_fns[a->esz], a, 0) =20 DO_SVE2_ZZZ_NARROW(ADDHNB, addhnb) @@ -7660,11 +7660,11 @@ TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gve= c_ool_arg_zpzz, TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, a->esz =3D=3D 0 ? gen_helper_sve2_histseg : NULL, = a, 0) =20 -DO_ZPZZ_FP(FADDP, aa64_sve2, sve2_faddp_zpzz) -DO_ZPZZ_FP(FMAXNMP, aa64_sve2, sve2_fmaxnmp_zpzz) -DO_ZPZZ_FP(FMINNMP, aa64_sve2, sve2_fminnmp_zpzz) -DO_ZPZZ_FP(FMAXP, aa64_sve2, sve2_fmaxp_zpzz) -DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz) +DO_ZPZZ_FP(FADDP, aa64_sme_or_sve2, sve2_faddp_zpzz) +DO_ZPZZ_FP(FMAXNMP, aa64_sme_or_sve2, sve2_fmaxnmp_zpzz) +DO_ZPZZ_FP(FMINNMP, aa64_sme_or_sve2, sve2_fminnmp_zpzz) +DO_ZPZZ_FP(FMAXP, aa64_sme_or_sve2, sve2_fmaxp_zpzz) +DO_ZPZZ_FP(FMINP, aa64_sme_or_sve2, sve2_fminp_zpzz) =20 static bool do_fmmla(DisasContext *s, arg_rrrr_esz *a, gen_helper_gvec_4_ptr *fn) @@ -7690,92 +7690,92 @@ static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[]= =3D { NULL, gen_helper_sve2_sqdmlal_zzzw_h, gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d, }; -TRANS_FEAT(SQDMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLALB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlal_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(SQDMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLALT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlal_zzzw_fns[a->esz], a, 3) -TRANS_FEAT(SQDMLALBT, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLALBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlal_zzzw_fns[a->esz], a, 2) =20 static gen_helper_gvec_4 * const sqdmlsl_zzzw_fns[] =3D { NULL, gen_helper_sve2_sqdmlsl_zzzw_h, gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d, }; -TRANS_FEAT(SQDMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLSLB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlsl_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(SQDMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLSLT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlsl_zzzw_fns[a->esz], a, 3) -TRANS_FEAT(SQDMLSLBT, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLSLBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlsl_zzzw_fns[a->esz], a, 2) =20 static gen_helper_gvec_4 * const sqrdmlah_fns[] =3D { gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h, gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d, }; -TRANS_FEAT(SQRDMLAH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQRDMLAH_zzzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqrdmlah_fns[a->esz], a, 0) =20 static gen_helper_gvec_4 * const sqrdmlsh_fns[] =3D { gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h, gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d, }; -TRANS_FEAT(SQRDMLSH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQRDMLSH_zzzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqrdmlsh_fns[a->esz], a, 0) =20 static gen_helper_gvec_4 * const smlal_zzzw_fns[] =3D { NULL, gen_helper_sve2_smlal_zzzw_h, gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d, }; -TRANS_FEAT(SMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SMLALB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, smlal_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(SMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SMLALT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, smlal_zzzw_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const umlal_zzzw_fns[] =3D { NULL, gen_helper_sve2_umlal_zzzw_h, gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d, }; -TRANS_FEAT(UMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(UMLALB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, umlal_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(UMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(UMLALT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, umlal_zzzw_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const smlsl_zzzw_fns[] =3D { NULL, gen_helper_sve2_smlsl_zzzw_h, gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d, }; -TRANS_FEAT(SMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SMLSLB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, smlsl_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(SMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SMLSLT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, smlsl_zzzw_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const umlsl_zzzw_fns[] =3D { NULL, gen_helper_sve2_umlsl_zzzw_h, gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d, }; -TRANS_FEAT(UMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(UMLSLB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, umlsl_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(UMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(UMLSLT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, umlsl_zzzw_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const cmla_fns[] =3D { gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h, gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d, }; -TRANS_FEAT(CMLA_zzzz, aa64_sve2, gen_gvec_ool_zzzz, +TRANS_FEAT(CMLA_zzzz, aa64_sme_or_sve2, gen_gvec_ool_zzzz, cmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) =20 static gen_helper_gvec_4 * const cdot_fns[] =3D { NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d }; -TRANS_FEAT(CDOT_zzzz, aa64_sve2, gen_gvec_ool_zzzz, +TRANS_FEAT(CDOT_zzzz, aa64_sme_or_sve2, gen_gvec_ool_zzzz, cdot_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) =20 static gen_helper_gvec_4 * const sqrdcmlah_fns[] =3D { gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h, gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d, }; -TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz, +TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sme_or_sve2, gen_gvec_ool_zzzz, sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) =20 TRANS_FEAT(USDOT_zzzz_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, @@ -7813,30 +7813,30 @@ static bool trans_RAX1(DisasContext *s, arg_RAX1 *a) return gen_gvec_fn_arg_zzz(s, gen_gvec_rax1, a); } =20 -TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTNT_sh, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) -TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTNT_ds, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64) =20 TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvtnt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 -TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTLT_hs, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64) -TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTLT_sd, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64) =20 -TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a, +TRANS_FEAT(FCVTX_ds, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, gen_helper_sve_fcvt_ds) -TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a, +TRANS_FEAT(FCVTXNT_ds, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds) =20 static gen_helper_gvec_3_ptr * const flogb_fns[] =3D { NULL, gen_helper_flogb_h, gen_helper_flogb_s, gen_helper_flogb_d }; -TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz], +TRANS_FEAT(FLOGB, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->es= z], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool= sel) @@ -7846,10 +7846,10 @@ static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr= _esz *a, bool sub, bool sel) (sel << 1) | sub, tcg_env); } =20 -TRANS_FEAT(FMLALB_zzzw, aa64_sve2, do_FMLAL_zzzw, a, false, false) -TRANS_FEAT(FMLALT_zzzw, aa64_sve2, do_FMLAL_zzzw, a, false, true) -TRANS_FEAT(FMLSLB_zzzw, aa64_sve2, do_FMLAL_zzzw, a, true, false) -TRANS_FEAT(FMLSLT_zzzw, aa64_sve2, do_FMLAL_zzzw, a, true, true) +TRANS_FEAT(FMLALB_zzzw, aa64_sme_or_sve2, do_FMLAL_zzzw, a, false, false) +TRANS_FEAT(FMLALT_zzzw, aa64_sme_or_sve2, do_FMLAL_zzzw, a, false, true) +TRANS_FEAT(FMLSLB_zzzw, aa64_sme_or_sve2, do_FMLAL_zzzw, a, true, false) +TRANS_FEAT(FMLSLT_zzzw, aa64_sme_or_sve2, do_FMLAL_zzzw, a, true, true) =20 static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool= sel) { @@ -7858,10 +7858,10 @@ static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr= _esz *a, bool sub, bool sel) (a->index << 3) | (sel << 1) | sub, tcg_env); } =20 -TRANS_FEAT(FMLALB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, false) -TRANS_FEAT(FMLALT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, true) -TRANS_FEAT(FMLSLB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, false) -TRANS_FEAT(FMLSLT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, true) +TRANS_FEAT(FMLALB_zzxw, aa64_sme_or_sve2, do_FMLAL_zzxw, a, false, false) +TRANS_FEAT(FMLALT_zzxw, aa64_sme_or_sve2, do_FMLAL_zzxw, a, false, true) +TRANS_FEAT(FMLSLB_zzxw, aa64_sme_or_sve2, do_FMLAL_zzxw, a, true, false) +TRANS_FEAT(FMLSLT_zzxw, aa64_sme_or_sve2, do_FMLAL_zzxw, a, true, true) =20 TRANS_FEAT_NONSTREAMING(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, gen_helper_gvec_smmla_b, a, 0) --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039437; cv=none; d=zohomail.com; s=zohoarc; b=iD9YgwVPKWKFFsvVbUBbYtakk+//ya7AedtC5Bw1ULgmHeZi9pQxLRVP7iTQ30Ox7u2AuIb4wej8WYFEsn2VAP5yG/15zqqWiSEO2/QOOiQnr8lDmNE0jmIYdGZOHn9bLbW35SZKQDiF0d+Erglm4jmtNbh22cEtHdosim6vdeg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039437; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1D5gDxMSdzziaFg9/E0uX86KkUPhS7bg4mwduipKGMc=; b=F9lu72pBb4yNHXJZVJbNwRqQBx5IGpDos6hg1opDif6k5U8jSraWy5lUM5GBhQ0R+MQ4iZ5/DTL2JEfB815gugh3srTUFa9sCPpdXyFqdoTi0hVNqRW42tB2e2oETP6fBnjzbLZz71G8O88NYaUFzfzbYY/Z7JepRsi6/5yhIBY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039437818918.5962988839098; Mon, 2 Feb 2026 05:37:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu4K-0007Em-Ba; Mon, 02 Feb 2026 08:34:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu4F-00075t-LW for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:15 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu4A-0002hL-2r for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:15 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4806ce0f97bso38006445e9.0 for ; Mon, 02 Feb 2026 05:34:09 -0800 (PST) Received: from lanath.. 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Currently we assume that it is only set for FEAT_SVE. Update the feature checks: * we rename the existing feature check function to sve_sme_i8mm to indicate that it is true for either SVE or SME I8MM * we add a new check function for FEAT_SVE && FEAT_I8MM (giving it the sve_i8mm name that the old function used to have) * the instructions which are (SVE || SME) && I8MM need their checks updating to sve_sme_i8mm: these are SUDOT, USDOT * instructions which are SVE && I8MM (i.e. really SVE-only) stay unchanged with sve_i8mm: these are SMMLA, USMMLA, UMMLA Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 8 +++++++- target/arm/tcg/translate-sve.c | 6 +++--- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 40393d88f0..8b8de5db04 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1449,7 +1449,8 @@ static inline bool isar_feature_aa64_sve2_sm4(const A= RMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) !=3D 0; } =20 -static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) +/* Note that this is true if either SVE or SME are implemented with I8MM */ +static inline bool isar_feature_aa64_sme_sve_i8mm(const ARMISARegisters *i= d) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, I8MM) !=3D 0; } @@ -1542,6 +1543,11 @@ static inline bool isar_feature_aa64_sme2_f64f64(con= st ARMISARegisters *id) return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_f64f64(id); } =20 +static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) +{ + return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 44eda7b07d..53d35f6de9 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3758,9 +3758,9 @@ TRANS_FEAT(UDOT_zzxw_4s, aa64_sme_or_sve, gen_gvec_oo= l_arg_zzxz, TRANS_FEAT(UDOT_zzxw_4d, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_udot_idx_4h, a) =20 -TRANS_FEAT(SUDOT_zzxw_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(SUDOT_zzxw_4s, aa64_sme_sve_i8mm, gen_gvec_ool_arg_zzxz, gen_helper_gvec_sudot_idx_4b, a) -TRANS_FEAT(USDOT_zzxw_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(USDOT_zzxw_4s, aa64_sme_sve_i8mm, gen_gvec_ool_arg_zzxz, gen_helper_gvec_usdot_idx_4b, a) =20 TRANS_FEAT(SDOT_zzxw_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzxz, @@ -7778,7 +7778,7 @@ static gen_helper_gvec_4 * const sqrdcmlah_fns[] =3D { TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sme_or_sve2, gen_gvec_ool_zzzz, sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) =20 -TRANS_FEAT(USDOT_zzzz_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(USDOT_zzzz_4s, aa64_sme_sve_i8mm, gen_gvec_ool_arg_zzzz, gen_helper_gvec_usdot_4b, a, 0) =20 TRANS_FEAT(SDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzzz, --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c42895sm478054495e9.14.2026.02.02.05.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 05:34:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770039250; x=1770644050; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wb6+lM6pydrnwcLmZGcqj6kVPeiLe8pR1QP6em9mlF8=; b=AOpyN+Zjk9hvyRhDUJnmafdGsxWmvSsAdEdQCoXr1Fwgza6Oo0Xpbw7R/is1khmfUO UGb5pF5YAa8ewYEUymZeS6ySkmD+UBfZAEhXGiDu2BciheqOtKK0DlrOkCnZMmaAjcxz YCttxf1nw6ssg+9TsCgzB3GuLSM9caTxacTiasDJLgd0/LT7WPakV4H6A191rRF92gVa BRnshXaaWXIKtA2kXsKDogLNhgV9sgtZSBPUn04zxkOn2fn65Dr2QWebfQVS8bl1y1F4 ywyyrhIr9JXQe3N9MtFxHFyVlqRuHroxVzvSGRS4Z6rPeuLCDdXazDddHX5PZymys/my feGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770039250; x=1770644050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wb6+lM6pydrnwcLmZGcqj6kVPeiLe8pR1QP6em9mlF8=; b=cXy5cDmkR9cR64EpiQYR/8UFX3J3BiBKl2ebGctoePo44dYBXOIRfaxpj42KpIQUOe ga8SkkfCk1I9qP41mKs9tS20HEA1LZS3SqMjI7+YHk1wmiENRbKGByZBMaoJl0F0kzio F98JjZPKZyu3kgtZDRMMO5vVk27QFxYtd/pk6HV+3DF1bvKEzrOZL3qioH19CqYahK3c as8dA3PIxj1YcAn0Q9jfKhLn77HDcl8Kf/7s54pyDMV3io+OQ5AulkPisD8ZC0YVswXo H0nx1chOHfHipBB0tyN/W/pIXlvQQA1yuxUiI90jqpH5yDddqQfKUfDcEjn6/RpMQm3b clIQ== X-Forwarded-Encrypted: i=1; AJvYcCXScmjbbb0gFroPS5YFrc2f4Sew0n6cu9uHWeoMY8WJeWSqRMvpytwoYWD+2w31kuvfCIh6hvwofYJW@nongnu.org X-Gm-Message-State: AOJu0Yx11J+4LtxjbZCtUGn1Sd7NL+f2H0OvftZE4aIMhHBEXhKL7P+f R/AmnzYLZeOQrYncb1VB1dEz+YzlwVJDD8kpJycOtSTWAK5Icmjb0+nihONO96SCCF4= X-Gm-Gg: AZuq6aIet1+V9oXwSVdypZEPygVvEphSkqOqgOvzjZB2440rs5W7dlt0mCBIcgP59kP rF7XxJjWBFJIvOff3MMHSIcvydFfUF9L197q5Dwn6eK6Ia1e7YiPoZuDtRFHU4KNftXi6boA40c zYNKY8WdHI0EI7vnFm3YQg8pqqsQcu6qU1YqGQiGF5u8SRTAK0iD2UyNls+suCg/AZG/6rayC5O jTQQmAMCoq+6PnxzkT7t0YeA5DmXU+WyXULcxbkt42hPx+E3r0/ma5H9lrzy5Hl/7V+Q6nBlLfL 4zq2Av7W4u2+8En6ctYq/HMi4dQTmFcenBJn7agJD2NvmoDISvZZpT6Ut6MR5hujSiw3jt/nNyL xvxuD64MrWKtP/ZLHtJCn5RaXxc5QyRNbMyuHbwruageIxlx/jXamUCB/G4FT+HaJilNmLbRW3i 2E/t/M08jsFzWannldtse9E75Exfx1og== X-Received: by 2002:a05:600c:19cc:b0:480:690e:f14a with SMTP id 5b1f17b1804b1-482db4563b7mr156150385e9.14.1770039249839; Mon, 02 Feb 2026 05:34:09 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , Manos Pitsidianakis , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v3 12/15] target/arm/tcg: Correct SVE/SME BF16 checks Date: Mon, 2 Feb 2026 13:33:50 +0000 Message-ID: <20260202133353.2231685-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260202133353.2231685-1-peter.maydell@linaro.org> References: <20260202133353.2231685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770039273756158500 Content-Type: text/plain; charset="utf-8" As with I8MM, the BF16 field of ID_AA64ZFR0_EL1 is set when the CPU implements FEAT_BF16 and either FEAT_SVE or FEAT_SME, so we need to have separate checks for "(SVE || SME) && BF16" and "SVE && BF16". Follow the same pattern as with I8MM: * aa64_sve_sme_bf16 means (SVE || SME) && BF16 * aa64_sve_bf16 means (SVE && BF16) BFMMLA is the only SVE BF16 insn that isn't in SME. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 7 ++++++- target/arm/tcg/translate-sve.c | 16 ++++++++-------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 8b8de5db04..1bcf28ab08 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1434,7 +1434,7 @@ static inline bool isar_feature_aa64_sve2_bitperm(con= st ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) !=3D 0; } =20 -static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) +static inline bool isar_feature_aa64_sme_sve_bf16(const ARMISARegisters *i= d) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) !=3D 0; } @@ -1548,6 +1548,11 @@ static inline bool isar_feature_aa64_sve_i8mm(const = ARMISARegisters *id) return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id); } =20 +static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) +{ + return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_bf16(id); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 53d35f6de9..956ddee123 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4430,7 +4430,7 @@ TRANS_FEAT(FCVT_sh, aa64_sme_or_sve, gen_gvec_fpst_ar= g_zpz, TRANS_FEAT(FCVT_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(BFCVT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 @@ -7818,7 +7818,7 @@ TRANS_FEAT(FCVTNT_sh, aa64_sme_or_sve2, gen_gvec_fpst= _arg_zpz, TRANS_FEAT(FCVTNT_ds, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(BFCVTNT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvtnt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 @@ -7875,9 +7875,9 @@ TRANS_FEAT(FDOT_zzzz, aa64_sme2_or_sve2p1, gen_gvec_e= nv_arg_zzzz, TRANS_FEAT(FDOT_zzxz, aa64_sme2_or_sve2p1, gen_gvec_env_arg_zzxz, gen_helper_sme2_fdot_idx_h, a) =20 -TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_env_arg_zzzz, +TRANS_FEAT(BFDOT_zzzz, aa64_sme_sve_bf16, gen_gvec_env_arg_zzzz, gen_helper_gvec_bfdot, a, 0) -TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_env_arg_zzxz, +TRANS_FEAT(BFDOT_zzxz, aa64_sme_sve_bf16, gen_gvec_env_arg_zzxz, gen_helper_gvec_bfdot_idx, a) =20 TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_env_arg_zzzz, @@ -7890,8 +7890,8 @@ static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_= esz *a, bool sel) s->fpcr_ah ? FPST_AH : FPST_A64); } =20 -TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false) -TRANS_FEAT(BFMLALT_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, true) +TRANS_FEAT(BFMLALB_zzzw, aa64_sme_sve_bf16, do_BFMLAL_zzzw, a, false) +TRANS_FEAT(BFMLALT_zzzw, aa64_sme_sve_bf16, do_BFMLAL_zzzw, a, true) =20 static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) { @@ -7901,8 +7901,8 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_= esz *a, bool sel) s->fpcr_ah ? FPST_AH : FPST_A64); } =20 -TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) -TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) +TRANS_FEAT(BFMLALB_zzxw, aa64_sme_sve_bf16, do_BFMLAL_zzxw, a, false) +TRANS_FEAT(BFMLALT_zzxw, aa64_sme_sve_bf16, do_BFMLAL_zzxw, a, true) =20 static bool do_BFMLSL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) { --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039378; cv=none; d=zohomail.com; s=zohoarc; b=mvZFVwkpNPC64u63xTwyJlDCTyd5aSHGXqzGXFxeee6Uv0UMbM8tOJLOISNMj8w+QL1kLxyC9h8DTfTPJHNOVmkAyRTXIqTpIMWORoBnSPpFkbiLypsF5oe7GNvu4YxmcOLzboqubdJG0Of5YxpaWyXYjb4YVDGRPLdj8K1Rjes= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039378; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=U7/A50zC5y9dv4obdxsbQJJ3KmtCSDayPVIoHJnHYD0=; b=nF0jy9kjMEyCUtxpGNjQQ118ddXyECHxlsF40nCbNrk8dxy/tB+RYuMkbzPGA3mtg7j823LzWT3dL68YQ5j3dD58v8SqPgfpjSPQFLJfZT2wl2r2Ic6qcbwtudXT10CVgvZeRTUAO02jzFqBJ+wjb14H+2zgVaEA2WX3gOEpQDA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17700393788121014.2506115141051; Mon, 2 Feb 2026 05:36:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu4L-0007I6-OX; Mon, 02 Feb 2026 08:34:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu4G-00076v-SG for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:17 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu4C-0002hq-M1 for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:16 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-47ff94b46afso40858685e9.1 for ; Mon, 02 Feb 2026 05:34:12 -0800 (PST) Received: from lanath.. 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Only clear the fields which are SVE-specific here, and clear the rest in arm_cpu_sme_finalize() if we have neither SME nor SVE. This requires us to update our ID_AA64ZFR0 field definitions to match the rev M.a.a Arm ARM, as the F16MM SVE-only field is not one we had a definition for previously. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 2 ++ target/arm/cpu64.c | 16 ++++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 1bcf28ab08..e0b7a45b7b 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -367,12 +367,14 @@ FIELD(ID_AA64DFR0, HPMN0, 60, 4) =20 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) FIELD(ID_AA64ZFR0, AES, 4, 4) +FIELD(ID_AA64ZFR0, ELTPERM, 12, 4) FIELD(ID_AA64ZFR0, BITPERM, 16, 4) FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) FIELD(ID_AA64ZFR0, B16B16, 24, 4) FIELD(ID_AA64ZFR0, SHA3, 32, 4) FIELD(ID_AA64ZFR0, SM4, 40, 4) FIELD(ID_AA64ZFR0, I8MM, 44, 4) +FIELD(ID_AA64ZFR0, F16MM, 48, 4) FIELD(ID_AA64ZFR0, F32MM, 52, 4) FIELD(ID_AA64ZFR0, F64MM, 56, 4) =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 26873a39b4..a9c1e60c95 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -133,9 +133,17 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) if (!cpu_isar_feature(aa64_sve, cpu)) { /* * SVE is disabled and so are all vector lengths. Good. - * Disable all SVE extensions as well. + * Disable all SVE extensions as well. Note that some ZFR0 + * fields are used also by SME so must not be wiped in + * an SME-no-SVE config. We will clear the rest in + * arm_cpu_sme_finalize() if necessary. */ - SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F64MM, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F32MM, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F16MM, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, SM4, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, B16B16, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, SVEVER, 0); return; } =20 @@ -335,6 +343,10 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) if (vq_map =3D=3D 0) { if (!cpu_isar_feature(aa64_sme, cpu)) { SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); + if (!cpu_isar_feature(aa64_sve, cpu)) { + /* This clears the "SVE or SME" fields in ZFR0 */ + SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); + } return; } =20 --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039397; cv=none; d=zohomail.com; s=zohoarc; b=PkviABub3VDPpCGUYs9K2xIBYnbwaojWrePHoBXSP/tNAl3/1vZk0lQi5Rjx7e/gKCUNObYDuILWy2Lm7dvTuUynHfTRFdwf/DUXGBs+MNqWeFazqfnk+QNw4EKV8cj6keAOd4BHd2rH7WJBKUj3PEQ1xanftGkVy4Iha1LvkO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039397; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yrzRKxM+gUNzaRlAaieIAxkZQfBhxlc5kLCyWkeZ6Cg=; b=nBGMLVAJexU+sZpNlaPJ9jRpid8X7qLMPl1GwI82TcHd1N+DdkRjFtUkvi3a6oKOVIY3MKkuehA0xBzO1rMTbosRLbUXZ0sj9Nw4bfrE21XfsrW+N9xoFGXpiP2RVPZ0KkiTSGRS4rxltwPvJw6fUQB1FQEWLOa8rf5/L6YKrQY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039397952979.0566942752955; Mon, 2 Feb 2026 05:36:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu4M-0007If-7R; Mon, 02 Feb 2026 08:34:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu4G-00076t-SA for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:17 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu4D-0002i3-IT for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:16 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-482f2599980so15948935e9.0 for ; Mon, 02 Feb 2026 05:34:13 -0800 (PST) Received: from lanath.. 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If we have a CPU with SME but not SVE, squash the FA64 bit in arm_cpu_sme_finalize(). This doesn't have any effect at the moment because we don't let the user create an SME-without-SVE CPU, but we are about to lift that restriction. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a9c1e60c95..c0447c8d54 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -385,6 +385,11 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) /* SME2 or better */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, 2); } + + if (!cpu_isar_feature(aa64_sve, cpu)) { + /* FEAT_SME_FA64 requires SVE, not just SME */ + FIELD_DP64_IDREG(&cpu->isar, ID_AA64SMFR0, FA64, 0); + } } =20 static bool cpu_arm_get_sme(Object *obj, Error **errp) --=20 2.43.0 From nobody Sat Feb 7 06:54:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039369; cv=none; d=zohomail.com; s=zohoarc; b=KrPaNn4zwCZcd8XSPrfr9jas0/FQ3tzwy0Hz2vQlZGFt+fLYWb/TRM/xsOytcE6O8pnW1LFqrviWFoX5wSYjqUjZIgRaXBdRrEaIeE83dRfvVHdfRHcEpImLcDtUfaNS2jNnv2DTp5TD+g5WQHECvYyifTGRPO69hMzD+hBggxY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039369; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gLvC5MaXe0awrq4wxvHbYeODF5FYi1/mHsfwhmhjVlU=; b=FouBZCJiljhPmZT3UdsJsBWCgK+RTLRO8h/dYrdmBWtsnitZezyISNPgxoCIufe2fe/ob70w4nlS8sHMWHvOqVtbD8Z8VoJmSRHFhidxDSF4XZORme0EEwdw4fErFMOAxx3C+1yATPe+uoSNhrxAoGzwmJ21sYs8GrdSki1Yb70= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039369874573.9443497144421; Mon, 2 Feb 2026 05:36:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu4L-0007Gb-4t; Mon, 02 Feb 2026 08:34:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu4G-00076x-TC for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:17 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu4E-0002iD-GV for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:16 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4806f9e61f9so22651295e9.1 for ; Mon, 02 Feb 2026 05:34:14 -0800 (PST) Received: from lanath.. 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This was something we did in the run-up to a release to avoid an assertion failure in smcr_write() if the user disabled SVE on the 'max' CPU without disabling SME also. Now that we have corrected the code so that it doesn't assert in an SME-without-SVE setup, we can let users select it. This effectively reverts f7767ca30179. Note that this now means that command lines like "-cpu max,sve=3Doff" which used to turn off SME and SVE will now give you a CPU with SME but not SVE. This is permitted by our loose "max can always give you extra stuff" rules, but may be unexpected to users. Mention this in the CPU property documentation. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Peter Maydell --- docs/system/arm/cpu-features.rst | 10 ++++++++-- target/arm/cpu.c | 10 ---------- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 024119449c..3db1f19401 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -323,12 +323,18 @@ SVE CPU Property Parsing Semantics enable SVE2). There are not generally any lower-level controls for disabling specific SVE sub-features. =20 + 11) Disabling SVE does not automatically disable SME. If you want to + disable both you must use ``sve=3Doff,sme=3Doff``. In particular, + for the ``max`` CPU, ``sve=3Doff`` alone will give you a CPU with + SME only (and which therefore still has the SVE vector registers). + Most users will want to disable both at once. + SVE CPU Property Examples ------------------------- =20 - 1) Disable SVE:: + 1) Disable SVE and SME:: =20 - $ qemu-system-aarch64 -M virt -cpu max,sve=3Doff + $ qemu-system-aarch64 -M virt -cpu max,sve=3Doff,sme=3Doff =20 2) Implicitly enable all vector lengths for the ``max`` CPU type:: =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 586202071d..32cd076f6e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1571,16 +1571,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **= errp) return; } =20 - /* - * FEAT_SME is not architecturally dependent on FEAT_SVE (unless - * FEAT_SME_FA64 is present). However our implementation currently - * assumes it, so if the user asked for sve=3Doff then turn off SM= E also. - * (KVM doesn't currently support SME at all.) - */ - if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve,= cpu)) { - object_property_set_bool(OBJECT(cpu), "sme", false, &error_abo= rt); - } - arm_cpu_sme_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.43.0