Add support for the ACPI RISC-V Quality of Service Controller (RQSC)
table [1] which describes the CBQRI controllers present in a system.
This series is based on the v5 series that implements Ssqosid extension
and CBQRI controllers [2]. The patches are also available as the
b4/riscv-rqsc branch [3].

This series is marked as an RFC due to open issues:

 - The "Add cache structure table creation for PPTT table" series [4] by
   Sia Jee Heng is used to generate to the PPTT table with a cache type
   1 structure for a 3-layer cache topology. This series doesn't seem to
   have made progress on landing upstream.

 - cluster_id is not set by the riscv arch, so cores 0-3 are hard-coded
   to be cluster 0 and cores 4-8 are cluster 1. The proper solution is
   for the riscv code to set cluster_id the same way as the arm code.

 - cluster 0 uses the first L2 cache controller and cluster 1 uses the
   second L2 cache controller. A more general solution is to make the L2
   cache private to the cluster and not private to the core.

 - struct CPUCaches is modified to add CPUCacheInfo *l2_cluster1_cache
   and CPUCacheInfo *l2_cluster2_cache. This is a hack to support the
   example configuration used for CBQRI. A solution could make use of
   the flexible approach in the "Specifying cache topology on ARM" patch
   series by Alireza Sanaee [5].

 - Need a solution to correlate bandwidth controllers to the Proximity
   Domain for Memory Affinity Structures in the SRAT table.

There is a Linux kernel patch series [6] and branch [7] that implement
Ssqosid and CBQRI support in resctrl as well as parsing the RQSC to
discover the CBQRI controllers in the system.

This Qemu series was developed and tested with the following
configuration:

  Base addr  Size
  0x4820000  4KB  Cluster 0 L2 cache controller
  0x4821000  4KB  Cluster 1 L2 cache controller
  0x4828000  4KB  Memory controller 0
  0x4829000  4KB  Memory controller 1
  0X482a000  4KB  Memory controller 2
  0X482b000  4KB  Shared LLC cache controller

The example platform is created with the following:

  qemu-system-riscv64 \
	-M virt,pflash0=pflash0,pflash1=pflash1,aia=aplic-imsic  \
	-smp cpus=8,sockets=1,clusters=2,cores=4,threads=1 \
	-m 1G \
	-nographic \
	-kernel ${LINUX}/arch/riscv/boot/Image \
	-append "root=/dev/vda rootwait" \
	-blockdev node-name=pflash0,driver=file,read-only=on,filename=${EDK}/RISCV_VIRT_CODE.fd \
	-blockdev node-name=pflash1,driver=file,filename=${EDK}/RISCV_VIRT_VARS.fd \
	-drive if=none,file=${ROOTFS}/rootfs.ext2,format=raw,id=hd0 \
	-device virtio-blk-device,drive=hd0 \
	-device qemu-xhci \
	-device usb-kbd \
	-device virtio-net-pci,netdev=net0 \
	-netdev user,id=net0 \
	-device riscv.cbqri.capacity,max_mcids=256,max_rcids=64,ncblks=12,alloc_op_flush_rcid=false,mon_op_config_event=false,mon_op_read_counter=false,mon_evt_id_none=false,mon_evt_id_occupancy=false,mmio_base=0x04820000 \
	-device riscv.cbqri.capacity,max_mcids=256,max_rcids=64,ncblks=12,alloc_op_flush_rcid=false,mon_op_config_event=false,mon_op_read_counter=false,mon_evt_id_none=false,mon_evt_id_occupancy=false,mmio_base=0x04821000 \
	-device riscv.cbqri.capacity,max_mcids=256,max_rcids=64,ncblks=16,mmio_base=0x0482B000 \
	-device riscv.cbqri.bandwidth,max_mcids=256,max_rcids=64,nbwblks=1024,mrbwb=819,mmio_base=0x04828000 \
	-device riscv.cbqri.bandwidth,max_mcids=256,max_rcids=64,nbwblks=1024,mrbwb=819,mmio_base=0x04829000 \
	-device riscv.cbqri.bandwidth,max_mcids=256,max_rcids=64,nbwblks=1024,mrbwb=819,mmio_base=0x0482a000

[1] https://github.com/riscv-non-isa/riscv-rqsc/blob/main/src/
[2] https://lore.kernel.org/all/20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org/
[3] https://github.com/tt-fustini/qemu/tree/b4/riscv-rqsc
[4] https://lore.kernel.org/all/20240129104039.117671-1-jeeheng.sia@starfivetech.com/
[5] https://lore.kernel.org/all/20250310162337.844-1-alireza.sanaee@huawei.com/
[6] https://lore.kernel.org/all/20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org/
[7] https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git/log/?h=b4/ssqosid-cbqri

Signed-off-by: Drew Fustini <fustini@kernel.org>
---
Drew Fustini (4):
      hw/riscv: virt-acpi-build: Adjust RQSC cache properties
      include: acpi: aml-build: Add Cache ID and L2 cache for each cluster
      acpi: aml-build: Add Cache ID to PPTT table and set Cluster ID
      hw/riscv: virt-acpi-build: Build PPTT table before RQSC table

Sia Jee Heng (2):
      acpi: aml-build: Add cache structure table creation for PPTT table
      hw/riscv: virt-acpi-build: Generate PPTT table

Vasudevan Srinivasan (1):
      hw/riscv: Add support for ACPI RQSC table

 hw/acpi/aml-build.c         | 108 ++++++++++++++++++++++++--
 hw/core/sysbus-fdt.c        |   3 +
 hw/riscv/cbqri_bandwidth.c  |  11 +++
 hw/riscv/cbqri_capacity.c   |  11 +++
 hw/riscv/virt-acpi-build.c  | 181 ++++++++++++++++++++++++++++++++++++++++++++
 hw/riscv/virt.c             |   1 +
 include/hw/acpi/aml-build.h |  23 +++++-
 include/hw/riscv/cbqri.h    |  12 +++
 8 files changed, 343 insertions(+), 7 deletions(-)
---
base-commit: 117b7aeabad83d437dfa69f2ee2bac75c0e02abe
change-id: 20260201-riscv-rqsc-ae806ee0a7aa

Best regards,
-- 
Drew Fustini <fustini@kernel.org>