From nobody Sun Feb 8 23:58:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1770102290; cv=none; d=zohomail.com; s=zohoarc; b=BoRDVXf2QO1vmTUS7NV2Vtoqlodyf7UlT0qCH3tNV9Nxt5TteKHJov7ZjRsN7NDnl/4/CVGVyJ+Tm4bh4IQFmvb0ljCL/VwHFNhi8NE9kNjlvURwKmWHuHzvumIBuF9sEy9yTQQoImxhBCZw8rQu5hBh1jxuaosnIgQR9hoUNfM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770102290; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FiUTWga3ENGjL5YtwwPSrAx5rMUi42cFmfinZoiV6TA=; b=chskgLa2GVQupsrmnPYjCRzipBxD8RAvrX5PMF7VOgwn0gF/Vp+CFnYDw6We5l57jCPqlhLcmSfSbvI5DnRUwDtekAnZeLWx9/2sEhu0CMaTnbUHK0vFJsNORRq/795TEAMZpTZ3dYdLGJBcbN252t+775VPWOoMPWm9N4CC7Qk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770102290446486.94813016203705; Mon, 2 Feb 2026 23:04:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnASB-0002D7-32; Tue, 03 Feb 2026 02:04:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnARv-00020a-Vd; Tue, 03 Feb 2026 02:03:47 -0500 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnARu-0003Dq-07; Tue, 03 Feb 2026 02:03:47 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 77C736013C; Tue, 3 Feb 2026 07:03:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9AD4EC2BC86; Tue, 3 Feb 2026 07:03:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770102216; bh=e2KtRGoKZ47Vc8zsUbi+oBeJfeeSHXFxI38YIVjPrls=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=E8KArSHj6slGZfuj6yEjISiiVHht4bbO92EsSJNrBhA0ULUE3EI6verYKRY1Oshra SOoQHnNN1ghfTZQKhAY+FsbZg39kMbUA7Kb7w1Q+/nBzG0jXFS8OZhiQPcg5CSlmtI DYDruaNhWB9lOb+YNLh8rGvYWyfScd3zXV42qu6eP2zT6FJ8GpEizbyr4c4cTmmyG6 0aOn8A/JIKgbAOAbS51dXIDVINWkOBRJ+c/LDinH711NPAh/v30d3u2goXBhAThbak cpF90VFVuHhieFL1QVQ2v5HhMEj17UAZm/66MUbmhDd2LcIHuaBvv8j1reK70kn0kV /X5PADs1eEsUA== From: Drew Fustini Date: Mon, 02 Feb 2026 23:01:17 -0800 Subject: [PATCH RFC 1/7] hw/riscv: Add support for ACPI RQSC table MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-riscv-rqsc-v1-1-dcf448a3ed73@kernel.org> References: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> In-Reply-To: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Sunil V L , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Peter Maydell , Sia Jee Heng , qemu-arm@nongnu.org, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=9127; i=fustini@kernel.org; h=from:subject:message-id; bh=eXZEfZrgLgLSbfNI9AvAgsinKRrStsfYatyPSMNmam0=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWQ2zj3GdOve2wDO/9miZW/enHyiJVXa8umE8a9rbGfdb /DLMxrd7ChlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBMhMOT4X8655Rdj5f+nGD/ KiTikuiziJzX5pd1l3w18A0LzJgv2yLJyPDwMMu8H37J+ayMLElGcxVLMmUW+ot03Ztjb/F2O1v sDGYA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2600:3c04:e001:324:0:1991:8:25; envelope-from=fustini@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1770102292832158500 From: Vasudevan Srinivasan In build_rqsc(), set Res ID 1 for each cache controller in RQSC table. The AML code that generates that PPTT table uses the cache controller mmio_base address as the Cache ID. TODO: Similar plumbing still needs to be done to correlate bandwitch controllers to the Proximity Domain for Memory Affinity Structures in the SRAT table. Signed-off-by: Vasudevan Srinivasan Signed-off-by: Drew Fustini --- hw/core/sysbus-fdt.c | 3 ++ hw/riscv/cbqri_bandwidth.c | 11 +++++ hw/riscv/cbqri_capacity.c | 11 +++++ hw/riscv/virt-acpi-build.c | 121 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/riscv/cbqri.h | 12 +++++ 5 files changed, 158 insertions(+) diff --git a/hw/core/sysbus-fdt.c b/hw/core/sysbus-fdt.c index 89d0c464454a..d7967cde51be 100644 --- a/hw/core/sysbus-fdt.c +++ b/hw/core/sysbus-fdt.c @@ -36,6 +36,7 @@ #include "hw/display/ramfb.h" #include "hw/uefi/var-service-api.h" #include "hw/arm/fdt.h" +#include "hw/riscv/cbqri.h" =20 /* * internal struct that contains the information to create dynamic @@ -140,6 +141,8 @@ static const BindingEntry bindings[] =3D { TYPE_BINDING(TYPE_ARM_SMMUV3, no_fdt_node), TYPE_BINDING(TYPE_RAMFB_DEVICE, no_fdt_node), TYPE_BINDING(TYPE_UEFI_VARS_SYSBUS, add_uefi_vars_node), + TYPE_BINDING(TYPE_RISCV_CBQRI_BC, no_fdt_node), + TYPE_BINDING(TYPE_RISCV_CBQRI_CC, no_fdt_node), TYPE_BINDING("", NULL), /* last element */ }; =20 diff --git a/hw/riscv/cbqri_bandwidth.c b/hw/riscv/cbqri_bandwidth.c index f86b3bf75027..01f03d790410 100644 --- a/hw/riscv/cbqri_bandwidth.c +++ b/hw/riscv/cbqri_bandwidth.c @@ -635,4 +635,15 @@ DeviceState *riscv_cbqri_bc_create(hwaddr addr, return dev; } =20 +void get_bc_details(DeviceState *ds, const char *type, RQSC *rqsc) +{ + if (strcmp(type, TYPE_RISCV_CBQRI_BC) =3D=3D 0) { + RiscvCbqriBandwidthState *bcs =3D RISCV_CBQRI_BC(ds); + (rqsc)->controllerType =3D 1; + (rqsc)->mmio_base =3D bcs->mmio_base; + (rqsc)->rcidCount =3D bcs->nb_rcids; + (rqsc)->mcidCount =3D bcs->nb_mcids; + } +} + type_init(riscv_cbqri_bc_register_types) diff --git a/hw/riscv/cbqri_capacity.c b/hw/riscv/cbqri_capacity.c index 1c3570262a36..8d830c278e00 100644 --- a/hw/riscv/cbqri_capacity.c +++ b/hw/riscv/cbqri_capacity.c @@ -730,4 +730,15 @@ DeviceState *riscv_cbqri_cc_create(hwaddr addr, return dev; } =20 +void get_cc_details(DeviceState *ds, const char *type, RQSC *rqsc) +{ + if (strcmp(type, TYPE_RISCV_CBQRI_CC) =3D=3D 0) { + RiscvCbqriCapacityState *ccs =3D RISCV_CBQRI_CC(ds); + rqsc->controllerType =3D 0; + rqsc->mmio_base =3D ccs->mmio_base; + rqsc->rcidCount =3D ccs->nb_rcids; + rqsc->mcidCount =3D ccs->nb_mcids; + } +} + type_init(riscv_cbqri_cc_register_types) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index f1406cb68339..210b3f5fff98 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -34,6 +34,7 @@ #include "hw/pci-host/gpex.h" #include "hw/riscv/virt.h" #include "hw/riscv/numa.h" +#include "hw/riscv/cbqri.h" #include "hw/virtio/virtio-acpi.h" #include "migration/vmstate.h" #include "qapi/error.h" @@ -269,6 +270,123 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RI= SCVVirtState *s) /* RHCT Node[N] starts at offset 56 */ #define RHCT_NODE_ARRAY_OFFSET 56 =20 +static u_int8_t gatherCbqriDetails(RISCVVirtState *vs, RQSC rqsc[]) +{ + BusChild *bc =3D NULL; + DeviceState *ds =3D NULL; + u_int8_t controllerCount =3D 0; + + if (vs =3D=3D NULL) { + printf("RISCVVirtState is NULL\n"); + return 0; + } + + QTAILQ_FOREACH(bc, &vs->platform_bus_dev->parent_bus->children, siblin= g) { + if (strcmp(object_get_typename(OBJECT(bc->child)), + TYPE_RISCV_CBQRI_BC) =3D=3D 0) + { + ds =3D bc->child; + get_bc_details(ds, object_get_typename(OBJECT(bc->child)), + &(rqsc[controllerCount])); + controllerCount++; + } + if (strcmp(object_get_typename(OBJECT(bc->child)), + TYPE_RISCV_CBQRI_CC) =3D=3D 0) + { + ds =3D bc->child; + get_cc_details(ds, object_get_typename(OBJECT(bc->child)), + &(rqsc[controllerCount])); + controllerCount++; + } + } + + return controllerCount; +} + +/* + * + * RQSC Table + * + */ +static void build_rqsc(GArray *table_data, + BIOSLinker *linker, + RISCVVirtState *s) +{ + int numCbqriControllers =3D 0; + /* Support for upto 10 CBQRI controllers */ + RQSC rqsc[10]; + int i =3D 0; + + AcpiTable table =3D { .sig =3D "RQSC", .rev =3D 0, .oem_id =3D s->oem_= id, + .oem_table_id =3D s->oem_table_id }; + + acpi_table_begin(&table, table_data); + + numCbqriControllers =3D gatherCbqriDetails(s, rqsc); + + fprintf(stderr, "[QEMU] %s(): numCbqriControllers =3D %d\n", + __func__, numCbqriControllers); + /* Number of QoS Controllers */ + build_append_int_noprefix(table_data, numCbqriControllers, 4); + + for (i =3D 0; i < numCbqriControllers; i++) { + fprintf(stderr, "[QEMU] %s(): Controller %d: Controller Type =3D %= d\n", + __func__, i, rqsc[i].controllerType); + /* Controller Type */ + build_append_int_noprefix(table_data, rqsc[i].controllerType, 1); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 1); + /* Length */ + build_append_int_noprefix(table_data, 32, 2); + /* Controller register interface address */ + build_append_gas(table_data, + AML_AS_SYSTEM_MEMORY, + 0, + 0, + 4, + rqsc[i].mmio_base); + /* RCID Count */ + build_append_int_noprefix(table_data, rqsc[i].rcidCount, 4); + /* MCID Count */ + build_append_int_noprefix(table_data, rqsc[i].mcidCount, 4); + /* Controller Flags*/ + build_append_int_noprefix(table_data, 0, 2); + /* Number of Resources hard coded to 1 for QEMU */ + build_append_int_noprefix(table_data, 1, 2); + + /* Resource Structure per Controller */ + /* Resource Type - Setting to the same as Controller Type for now= */ + build_append_int_noprefix(table_data, rqsc[i].controllerType, 1); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 1); + /* Length of Resource Structure */ + build_append_int_noprefix(table_data, 20, 2); + /* Resource Flags */ + build_append_int_noprefix(table_data, 0, 2); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 1); + /* Resource ID Type - Setting to the same as Controller Type for = now */ + build_append_int_noprefix(table_data, rqsc[i].controllerType, 1); + /* + * The AML code that generates that PPTT table uses the cache + * controller mmio_base address as the Cache ID. + * + * TODO: Similar plumbing still needs to be done to correlate + * the memory controller to Proximity Domain in the SRAT table + */ + fprintf(stderr, "[QEMU] %s(): Controller %d: Resource ID 1 =3D 0x%= lx\n", + __func__, i, rqsc[i].mmio_base); + /* Resource ID 1 DWORD 1 CacheID or Proximity Domain */ + build_append_int_noprefix(table_data, rqsc[i].mmio_base, 4); + /* Resource ID 1 DWORD 2 Reserved */ + build_append_int_noprefix(table_data, 0, 4); + /* Resrouce ID 2 */ + build_append_int_noprefix(table_data, 0, 4); + } + + acpi_table_end(linker, &table); +} + /* * ACPI spec, Revision 6.6 * 5.2.37 RISC-V Hart Capabilities Table (RHCT) @@ -894,6 +1012,9 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBui= ldTables *tables) spcr_setup(tables_blob, tables->linker, s); } =20 + acpi_add_table(table_offsets, tables_blob); + build_rqsc(tables_blob, tables->linker, s); + acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg =3D { diff --git a/include/hw/riscv/cbqri.h b/include/hw/riscv/cbqri.h index a07f1e3a2dde..227d4d2bd842 100644 --- a/include/hw/riscv/cbqri.h +++ b/include/hw/riscv/cbqri.h @@ -79,4 +79,16 @@ DeviceState *riscv_cbqri_cc_create(hwaddr addr, DeviceState *riscv_cbqri_bc_create(hwaddr addr, const RiscvCbqriBandwidthCaps *caps, const char *target_name); +void example_soc_cbqri_init(void); + +typedef struct _RQSC { + u_int8_t controllerType; + u_int64_t mmio_base; + u_int16_t rcidCount; + u_int16_t mcidCount; +} RQSC; + +void get_bc_details(DeviceState *ds, const char *type, RQSC *rqsc); +void get_cc_details(DeviceState *ds, const char *type, RQSC *rqsc); + #endif --=20 2.43.0 From nobody Sun Feb 8 23:58:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1770102311; cv=none; d=zohomail.com; s=zohoarc; b=OfNyN3UEbiSAgtXCmm38z5pw1FNCpKjBEt7STrBovMfGsuxjWcC79cXhasjE1wopaouykPnARUpPysXw4sByAM4CFzgO3xUKlu4ktpU17BTgthWujhSTBqWh6RCedfHhgkcclF9hmCOj27qHQjLjPnG2Xni9MQ+s0WF+99Kw6pI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770102311; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 03 Feb 2026 02:03:51 -0500 Received: from sea.source.kernel.org ([172.234.252.31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnARv-0003Du-Iw; Tue, 03 Feb 2026 02:03:49 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id B4A0541874; Tue, 3 Feb 2026 07:03:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4754BC19425; Tue, 3 Feb 2026 07:03:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770102216; bh=wxW16Aj8+WzjRknuFv3nEfcuaZXq+HX7rJ/JER0/6CM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MawDolkzv19ctlvC0TLxkDaRclaw8oxxAEtE/JJyNL08KZCWJ0F5y2BdNZdtXP9Yk 5HsFulI+NMi68HUtNZc06WkjSlRGLJ6gu3mJhLW8t+c3E8IioJWT/F0x+iWAkJHe7/ gJBxzrl6m7j7pVgjWDxugUSVryH3J2GRg9/OQrqExk/UPfvrrsvo0xuGQGSPH5caSO 3Vy+FwqF8+6Sxx4xjixKniSevIJciDvv9vuzbKY9TlBs7ixBnRs8qjO5DTkDoqR2qR idwPBp12+ybS0iuPQxEhOGtKpFABqvtSDJ7L5s+6UNCmhNBINNPQQuXclEqGXUJaGr oH+dE4q+gO63A== From: Drew Fustini Date: Mon, 02 Feb 2026 23:01:18 -0800 Subject: [PATCH RFC 2/7] acpi: aml-build: Add cache structure table creation for PPTT table MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-riscv-rqsc-v1-2-dcf448a3ed73@kernel.org> References: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> In-Reply-To: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Sunil V L , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Peter Maydell , Sia Jee Heng , qemu-arm@nongnu.org, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8295; i=fustini@kernel.org; h=from:subject:message-id; bh=5p3vnkRRKyTkMr0IIO7uoTexFRSKAeuHTrWqcyemBRY=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWQ2zj3W75lzS6DswOUvM2eztO35e5iD5eR/35XimTWt6 nc2qpU3dZSyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmoi3N8M96nkb5k0x1kelH hWyqpy3LvmVbrx+27f8S9aZr60KLV0gwMpw2+at7XZmPZ8q6w+uSvv3kWvjw6//bq9lYtE//WiV /7gY/AA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.234.252.31; envelope-from=fustini@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1770103862757158500 From: Sia Jee Heng Adds cache structure table generation for the Processor Properties Topology Table (PPTT) to describe cache hierarchy information for ACPI guests. A 3-level cache topology is employed here, referring to the type 1 cache structure according to ACPI spec v6.3. The L1 cache and L2 cache are private resources for the core, while the L3 cache is the private resource for the cluster. In the absence of cluster values in the QEMU command, a 2-layer cache is expected. The default cache value should be passed in from the architecture code. Examples: 3-layer: -smp 4,sockets=3D1,clusters=3D2,cores=3D2,threads=3D1 2-layer: -smp 4,sockets=3D1,cores=3D2,threads=3D2 Link: https://lore.kernel.org/all/20240129104039.117671-1-jeeheng.sia@starf= ivetech.com/ Signed-off-by: Sia Jee Heng Signed-off-by: Drew Fustini --- hw/acpi/aml-build.c | 69 +++++++++++++++++++++++++++++++++++++++++= ---- include/hw/acpi/aml-build.h | 21 +++++++++++++- 2 files changed, 84 insertions(+), 6 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index dad4cfcc7d80..742e7a6eb261 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2140,12 +2140,41 @@ void build_spcr(GArray *table_data, BIOSLinker *lin= ker, } acpi_table_end(linker, &table); } + +/* ACPI spec, Revision 6.3 Cache type structure (Type 1) */ +static void build_cache_structure(GArray *tbl, + uint32_t next_level, + CPUCacheInfo *cache_info) +{ + /* Cache type structure */ + build_append_byte(tbl, 1); + /* Length */ + build_append_byte(tbl, 24); + /* Reserved */ + build_append_int_noprefix(tbl, 0, 2); + /* Flags */ + build_append_int_noprefix(tbl, 0x7f, 4); + /* Next level cache */ + build_append_int_noprefix(tbl, next_level, 4); + /* Size */ + build_append_int_noprefix(tbl, cache_info->size, 4); + /* Number of sets */ + build_append_int_noprefix(tbl, cache_info->sets, 4); + /* Associativity */ + build_append_byte(tbl, cache_info->associativity); + /* Attributes */ + build_append_byte(tbl, cache_info->attributes); + /* Line size */ + build_append_int_noprefix(tbl, cache_info->line_size, 2); +} + /* * ACPI spec, Revision 6.3 * 5.2.29 Processor Properties Topology Table (PPTT) */ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id) + const char *oem_id, const char *oem_table_id, + const CPUCaches *CPUCaches) { MachineClass *mc =3D MACHINE_GET_CLASS(ms); CPUArchIdList *cpus =3D ms->possible_cpus; @@ -2153,6 +2182,8 @@ void build_pptt(GArray *table_data, BIOSLinker *linke= r, MachineState *ms, uint32_t socket_offset =3D 0, cluster_offset =3D 0, core_offset =3D 0; uint32_t pptt_start =3D table_data->len; uint32_t root_offset; + uint32_t l3_offset =3D 0, priv_num =3D 0; + uint32_t priv_rsrc[3] =3D {0}; int n; AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 2, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; @@ -2183,11 +2214,15 @@ void build_pptt(GArray *table_data, BIOSLinker *lin= ker, MachineState *ms, socket_id =3D cpus->cpus[n].props.socket_id; cluster_id =3D -1; core_id =3D -1; + priv_num =3D 0; socket_offset =3D table_data->len - pptt_start; build_processor_hierarchy_node(table_data, (1 << 0) | /* Physical package */ (1 << 4), /* Identical Implementation */ - root_offset, socket_id, NULL, 0); + root_offset, + socket_id, + NULL, + priv_num); } =20 if (mc->smp_props.clusters_supported && mc->smp_props.has_clusters= ) { @@ -2195,21 +2230,45 @@ void build_pptt(GArray *table_data, BIOSLinker *lin= ker, MachineState *ms, assert(cpus->cpus[n].props.cluster_id > cluster_id); cluster_id =3D cpus->cpus[n].props.cluster_id; core_id =3D -1; + priv_num =3D 0; + l3_offset =3D table_data->len - pptt_start; + /* L3 cache type structure */ + if (CPUCaches && CPUCaches->l3_cache) { + priv_num =3D 1; + build_cache_structure(table_data, 0, CPUCaches->l3_cac= he); + } cluster_offset =3D table_data->len - pptt_start; build_processor_hierarchy_node(table_data, (0 << 0) | /* Not a physical package */ (1 << 4), /* Identical Implementation */ - socket_offset, cluster_id, NULL, 0); + socket_offset, cluster_id, &l3_offset, priv_num); } } else { cluster_offset =3D socket_offset; } =20 + if (CPUCaches) { + /* L2 cache type structure */ + priv_rsrc[0] =3D table_data->len - pptt_start; + build_cache_structure(table_data, 0, CPUCaches->l2_cache); + + /* L1d cache type structure */ + priv_rsrc[1] =3D table_data->len - pptt_start; + build_cache_structure(table_data, priv_rsrc[0], + CPUCaches->l1d_cache); + + /* L1i cache type structure */ + priv_rsrc[2] =3D table_data->len - pptt_start; + build_cache_structure(table_data, priv_rsrc[0], + CPUCaches->l1i_cache); + + priv_num =3D 3; + } if (ms->smp.threads =3D=3D 1) { build_processor_hierarchy_node(table_data, (1 << 1) | /* ACPI Processor ID valid */ (1 << 3), /* Node is a Leaf */ - cluster_offset, n, NULL, 0); + cluster_offset, n, priv_rsrc, priv_num); } else { if (cpus->cpus[n].props.core_id !=3D core_id) { assert(cpus->cpus[n].props.core_id > core_id); @@ -2225,7 +2284,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linke= r, MachineState *ms, (1 << 1) | /* ACPI Processor ID valid */ (1 << 2) | /* Processor is a Thread */ (1 << 3), /* Node is a Leaf */ - core_offset, n, NULL, 0); + core_offset, n, priv_rsrc, priv_num); } } =20 diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index f38e12971932..33b303fc833b 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -3,6 +3,7 @@ =20 #include "hw/acpi/acpi-defs.h" #include "hw/acpi/bios-linker-loader.h" +#include "include/hw/core/cpu.h" =20 #define ACPI_BUILD_APPNAME6 "BOCHS " #define ACPI_BUILD_APPNAME8 "BXPC " @@ -234,6 +235,23 @@ struct CrsRangeSet { GPtrArray *mem_64bit_ranges; } CrsRangeSet; =20 +typedef +struct CPUCacheInfo { + enum CacheType type; /* Cache Type*/ + uint32_t size; /* Size of the cache in bytes */ + uint32_t sets; /* Number of sets in the cache */ + uint8_t associativity; /* Cache associativity */ + uint8_t attributes; /* Cache attributes */ + uint16_t line_size; /* Line size in bytes */ +} CPUCacheInfo; + +typedef +struct CPUCaches { + CPUCacheInfo *l1d_cache; + CPUCacheInfo *l1i_cache; + CPUCacheInfo *l2_cache; + CPUCacheInfo *l3_cache; +} CPUCaches; =20 /* * ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors @@ -499,7 +517,8 @@ void build_slit(GArray *table_data, BIOSLinker *linker,= MachineState *ms, const char *oem_id, const char *oem_table_id); =20 void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id); + const char *oem_id, const char *oem_table_id, + const CPUCaches *CPUCaches); =20 void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); 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Tue, 3 Feb 2026 07:03:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1138C2BC86; Tue, 3 Feb 2026 07:03:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770102217; bh=Nkr5nf9b7Y4A9IBCYQHm95/Po/azKwjoY+f4gLgHvqk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Mm/hMfPJLfZVNBLSnNrD2YZr4EPrVCKv2Oa1w1RYa4eR/F9c+i6Dv1vdiUVk0XmQy Ykymu20za64Iygmrq11g5F1P0y6TkcDQz9o9oQpT29DM7ASDC9VRf6JG0alhRWf0HJ wD0pUv3YFC+x/BAGjJlVMWHh6MDNnGqgrSrbibkOcHktFoE8gpXeEhUsH/QecGgO3O nGwHtGc4JLz90aavL7n/G/1KiAJ2AruVnAeQE9WFwrkTCabntvibUjRNQNDdfKyADp D3slJnnTJa122Sqps2JPdnmz9eE+eH5FCGBHDWTlPSO9awqGIKdYZ2Dcpsv5b/vQN7 GNVFxFzPP7FVA== From: Drew Fustini Date: Mon, 02 Feb 2026 23:01:19 -0800 Subject: [PATCH RFC 3/7] hw/riscv: virt-acpi-build: Generate PPTT table MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-riscv-rqsc-v1-3-dcf448a3ed73@kernel.org> References: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> In-Reply-To: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Sunil V L , "Michael S. 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A 3-layer cache topology is used. Link: https://lore.kernel.org/all/20240129104039.117671-1-jeeheng.sia@starf= ivetech.com/ Signed-off-by: Sia Jee Heng Signed-off-by: Drew Fustini --- hw/riscv/virt-acpi-build.c | 47 ++++++++++++++++++++++++++++++++++++++++++= ++++ hw/riscv/virt.c | 1 + 2 files changed, 48 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 210b3f5fff98..5703b0827682 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -40,6 +40,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "system/reset.h" +#include "qemu/units.h" =20 #define ACPI_BUILD_TABLE_SIZE 0x20000 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) @@ -973,6 +974,48 @@ build_srat(GArray *table_data, BIOSLinker *linker, RIS= CVVirtState *vms) acpi_table_end(linker, &table); } =20 +static void pptt_setup(GArray *table_data, BIOSLinker *linker, MachineStat= e *ms, + const char *oem_id, const char *oem_table_id) +{ + CPUCaches default_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .size =3D 64 * KiB, + .line_size =3D 64, + .associativity =3D 4, + .sets =3D 256, + .attributes =3D 0x02, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .size =3D 64 * KiB, + .line_size =3D 64, + .associativity =3D 4, + .sets =3D 256, + .attributes =3D 0x04, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .size =3D 2048 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 4096, + .attributes =3D 0x0a, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .size =3D 4096 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 8192, + .attributes =3D 0x0a, + }, + }; + + build_pptt(table_data, linker, ms, oem_id, oem_table_id, + &default_cache_info); +} + static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) { GArray *table_offsets; @@ -1015,6 +1058,10 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiB= uildTables *tables) acpi_add_table(table_offsets, tables_blob); build_rqsc(tables_blob, tables->linker, s); =20 + acpi_add_table(table_offsets, tables_blob); + pptt_setup(tables_blob, tables->linker, ms, + s->oem_id, s->oem_table_id); + acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg =3D { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 99871119be44..491328f7e192 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1929,6 +1929,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->cpu_index_to_instance_props =3D riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; mc->numa_mem_supported =3D true; + mc->smp_props.clusters_supported =3D true; /* platform instead of architectural choice */ mc->cpu_cluster_has_numa_boundary =3D true; mc->default_ram_id =3D "riscv_virt_board.ram"; --=20 2.43.0 From nobody Sun Feb 8 23:58:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1770102297; cv=none; d=zohomail.com; s=zohoarc; b=Hn32BHClzB3egAV5cbD1WApgF9ABSZvvU+EhCh5qT/HlDjnoj0C5oyDOkebWZl2PQqkt0av0DHEXkWpqG52tNBo3A57qQg7v5k7xaMhPWXlp84aXQfRlblSJ/iLpqQSVt9WvxbTo5M+YQWTXDMagXZkLYusKhtJPmkjwje+EeT4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770102297; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-riscv-rqsc-v1-4-dcf448a3ed73@kernel.org> References: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> In-Reply-To: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Sunil V L , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Peter Maydell , Sia Jee Heng , qemu-arm@nongnu.org, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2270; i=fustini@kernel.org; h=from:subject:message-id; bh=KJJuiCEAdc4sb40f+3lpJ6ySCUeXhsuEemgr1CBy3E8=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWQ2zj12+oLQAevUShn+ghv/GF5G7jgrrzVJfnsRs6z9F p6Hj2xlO0pZGMS4GGTFFFk2fci7sMQr9OuC+S+2wcxhZQIZwsDFKQAT6cxm+F9vmafo13ty3oSb ocIlMoUntx74yPGw6lB1b0JBLc8iTk6GPzzzLv5YuJCv3LM3c7lez7EloqlJ2546h34QreOzVJv Gzg4A X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2600:3c04:e001:324:0:1991:8:25; envelope-from=fustini@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1770102298919158500 In pptt_setup(), set the cache properties to match the example CBQRI controller configuration. Base addr 0x4820000 Cluster 0 L2 cache controller 0x4821000 Cluster 1 L2 cache controller 0X482b000 Shared LLC cache controller Signed-off-by: Drew Fustini --- hw/riscv/virt-acpi-build.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 5703b0827682..da3c355427af 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -985,6 +985,7 @@ static void pptt_setup(GArray *table_data, BIOSLinker *= linker, MachineState *ms, .associativity =3D 4, .sets =3D 256, .attributes =3D 0x02, + .id =3D 0x1D, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -993,22 +994,34 @@ static void pptt_setup(GArray *table_data, BIOSLinker= *linker, MachineState *ms, .associativity =3D 4, .sets =3D 256, .attributes =3D 0x04, + .id =3D 0x1E, }, - .l2_cache =3D &(CPUCacheInfo) { + .l2_cluster1_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, - .size =3D 2048 * KiB, + .size =3D 750 * KiB, .line_size =3D 64, - .associativity =3D 8, - .sets =3D 4096, + .associativity =3D 12, + .sets =3D 1000, + .attributes =3D 0x0a, + .id =3D 0x4821000, + }, + .l2_cluster2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .size =3D 750 * KiB, + .line_size =3D 64, + .associativity =3D 12, + .sets =3D 1000, .attributes =3D 0x0a, + .id =3D 0x4820000, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, - .size =3D 4096 * KiB, + .size =3D 3 * MiB, .line_size =3D 64, - .associativity =3D 8, - .sets =3D 8192, + .associativity =3D 16, + .sets =3D 4096, .attributes =3D 0x0a, + .id =3D 0x482b000, }, }; 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Tue, 3 Feb 2026 07:03:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8A413C2BC86; Tue, 3 Feb 2026 07:03:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770102217; bh=xd/or6D4+Uo85wHzGmSUtze4r1hjimqUeK6Apn/pJpE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GGK66X0xdfpnLm+UXbqEmwY7idrbQX5ftRqJAgrjQxeGi/KaBNdKLXvII4/AtOLw8 6sL/9ORtBdEO3elA3dXvkWqF8+SzY6LVLZFknQh4UzLUdaHMs1rIJdO2PZgYSMHWgF Cq+UTVcml4aCd9pTIjjHkxFUm/L1E+2shYsraB3R+CC3gjbZG75XH7Fm7lVRK78pKa /t8dOQ0iWILPNtRYYzRsaGpvWEzqWS7Y6pgw68EFCgobCCn3OcOxi+ZQg/t/avP1VK GW7GfNMjfa+I7Qq+yJRD6vr3m1VL4JzC/UBgRZcWAgxkW9J+GUm8ioic3qrvsG1/Ga tcdFZejUySCnQ== From: Drew Fustini Date: Mon, 02 Feb 2026 23:01:21 -0800 Subject: [PATCH RFC 5/7] include: acpi: aml-build: Add Cache ID and L2 cache for each cluster MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-riscv-rqsc-v1-5-dcf448a3ed73@kernel.org> References: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> In-Reply-To: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Sunil V L , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Peter Maydell , Sia Jee Heng , qemu-arm@nongnu.org, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1399; i=fustini@kernel.org; h=from:subject:message-id; bh=xd/or6D4+Uo85wHzGmSUtze4r1hjimqUeK6Apn/pJpE=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWQ2zj0m8tQgNVGVaZ3ttUX/+F5rnpOTyOCOO/JhtWdqu PquqQmCHaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJ7GlgZGgpcU8zKbBb8e70 1o29F0xZbR14w3q4rixxW661Vf/X/UUM/+vZvN4r3d3Bm/pEeoc4w6eLPGVaqg/2hp1fEqGsm/W bmRkA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.105.4.254; envelope-from=fustini@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1770103890583158500 ACPI 6.4 added Cache ID to the PPTT Cache Type Structure so add id field to CPUCacheInfo. Add an L2 cache for each of the two clusters in CPUCaches. NOTE: This is hack as it mixes the specifics of the CBQRI example SoC into the the core ACPI AML code. A proper solution would make use of the flexible approach in the "Specifying cache topology on ARM" patch series by Alireza Sanaee. Link: https://lore.kernel.org/all/20250310162337.844-1-alireza.sanaee@huawe= i.com/ Signed-off-by: Drew Fustini --- include/hw/acpi/aml-build.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 33b303fc833b..2f7551da2b94 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -243,13 +243,15 @@ struct CPUCacheInfo { uint8_t associativity; /* Cache associativity */ uint8_t attributes; /* Cache attributes */ uint16_t line_size; /* Line size in bytes */ + uint32_t id; /* Cache ID - added in ACPI 6.4 */ } CPUCacheInfo; =20 typedef struct CPUCaches { CPUCacheInfo *l1d_cache; CPUCacheInfo *l1i_cache; - CPUCacheInfo *l2_cache; + CPUCacheInfo *l2_cluster1_cache; + CPUCacheInfo *l2_cluster2_cache; CPUCacheInfo *l3_cache; } CPUCaches; =20 --=20 2.43.0 From nobody Sun Feb 8 23:58:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1770102275; cv=none; d=zohomail.com; s=zohoarc; b=aqNruORv+VexAyCfscKtkxYvm/tgZAIv40l7nMPe2Fqkle1IE5H+LArclmPHZKRy7yL4ZHOckPM1+3UomV6AhQ91bEE0CisHC7oUrZGAHnG3W/3JINvAalzG06LXdco+RbUMKh6LUB8/auQqCu62SvJ1SL+Bexk6IaE3thgjGyI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770102275; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=azOaMqVEOHzsUxogGCN2ATgCOaodd1LxAZTj+Wbga28=; b=J6hLa2Hsw6n01TOu6TEjWhhPoHu+hvmw36G4MGtf6XC3HxF9PhxySshbGTZ+9xF7jJJgCOWt9oQ7XKItbVxQjPsgeNnR8e/sFDnCGjkGLtuefDuPcUNDAs4Eym7sxtkfk+vc0ZrDWyWCXHGXvxvXMWHrCZbdS6jTHbGP11P6J6k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770102275940191.47680986832245; Mon, 2 Feb 2026 23:04:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnASB-0002Dt-9v; Tue, 03 Feb 2026 02:04:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnARx-00020x-Vp; Tue, 03 Feb 2026 02:03:51 -0500 Received: from tor.source.kernel.org ([172.105.4.254]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnARv-0003EA-IC; Tue, 03 Feb 2026 02:03:49 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 8F3A660141; Tue, 3 Feb 2026 07:03:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F13F4C19425; Tue, 3 Feb 2026 07:03:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770102218; bh=g4wSj2V6c1HLF8bCaTH2AO2uiIhDCllAUUFILdOy3vI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=F03r8Xxc36vZp2i+Z+RbQcjfKNvYddJdqiA7/XLQkmu7+sfWjOLnCM7JNegnK042O rzVvPAzCQddiodxPuVNBJysztaUIroXUwJg/YZV5gCz2OVab6EVQR0MS62OgpWf03Z AOAenfmTc59pg6bb8AcXJfY2O0qQagS951oOzxZyzalfGukCSJ7z309DhU+uu8rVR6 o5qQpnP+lU7HW7WkRRr/V190SOZbBBSPCpaGTN/btL+PEQ1vwuTVkAKdw1vOH1ybnX qB6Ht2+0sVifYHH/vHjL6jRk3pYhUnrzc00h42JPWt5sMbN3ZGKZddmQ9JvZPeGgoQ m+4A0YdzBK5tg== From: Drew Fustini Date: Mon, 02 Feb 2026 23:01:22 -0800 Subject: [PATCH RFC 6/7] acpi: aml-build: Add Cache ID to PPTT table and set Cluster ID MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-riscv-rqsc-v1-6-dcf448a3ed73@kernel.org> References: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> In-Reply-To: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Sunil V L , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Peter Maydell , Sia Jee Heng , qemu-arm@nongnu.org, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6380; i=fustini@kernel.org; h=from:subject:message-id; bh=g4wSj2V6c1HLF8bCaTH2AO2uiIhDCllAUUFILdOy3vI=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWQ2zj3mfWbrtNVLZpYur3nftL87fN7LFXUb1tx9c459a rxFtmL83I5SFgYxLgZZMUWWTR/yLizxCv26YP6LbTBzWJlAhjBwcQrARJZ2MPwVNi99MWHhQY+u B6cuBslfuvJ/o2nCqvkNerWt36IctcodGRnuyivvnf3Z/PPcqwl1D68c5srj17sU8N658O16w/s HH27kAQA= X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.105.4.254; envelope-from=fustini@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1770102277838154100 Bump PPTT table revision to 3 which corresponds to ACPI 6.4. A new field was added to the end of PPTT for the Cache ID. Ensure the Cache ID Valid bit is set in the flags. HACK: cluster_id is not set by the riscv arch so force setting it. Divide the cores between the number of clusters. For the CBQRI example, cores 0-3 are cluster 0 and cores 4-8 are cluster 1. The proper solution is for the riscv code to set cluster_id the same way as the arm code. HACK: cluster 0 uses the first L2 cache controller and cluster 1 uses the second L2 cache controller. A more general solution is to make the L2 cache private to the cluster and not private to the core. The series "[PATCH v8 0/6] Specifying cache topology on ARM" looks to be the correct approach. RISC-V support could be based on this. Link: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/05_ACPI_Software_Progra= mming_Model/ACPI_Software_Programming_Model.html#cache-type-structure-table Link: https://lore.kernel.org/all/20250310162337.844-1-alireza.sanaee@huawe= i.com/ Signed-off-by: Drew Fustini --- hw/acpi/aml-build.c | 57 +++++++++++++++++++++++++++++++++++++++++++------= ---- 1 file changed, 47 insertions(+), 10 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 742e7a6eb261..7c23b0413f5e 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2148,12 +2148,16 @@ static void build_cache_structure(GArray *tbl, { /* Cache type structure */ build_append_byte(tbl, 1); - /* Length */ - build_append_byte(tbl, 24); + /* + * Length - ACPI 6.4 table 5.140 shows size 28 which increased from + * previous version to include space for the new cache id property + * https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/05_ACPI_Software_Prog= ramming_Model/ACPI_Software_Programming_Model.html#cache-type-structure-tab= le + */ + build_append_byte(tbl, 28); /* Reserved */ build_append_int_noprefix(tbl, 0, 2); - /* Flags */ - build_append_int_noprefix(tbl, 0x7f, 4); + /* Flags - enable bit 7 for Cache ID Valid */ + build_append_int_noprefix(tbl, 0xff, 4); /* Next level cache */ build_append_int_noprefix(tbl, next_level, 4); /* Size */ @@ -2166,6 +2170,8 @@ static void build_cache_structure(GArray *tbl, build_append_byte(tbl, cache_info->attributes); /* Line size */ build_append_int_noprefix(tbl, cache_info->line_size, 2); + /* Cache ID */ + build_append_int_noprefix(tbl, cache_info->id, 4); } =20 /* @@ -2183,9 +2189,13 @@ void build_pptt(GArray *table_data, BIOSLinker *link= er, MachineState *ms, uint32_t pptt_start =3D table_data->len; uint32_t root_offset; uint32_t l3_offset =3D 0, priv_num =3D 0; - uint32_t priv_rsrc[3] =3D {0}; + uint32_t priv_rsrc[4] =3D {0}; int n; - AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 2, + /* + * rev should 3 not 2 based on + * https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/05_ACPI_Software_Prog= ramming_Model/ACPI_Software_Programming_Model.html#processor-properties-top= ology-table-pptt + */ + AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 3, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; =20 acpi_table_begin(&table, table_data); @@ -2209,6 +2219,16 @@ void build_pptt(GArray *table_data, BIOSLinker *link= er, MachineState *ms, * created. */ for (n =3D 0; n < cpus->len; n++) { + /* + * HACK: cluster_id is not set by the riscv arch so force setting = it. + * Divide the cores between the number of clusters. For the CBQRI + * example, cores 0-3 are cluster 0 and cores 4-8 are cluster 1. + * The correct solution is for the riscv code to set cluster_id the + * same way the arm code is doing it. + */ + cpus->cpus[n].props.cluster_id =3D (n / (ms->smp.cores * ms->smp.t= hreads)) + % ms->smp.clusters; + if (cpus->cpus[n].props.socket_id !=3D socket_id) { assert(cpus->cpus[n].props.socket_id > socket_id); socket_id =3D cpus->cpus[n].props.socket_id; @@ -2250,7 +2270,25 @@ void build_pptt(GArray *table_data, BIOSLinker *link= er, MachineState *ms, if (CPUCaches) { /* L2 cache type structure */ priv_rsrc[0] =3D table_data->len - pptt_start; - build_cache_structure(table_data, 0, CPUCaches->l2_cache); + + /* + * HACK: cluster 0 uses the first L2 cache controller and + * cluster 1 uses the second L2 cache controller. A more + * general solution is to make the L2 cache private to + * the cluster and not private to the core. + * + * This series seems to be the correct direction: + * https://lore.kernel.org/all/20250310162337.844-1-alireza.sa= naee@huawei.com/ + * but it is only adding support for ARM so it needs to + * be broaden to support RISC-V too + */ + if (cluster_id =3D=3D 0) { + build_cache_structure(table_data, l3_offset, + CPUCaches->l2_cluster1_cache); + } else { + build_cache_structure(table_data, l3_offset, + CPUCaches->l2_cluster2_cache); + } =20 /* L1d cache type structure */ priv_rsrc[1] =3D table_data->len - pptt_start; @@ -2261,14 +2299,13 @@ void build_pptt(GArray *table_data, BIOSLinker *lin= ker, MachineState *ms, priv_rsrc[2] =3D table_data->len - pptt_start; build_cache_structure(table_data, priv_rsrc[0], CPUCaches->l1i_cache); - - priv_num =3D 3; + priv_num =3D 2; } if (ms->smp.threads =3D=3D 1) { build_processor_hierarchy_node(table_data, (1 << 1) | /* ACPI Processor ID valid */ (1 << 3), /* Node is a Leaf */ - cluster_offset, n, priv_rsrc, priv_num); + cluster_offset, n, &priv_rsrc[1], priv_num); } else { if (cpus->cpus[n].props.core_id !=3D core_id) { assert(cpus->cpus[n].props.core_id > core_id); --=20 2.43.0 From nobody Sun Feb 8 23:58:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1770102363; cv=none; d=zohomail.com; s=zohoarc; b=Jk9Ay6YgdGQ37a9QyZQ/Sfqkc4A/2a1HEQbc6tYepIjtcvMRpNG8TIire7uGAz/kdoYRmG4XVHsQ1bUKWJ3LK8wePcMXP6rKMa8clrbIEP7kp04FWMxFNDqHavgZ/hhvBtVGgISfzRYrrwic/GK8Zx/59380PzZdBRNufOWIE7I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770102363; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 03 Feb 2026 02:03:51 -0500 Received: from tor.source.kernel.org ([172.105.4.254]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnARw-0003G9-Kc; Tue, 03 Feb 2026 02:03:50 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id EF02160147; Tue, 3 Feb 2026 07:03:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60006C2BC86; Tue, 3 Feb 2026 07:03:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770102218; bh=i8kqSXew10HQoZsEqPOWNA6a2DuzT5eQ35FVRfqpxRA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jZBKi8SYFtHS02tLdaaVs6CbzZBqxtz9VIioHVVYFT+9jSOV5gmP8iHDsp3yWOsyh 91skd+PqVzGPISH30m1HiZ74IT5dnyVOaj2oR8eihh2HJzF3HBbnDQb19fT95SXh+8 1D5qvzmB3EIdALCpK/S6/aE+ggJThFSDdcn4t3dtze/k4yuMrQVwBpiKogH2ECsrkY HhWx0GdqM5bJR7ZzcUUeK/2fRxCiC4lIrXz5BqAJEiEsXIey1cuK0vn5uTjCkzo7Um 9DN2oRhLfOa76a39ff93cesGwUaLoJZbxYmaV/5FRsvjF4uAjnkraVxL02vhaIaQso sJSpPA/vmPTtA== From: Drew Fustini Date: Mon, 02 Feb 2026 23:01:23 -0800 Subject: [PATCH RFC 7/7] hw/riscv: virt-acpi-build: Build PPTT table before RQSC table MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-riscv-rqsc-v1-7-dcf448a3ed73@kernel.org> References: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> In-Reply-To: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Sunil V L , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Peter Maydell , Sia Jee Heng , qemu-arm@nongnu.org, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1025; i=fustini@kernel.org; h=from:subject:message-id; bh=i8kqSXew10HQoZsEqPOWNA6a2DuzT5eQ35FVRfqpxRA=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWQ2zj2WftTi/tTFT1JV7bZkx9el1qd6XJcVCwp2fHLE7 JdGx96DHaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJbD7JyPBAfKXdgvYbbJ8i +f6/2c2wedbPu8d8K751b37VdOnYr523GRneONfXewlaiq7kXyPnLPwt7dqjnasjmhLtZPcr3ug 03M0BAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.105.4.254; envelope-from=fustini@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1770104005468158500 RQSC table will reference cache IDs in PPTT so PPTT must be built first. Signed-off-by: Drew Fustini --- hw/riscv/virt-acpi-build.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index da3c355427af..ce2283d79f67 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -1068,13 +1068,13 @@ static void virt_acpi_build(RISCVVirtState *s, Acpi= BuildTables *tables) spcr_setup(tables_blob, tables->linker, s); } =20 - acpi_add_table(table_offsets, tables_blob); - build_rqsc(tables_blob, tables->linker, s); - acpi_add_table(table_offsets, tables_blob); pptt_setup(tables_blob, tables->linker, ms, s->oem_id, s->oem_table_id); =20 + acpi_add_table(table_offsets, tables_blob); + build_rqsc(tables_blob, tables->linker, s); + acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg =3D { --=20 2.43.0