setup_2d_blt_ctx is responsible for knowing how to retrieve the state
needed by ati_2d_blt from the registers and assigning it to the ATI2DCtx.
This will be useful in a future patch when HOST_DATA needs to make small
modifications to the ctx.

Signed-off-by: Chad Jablonski <chad@jablonski.xyz>
---
 hw/display/ati_2d.c | 71 +++++++++++++++++++++++++--------------------
 1 file changed, 39 insertions(+), 32 deletions(-)

diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c
index bc41ad37f6..4c55898e9a 100644
--- a/hw/display/ati_2d.c
+++ b/hw/display/ati_2d.c
@@ -25,7 +25,7 @@
  * possible.
  */
 
-static int ati_bpp_from_datatype(ATIVGAState *s)
+static int ati_bpp_from_datatype(const ATIVGAState *s)
 {
     switch (s->regs.dp_datatype & 0xf) {
     case 2:
@@ -64,6 +64,43 @@ typedef struct {
     const uint8_t *src_bits;
 } ATI2DCtx;
 
+static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx)
+{
+    ctx->bpp = ati_bpp_from_datatype(s);
+    ctx->rop3 = s->regs.dp_mix & GMC_ROP3_MASK;
+    ctx->left_to_right = s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT;
+    ctx->top_to_bottom = s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM;
+    ctx->frgd_clr = s->regs.dp_brush_frgd_clr;
+    ctx->palette = s->vga.palette;
+    ctx->vram_end = s->vga.vram_ptr + s->vga.vram_size;
+
+    /* dst */
+    ctx->dst.width = s->regs.dst_width;
+    ctx->dst.height = s->regs.dst_height;
+    ctx->dst.x = (ctx->left_to_right ?
+                 s->regs.dst_x : s->regs.dst_x + 1 - ctx->dst.width);
+    ctx->dst.y = (ctx->top_to_bottom ?
+                 s->regs.dst_y : s->regs.dst_y + 1 - ctx->dst.height);
+    ctx->dst_stride = s->regs.dst_pitch;
+    ctx->dst_bits = s->vga.vram_ptr + s->regs.dst_offset;
+    if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+        ctx->dst_bits += s->regs.crtc_offset & 0x07ffffff;
+        ctx->dst_stride *= ctx->bpp;
+    }
+
+    /* src */
+    ctx->src.x = (ctx->left_to_right ?
+                 s->regs.src_x : s->regs.src_x + 1 - ctx->dst.width);
+    ctx->src.y = (ctx->top_to_bottom ?
+                 s->regs.src_y : s->regs.src_y + 1 - ctx->dst.height);
+    ctx->src_stride = s->regs.src_pitch;
+    ctx->src_bits = s->vga.vram_ptr + s->regs.src_offset;
+    if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
+        ctx->src_bits += s->regs.crtc_offset & 0x07ffffff;
+        ctx->src_stride *= ctx->bpp;
+    }
+}
+
 void ati_2d_blt(ATIVGAState *s)
 {
     /* FIXME it is probably more complex than this and may need to be */
@@ -72,40 +109,21 @@ void ati_2d_blt(ATIVGAState *s)
     bool use_pixman_fill = s->use_pixman & BIT(0);
     bool use_pixman_blt = s->use_pixman & BIT(1);
     ATI2DCtx ctx;
-    ctx.rop3 = s->regs.dp_mix & GMC_ROP3_MASK;
-    ctx.left_to_right = s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT;
-    ctx.top_to_bottom = s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM;
-    ctx.frgd_clr = s->regs.dp_brush_frgd_clr;
-    ctx.palette = s->vga.palette;
+    setup_2d_blt_ctx(s, &ctx);
     DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
             s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
             surface_bits_per_pixel(ds),
             ctx.rop3 >> 16);
     unsigned dst_offset = s->regs.dst_offset;
-    ctx.dst.width = s->regs.dst_width;
-    ctx.dst.height = s->regs.dst_height;
-    ctx.dst.x = (ctx.left_to_right ?
-                s->regs.dst_x : s->regs.dst_x + 1 - ctx.dst.width);
-    ctx.dst.y = (ctx.top_to_bottom ?
-                s->regs.dst_y : s->regs.dst_y + 1 - ctx.dst.height);
-    ctx.bpp = ati_bpp_from_datatype(s);
     if (!ctx.bpp) {
         qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n");
         return;
     }
-    ctx.dst_stride = s->regs.dst_pitch;
     if (!ctx.dst_stride) {
         qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n");
         return;
     }
-    ctx.dst_bits = s->vga.vram_ptr + dst_offset;
-
-    if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
-        ctx.dst_bits += s->regs.crtc_offset & 0x07ffffff;
-        ctx.dst_stride *= ctx.bpp;
-    }
     int dst_stride_words = ctx.dst_stride / sizeof(uint32_t);
-    ctx.vram_end = s->vga.vram_ptr + s->vga.vram_size;
     if (ctx.dst.x > 0x3fff || ctx.dst.y > 0x3fff || ctx.dst_bits >= ctx.vram_end
         || ctx.dst_bits + ctx.dst.x
          + (ctx.dst.y + ctx.dst.height) * ctx.dst_stride >= ctx.vram_end) {
@@ -123,21 +141,10 @@ void ati_2d_blt(ATIVGAState *s)
     case ROP3_SRCCOPY:
     {
         bool fallback = false;
-        ctx.src.x = (ctx.left_to_right ?
-                    s->regs.src_x : s->regs.src_x + 1 - ctx.dst.width);
-        ctx.src.y = (ctx.top_to_bottom ?
-                    s->regs.src_y : s->regs.src_y + 1 - ctx.dst.height);
-        ctx.src_stride = s->regs.src_pitch;
         if (!ctx.src_stride) {
             qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n");
             return;
         }
-        ctx.src_bits = s->vga.vram_ptr + s->regs.src_offset;
-
-        if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
-            ctx.src_bits += s->regs.crtc_offset & 0x07ffffff;
-            ctx.src_stride *= ctx.bpp;
-        }
         int src_stride_words = ctx.src_stride / sizeof(uint32_t);
         if (ctx.src.x > 0x3fff || ctx.src.y > 0x3fff
             || ctx.src_bits >= ctx.vram_end
-- 
2.52.0