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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=202.12.124.147; envelope-from=chad@jablonski.xyz; helo=fout-b4-smtp.messagingengine.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.499, PDS_OTHER_BAD_TLD=1.999, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1769784674163154100 Content-Type: text/plain; charset="utf-8" setup_2d_blt_ctx is responsible for knowing how to retrieve the state needed by ati_2d_blt from the registers and assigning it to the ATI2DCtx. This will be useful in a future patch when HOST_DATA needs to make small modifications to the ctx. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 71 +++++++++++++++++++++++++-------------------- 1 file changed, 39 insertions(+), 32 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index bc41ad37f6..4c55898e9a 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -25,7 +25,7 @@ * possible. */ =20 -static int ati_bpp_from_datatype(ATIVGAState *s) +static int ati_bpp_from_datatype(const ATIVGAState *s) { switch (s->regs.dp_datatype & 0xf) { case 2: @@ -64,6 +64,43 @@ typedef struct { const uint8_t *src_bits; } ATI2DCtx; =20 +static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx) +{ + ctx->bpp =3D ati_bpp_from_datatype(s); + ctx->rop3 =3D s->regs.dp_mix & GMC_ROP3_MASK; + ctx->left_to_right =3D s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT; + ctx->top_to_bottom =3D s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM; + ctx->frgd_clr =3D s->regs.dp_brush_frgd_clr; + ctx->palette =3D s->vga.palette; + ctx->vram_end =3D s->vga.vram_ptr + s->vga.vram_size; + + /* dst */ + ctx->dst.width =3D s->regs.dst_width; + ctx->dst.height =3D s->regs.dst_height; + ctx->dst.x =3D (ctx->left_to_right ? + s->regs.dst_x : s->regs.dst_x + 1 - ctx->dst.width); + ctx->dst.y =3D (ctx->top_to_bottom ? + s->regs.dst_y : s->regs.dst_y + 1 - ctx->dst.height); + ctx->dst_stride =3D s->regs.dst_pitch; + ctx->dst_bits =3D s->vga.vram_ptr + s->regs.dst_offset; + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { + ctx->dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; + ctx->dst_stride *=3D ctx->bpp; + } + + /* src */ + ctx->src.x =3D (ctx->left_to_right ? + s->regs.src_x : s->regs.src_x + 1 - ctx->dst.width); + ctx->src.y =3D (ctx->top_to_bottom ? + s->regs.src_y : s->regs.src_y + 1 - ctx->dst.height); + ctx->src_stride =3D s->regs.src_pitch; + ctx->src_bits =3D s->vga.vram_ptr + s->regs.src_offset; + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { + ctx->src_bits +=3D s->regs.crtc_offset & 0x07ffffff; + ctx->src_stride *=3D ctx->bpp; + } +} + void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -72,40 +109,21 @@ void ati_2d_blt(ATIVGAState *s) bool use_pixman_fill =3D s->use_pixman & BIT(0); bool use_pixman_blt =3D s->use_pixman & BIT(1); ATI2DCtx ctx; - ctx.rop3 =3D s->regs.dp_mix & GMC_ROP3_MASK; - ctx.left_to_right =3D s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT; - ctx.top_to_bottom =3D s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM; - ctx.frgd_clr =3D s->regs.dp_brush_frgd_clr; - ctx.palette =3D s->vga.palette; + setup_2d_blt_ctx(s, &ctx); DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), ctx.rop3 >> 16); unsigned dst_offset =3D s->regs.dst_offset; - ctx.dst.width =3D s->regs.dst_width; - ctx.dst.height =3D s->regs.dst_height; - ctx.dst.x =3D (ctx.left_to_right ? - s->regs.dst_x : s->regs.dst_x + 1 - ctx.dst.width); - ctx.dst.y =3D (ctx.top_to_bottom ? - s->regs.dst_y : s->regs.dst_y + 1 - ctx.dst.height); - ctx.bpp =3D ati_bpp_from_datatype(s); if (!ctx.bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; } - ctx.dst_stride =3D s->regs.dst_pitch; if (!ctx.dst_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); return; } - ctx.dst_bits =3D s->vga.vram_ptr + dst_offset; - - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - ctx.dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; - ctx.dst_stride *=3D ctx.bpp; - } int dst_stride_words =3D ctx.dst_stride / sizeof(uint32_t); - ctx.vram_end =3D s->vga.vram_ptr + s->vga.vram_size; if (ctx.dst.x > 0x3fff || ctx.dst.y > 0x3fff || ctx.dst_bits >=3D ctx.= vram_end || ctx.dst_bits + ctx.dst.x + (ctx.dst.y + ctx.dst.height) * ctx.dst_stride >=3D ctx.vram_end= ) { @@ -123,21 +141,10 @@ void ati_2d_blt(ATIVGAState *s) case ROP3_SRCCOPY: { bool fallback =3D false; - ctx.src.x =3D (ctx.left_to_right ? - s->regs.src_x : s->regs.src_x + 1 - ctx.dst.width); - ctx.src.y =3D (ctx.top_to_bottom ? - s->regs.src_y : s->regs.src_y + 1 - ctx.dst.height); - ctx.src_stride =3D s->regs.src_pitch; if (!ctx.src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); return; } - ctx.src_bits =3D s->vga.vram_ptr + s->regs.src_offset; - - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - ctx.src_bits +=3D s->regs.crtc_offset & 0x07ffffff; - ctx.src_stride *=3D ctx.bpp; - } int src_stride_words =3D ctx.src_stride / sizeof(uint32_t); if (ctx.src.x > 0x3fff || ctx.src.y > 0x3fff || ctx.src_bits >=3D ctx.vram_end --=20 2.52.0