This commit adds SCU register support for TSP SDRAM remap control and runtime
activation. Unlike SSP, the TSP does not support configurable target address remapping
through SCU registers. It only supports setting the PSP DRAM base and size, which
are then aliased into the TSP-visible SDRAM window.

coprocessor_sdram_remap[2]: maps PSP DRAM offset 0x42E000000 (size: 32MB) to TSP SDRAM
      offset 0x0

The SCU registers AST2700_SCU_TSP_CTRL_1 and
AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base (alias offset)
and mapping size.

|------------------------------------------|         |----------------------------|
|               PSP DRAM                   |         |        TSP SDRAM           |
|------------------------------------------|         |----------------------------|
| 0x42E0_0000_0 (SCU_168 << 4)             |         | 0x0000_0000                |
|   remap base                             |------>  |  - fixed target addr       |
|   size: 32MB    (SCU_194)                |         |                            |
|------------------------------------------|         |----------------------------|

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_scu.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 333fa964d3..a551063c03 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -159,6 +159,8 @@
 #define AST2700_SSP_TSP_RST_RB          BIT(8)
 #define AST2700_SSP_TSP_RST_HOLD_RB     BIT(9)
 #define AST2700_SSP_TSP_RST_SRC_RB      BIT(10)
+#define AST2700_SCU_TSP_CTRL_1          TO_REG(0x168)
+#define AST2700_SCU_TSP_REMAP_SIZE_2    TO_REG(0x194)
 #define AST2700_SCU_SYS_RST_CTRL_1      TO_REG(0x200)
 #define AST2700_SCU_SYS_RST_CLR_1       TO_REG(0x204)
 #define AST2700_SCU_SYS_RST_SSP         BIT(30)
@@ -1088,6 +1090,23 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
         data &= 0x3fffffff;
         memory_region_set_size(mr, data);
         break;
+    case AST2700_SCU_TSP_CTRL_1:
+        mr = &s->dram_remap_alias[2];
+        if (s->tsp_cpuid < 0 || mr == NULL) {
+            return;
+        }
+        data &= 0x7fffffff;
+        memory_region_set_alias_offset(mr,
+                                       ((uint64_t) data << 4) & 0x3ffffffff);
+        break;
+    case AST2700_SCU_TSP_REMAP_SIZE_2:
+        mr = &s->dram_remap_alias[2];
+        if (s->tsp_cpuid < 0 || mr == NULL) {
+            return;
+        }
+        data &= 0x3fffffff;
+        memory_region_set_size(mr, data);
+        break;
     case AST2700_SCU_SYS_RST_CTRL_1:
         if (s->ssp_cpuid < 0) {
             return;
@@ -1165,6 +1184,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
     [AST2700_SCU_SSP_REMAP_ADDR_2]  = 0x00000000,
     [AST2700_SCU_SSP_REMAP_SIZE_2]  = 0x02000000,
     [AST2700_SCU_TSP_CTRL_0]        = 0x000007FE,
+    [AST2700_SCU_TSP_CTRL_1]        = 0x42E00000,
+    [AST2700_SCU_TSP_REMAP_SIZE_2]  = 0x02000000,
     [AST2700_SCU_SYS_RST_CTRL_1]    = 0xFFC37FDC,
     [AST2700_SCU_SYS_RST_CTRL_2]    = 0x00001FFF,
     [AST2700_SCU_HPLL_PARAM]        = 0x0000009f,
@@ -1205,6 +1226,8 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
 
     if (s->tsp_cpuid > 0) {
         arm_set_cpu_off(s->tsp_cpuid);
+        memory_region_set_alias_offset(&s->dram_remap_alias[2], 0x2e000000);
+        memory_region_set_size(&s->dram_remap_alias[2], 32 * MiB);
     }
 }
 
-- 
2.43.0