From nobody Mon Feb 9 08:57:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1769506379; cv=none; d=zohomail.com; s=zohoarc; b=KyFfuOM0kTjja+lC3jDvB2stjaEKxlUOAREBCVuu+lPPgCyMISzH40Wc68Uabq/AS/wOaipEuWe9055+mIz7Qzm/5y+yvI0OOVKWHxQZr9CSATj8QNuFEnCi79sNWowD44Fv8/TyyZXhapyYC7Hi8kXhWELQ+SfOFC0bURf0M1Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769506379; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=thCfHYMRKnRPNAMi5MfaVOJL1a/kziMB1EUuMRINwN4=; b=lzXq3Bzi3verizZXzFZj+Pxh4WmdfukCgeE7CvEMEt1pinABFixBaQtPEwZ/+KQKMvtASbFbZ4grdjZEG5b6buQHkD0GQU/9Xd9j8VHt9BO/Rh83SADPFtLnt00leDApC/dRtJlcdqSxtzJbcgoOiVeFXNSpfgDCIqGTkTi2k80= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769506379755806.7612754041553; Tue, 27 Jan 2026 01:32:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vkfPV-0004cB-VS; Tue, 27 Jan 2026 04:30:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkfPT-0004SJ-KH; Tue, 27 Jan 2026 04:30:56 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vkfPS-0005A1-3J; Tue, 27 Jan 2026 04:30:55 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 27 Jan 2026 17:29:46 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 27 Jan 2026 17:29:46 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 09/11] hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap Date: Tue, 27 Jan 2026 17:29:38 +0800 Message-ID: <20260127092943.3731635-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260127092943.3731635-1-jamin_lin@aspeedtech.com> References: <20260127092943.3731635-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1769506380474158500 Content-Type: text/plain; charset="utf-8" This commit adds SCU register support for TSP SDRAM remap control and runti= me activation. Unlike SSP, the TSP does not support configurable target addres= s remapping through SCU registers. It only supports setting the PSP DRAM base and size,= which are then aliased into the TSP-visible SDRAM window. coprocessor_sdram_remap[2]: maps PSP DRAM offset 0x42E000000 (size: 32MB) t= o TSP SDRAM offset 0x0 The SCU registers AST2700_SCU_TSP_CTRL_1 and AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base= (alias offset) and mapping size. |------------------------------------------| |---------------------= -------| | PSP DRAM | | TSP SDRAM = | |------------------------------------------| |---------------------= -------| | 0x42E0_0000_0 (SCU_168 << 4) | | 0x0000_0000 = | | remap base |------> | - fixed target addr= | | size: 32MB (SCU_194) | | = | |------------------------------------------| |---------------------= -------| Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 333fa964d3..a551063c03 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -159,6 +159,8 @@ #define AST2700_SSP_TSP_RST_RB BIT(8) #define AST2700_SSP_TSP_RST_HOLD_RB BIT(9) #define AST2700_SSP_TSP_RST_SRC_RB BIT(10) +#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168) +#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194) #define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200) #define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204) #define AST2700_SCU_SYS_RST_SSP BIT(30) @@ -1088,6 +1090,23 @@ static void aspeed_ast2700_scu_write(void *opaque, h= waddr offset, data &=3D 0x3fffffff; memory_region_set_size(mr, data); break; + case AST2700_SCU_TSP_CTRL_1: + mr =3D &s->dram_remap_alias[2]; + if (s->tsp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x7fffffff; + memory_region_set_alias_offset(mr, + ((uint64_t) data << 4) & 0x3fffffff= f); + break; + case AST2700_SCU_TSP_REMAP_SIZE_2: + mr =3D &s->dram_remap_alias[2]; + if (s->tsp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x3fffffff; + memory_region_set_size(mr, data); + break; case AST2700_SCU_SYS_RST_CTRL_1: if (s->ssp_cpuid < 0) { return; @@ -1165,6 +1184,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST270= 0_SCU_NR_REGS] =3D { [AST2700_SCU_SSP_REMAP_ADDR_2] =3D 0x00000000, [AST2700_SCU_SSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_TSP_CTRL_0] =3D 0x000007FE, + [AST2700_SCU_TSP_CTRL_1] =3D 0x42E00000, + [AST2700_SCU_TSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC, [AST2700_SCU_SYS_RST_CTRL_2] =3D 0x00001FFF, [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f, @@ -1205,6 +1226,8 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev) =20 if (s->tsp_cpuid > 0) { arm_set_cpu_off(s->tsp_cpuid); + memory_region_set_alias_offset(&s->dram_remap_alias[2], 0x2e000000= ); + memory_region_set_size(&s->dram_remap_alias[2], 32 * MiB); } } =20 --=20 2.43.0