This commit adds SCU register support for SSP SDRAM remap control and runtime
activation. It introduces logic for the PSP to dynamically configure the mapping
of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory
communication via memory region aliases.

- coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x400000000 (size: 32MB) to SSP SDRAM
    offset 0x2000000
- coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x42c000000 (size: 32MB) to SSP SDRAM
    offset 0x0

The SCU registers AST2700_SCU_SSP_CTRL_1/2 and
AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfiguration
of alias offset, base, and size.

|------------------------------------------|         |----------------------------|
|               PSP DRAM                   |         |        SSP SDRAM           |
|------------------------------------------|         |----------------------------|
| 0x4_0000_0000 (SCU_124 << 4)             |     --> | 0x0000_0000                |
|   remap1 base                            |---| |   |  - SCU_150: target addr    |
|   size: 32MB    (SCU_14C)                |   | |   |    remap2                  |
|------------------------------------------|   | |   |----------------------------|
|                                          |   | |   |                            |
| 0x4_2C00_0000 (SCU_128 << 4)             |-----|   | 0x0200_0000                |
|   remap2 base                            |   |     |  - SCU_148: target addr    |
|   size: 32MB    (SCU_154)                |   |---> |    remap1                  |
|------------------------------------------|         |----------------------------|

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_scu.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 6aebdd630f..27591f53c4 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -147,6 +147,12 @@
 
 /* SSP TSP */
 #define AST2700_SCU_SSP_CTRL_0          TO_REG(0x120)
+#define AST2700_SCU_SSP_CTRL_1          TO_REG(0x124)
+#define AST2700_SCU_SSP_CTRL_2          TO_REG(0x128)
+#define AST2700_SCU_SSP_REMAP_ADDR_1    TO_REG(0x148)
+#define AST2700_SCU_SSP_REMAP_SIZE_1    TO_REG(0x14C)
+#define AST2700_SCU_SSP_REMAP_ADDR_2    TO_REG(0x150)
+#define AST2700_SCU_SSP_REMAP_SIZE_2    TO_REG(0x154)
 #define AST2700_SCU_TSP_CTRL_0          TO_REG(0x160)
 #define AST2700_SSP_TSP_ENABLE          BIT(0)
 #define AST2700_SSP_TSP_RST             BIT(1)
@@ -993,6 +999,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
                                      uint64_t data64, unsigned size)
 {
     AspeedSCUState *s = ASPEED_SCU(opaque);
+    MemoryRegion *mr = NULL;
     int reg = TO_REG(offset);
     /* Truncate here so bitwise operations below behave as expected */
     uint32_t data = data64;
@@ -1050,6 +1057,37 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
         data &= ~AST2700_SSP_TSP_ENABLE;
         s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
         return;
+    case AST2700_SCU_SSP_CTRL_1:
+    case AST2700_SCU_SSP_CTRL_2:
+        mr = (reg == AST2700_SCU_SSP_CTRL_1) ?
+            &s->dram_remap_alias[0] : &s->dram_remap_alias[1];
+        if (s->ssp_cpuid < 0 || mr == NULL) {
+            return;
+        }
+        data &= 0x7fffffff;
+        memory_region_set_alias_offset(mr,
+                                       ((uint64_t) data << 4) & 0x3ffffffff);
+        break;
+    case AST2700_SCU_SSP_REMAP_ADDR_1:
+    case AST2700_SCU_SSP_REMAP_ADDR_2:
+        mr = (reg == AST2700_SCU_SSP_REMAP_ADDR_1) ?
+            &s->dram_remap_alias[0] : &s->dram_remap_alias[1];
+        if (s->ssp_cpuid < 0 || mr == NULL) {
+            return;
+        }
+        data &= 0x3fffffff;
+        memory_region_set_address(mr, data);
+        break;
+    case AST2700_SCU_SSP_REMAP_SIZE_1:
+    case AST2700_SCU_SSP_REMAP_SIZE_2:
+        mr = (reg == AST2700_SCU_SSP_REMAP_SIZE_1) ?
+            &s->dram_remap_alias[0] : &s->dram_remap_alias[1];
+        if (s->ssp_cpuid < 0 || mr == NULL) {
+            return;
+        }
+        data &= 0x3fffffff;
+        memory_region_set_size(mr, data);
+        break;
     case AST2700_SCU_SYS_RST_CTRL_1:
         if (s->ssp_cpuid < 0) {
             return;
@@ -1120,6 +1158,12 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
     [AST2700_HW_STRAP1_SEC2]        = 0x00000000,
     [AST2700_HW_STRAP1_SEC3]        = 0x1000408F,
     [AST2700_SCU_SSP_CTRL_0]        = 0x000007FE,
+    [AST2700_SCU_SSP_CTRL_1]        = 0x40000000,
+    [AST2700_SCU_SSP_CTRL_2]        = 0x42C00000,
+    [AST2700_SCU_SSP_REMAP_ADDR_1]  = 0x02000000,
+    [AST2700_SCU_SSP_REMAP_SIZE_1]  = 0x02000000,
+    [AST2700_SCU_SSP_REMAP_ADDR_2]  = 0x00000000,
+    [AST2700_SCU_SSP_REMAP_SIZE_2]  = 0x02000000,
     [AST2700_SCU_TSP_CTRL_0]        = 0x000007FE,
     [AST2700_SCU_SYS_RST_CTRL_1]    = 0xFFC37FDC,
     [AST2700_SCU_SYS_RST_CTRL_2]    = 0x00001FFF,
@@ -1151,6 +1195,12 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
 
     if (s->ssp_cpuid > 0) {
         arm_set_cpu_off(s->ssp_cpuid);
+        memory_region_set_address(&s->dram_remap_alias[0], 32 * MiB);
+        memory_region_set_alias_offset(&s->dram_remap_alias[0], 0);
+        memory_region_set_size(&s->dram_remap_alias[0], 32 * MiB);
+        memory_region_set_address(&s->dram_remap_alias[1], 0);
+        memory_region_set_alias_offset(&s->dram_remap_alias[1], 0x2c000000);
+        memory_region_set_size(&s->dram_remap_alias[1], 32 * MiB);
     }
 
     if (s->tsp_cpuid > 0) {
-- 
2.43.0