From nobody Mon Feb 9 07:55:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768901608; cv=none; d=zohomail.com; s=zohoarc; b=Jn1ohYZNfsNQRatW537wiJlwUUQedNKlDsXT30rQJKDAvaldLt1w64eiFWyGdjHQDsnshFWj+Z/gAvTDnZOrlBGRFOHUhGGss0QVOGpoihNiUvwumI71UsxDjJ9GGkSlC0t/vd8R9IXl515x+qcZ70ZFXYlQbdOJRb8IVyIF8ko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768901608; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=mhUkGxsC8pXYeb+L2fC6THZe6LNIn/MtQL6bMw5m8y0=; b=esdrrS32LqA45IwGZqB8hOpwPwr4U1kWqHjANlAPITgfP4Lfn17lL/fwVEpfbOmvneQkCt/Q61mOGenuMewo323kzUvaeKEbXKrJlnXoFPAS9SPRjp1S1PFdtg2IFB9ExMfeAck9yIsopfsSjzPyJvCtZRp/3MHawIPBJR4K+94= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768901608567576.9272280623942; Tue, 20 Jan 2026 01:33:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vi83v-0003sC-Ls; Tue, 20 Jan 2026 04:30:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83u-0003pM-95; Tue, 20 Jan 2026 04:30:10 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi83s-0005eG-Io; Tue, 20 Jan 2026 04:30:09 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 17:29:41 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 17:29:41 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Date: Tue, 20 Jan 2026 17:29:33 +0800 Message-ID: <20260120092939.2708302-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> References: <20260120092939.2708302-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768901610992154100 Content-Type: text/plain; charset="utf-8" This commit adds SCU register support for SSP SDRAM remap control and runti= me activation. It introduces logic for the PSP to dynamically configure the ma= pping of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory communication via memory region aliases. - coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x400000000 (size: 32MB)= to SSP SDRAM offset 0x2000000 - coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x42c000000 (size: 32MB)= to SSP SDRAM offset 0x0 The SCU registers AST2700_SCU_SSP_CTRL_1/2 and AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfigu= ration of alias offset, base, and size. |------------------------------------------| |---------------------= -------| | PSP DRAM | | SSP SDRAM = | |------------------------------------------| |---------------------= -------| | 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 = | | remap1 base |---| | | - SCU_150: target a= ddr | | size: 32MB (SCU_14C) | | | | remap2 = | |------------------------------------------| | | |---------------------= -------| | | | | | = | | 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x0200_0000 = | | remap2 base | | | - SCU_148: target a= ddr | | size: 32MB (SCU_154) | |---> | remap1 = | |------------------------------------------| |---------------------= -------| Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 50 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 6aebdd630f..27591f53c4 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -147,6 +147,12 @@ =20 /* SSP TSP */ #define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120) +#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124) +#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128) +#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148) +#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14C) +#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150) +#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154) #define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160) #define AST2700_SSP_TSP_ENABLE BIT(0) #define AST2700_SSP_TSP_RST BIT(1) @@ -993,6 +999,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwad= dr offset, uint64_t data64, unsigned size) { AspeedSCUState *s =3D ASPEED_SCU(opaque); + MemoryRegion *mr =3D NULL; int reg =3D TO_REG(offset); /* Truncate here so bitwise operations below behave as expected */ uint32_t data =3D data64; @@ -1050,6 +1057,37 @@ static void aspeed_ast2700_scu_write(void *opaque, h= waddr offset, data &=3D ~AST2700_SSP_TSP_ENABLE; s->regs[reg] =3D (s->regs[reg] & ~0xff) | (data & 0xff); return; + case AST2700_SCU_SSP_CTRL_1: + case AST2700_SCU_SSP_CTRL_2: + mr =3D (reg =3D=3D AST2700_SCU_SSP_CTRL_1) ? + &s->dram_remap_alias[0] : &s->dram_remap_alias[1]; + if (s->ssp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x7fffffff; + memory_region_set_alias_offset(mr, + ((uint64_t) data << 4) & 0x3fffffff= f); + break; + case AST2700_SCU_SSP_REMAP_ADDR_1: + case AST2700_SCU_SSP_REMAP_ADDR_2: + mr =3D (reg =3D=3D AST2700_SCU_SSP_REMAP_ADDR_1) ? + &s->dram_remap_alias[0] : &s->dram_remap_alias[1]; + if (s->ssp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x3fffffff; + memory_region_set_address(mr, data); + break; + case AST2700_SCU_SSP_REMAP_SIZE_1: + case AST2700_SCU_SSP_REMAP_SIZE_2: + mr =3D (reg =3D=3D AST2700_SCU_SSP_REMAP_SIZE_1) ? + &s->dram_remap_alias[0] : &s->dram_remap_alias[1]; + if (s->ssp_cpuid < 0 || mr =3D=3D NULL) { + return; + } + data &=3D 0x3fffffff; + memory_region_set_size(mr, data); + break; case AST2700_SCU_SYS_RST_CTRL_1: if (s->ssp_cpuid < 0) { return; @@ -1120,6 +1158,12 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST27= 00_SCU_NR_REGS] =3D { [AST2700_HW_STRAP1_SEC2] =3D 0x00000000, [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F, [AST2700_SCU_SSP_CTRL_0] =3D 0x000007FE, + [AST2700_SCU_SSP_CTRL_1] =3D 0x40000000, + [AST2700_SCU_SSP_CTRL_2] =3D 0x42C00000, + [AST2700_SCU_SSP_REMAP_ADDR_1] =3D 0x02000000, + [AST2700_SCU_SSP_REMAP_SIZE_1] =3D 0x02000000, + [AST2700_SCU_SSP_REMAP_ADDR_2] =3D 0x00000000, + [AST2700_SCU_SSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_TSP_CTRL_0] =3D 0x000007FE, [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC, [AST2700_SCU_SYS_RST_CTRL_2] =3D 0x00001FFF, @@ -1151,6 +1195,12 @@ static void aspeed_ast2700_scu_reset(DeviceState *de= v) =20 if (s->ssp_cpuid > 0) { arm_set_cpu_off(s->ssp_cpuid); + memory_region_set_address(&s->dram_remap_alias[0], 32 * MiB); + memory_region_set_alias_offset(&s->dram_remap_alias[0], 0); + memory_region_set_size(&s->dram_remap_alias[0], 32 * MiB); + memory_region_set_address(&s->dram_remap_alias[1], 0); + memory_region_set_alias_offset(&s->dram_remap_alias[1], 0x2c000000= ); + memory_region_set_size(&s->dram_remap_alias[1], 32 * MiB); } =20 if (s->tsp_cpuid > 0) { --=20 2.43.0