include/hw/arm/aspeed_ast1700.h | 55 ++++ include/hw/arm/aspeed_soc.h | 25 +- include/hw/intc/aspeed_intc.h | 2 + include/hw/misc/aspeed_ltpi.h | 33 +++ include/hw/misc/aspeed_pwm.h | 31 ++ hw/arm/aspeed_ast1700.c | 280 ++++++++++++++++++ hw/arm/aspeed_ast27x0.c | 170 ++++++++++- hw/intc/aspeed_intc.c | 60 ++++ hw/misc/aspeed_ltpi.c | 193 ++++++++++++ hw/misc/aspeed_pwm.c | 121 ++++++++ hw/arm/meson.build | 1 + hw/misc/meson.build | 2 + hw/misc/trace-events | 4 + .../functional/aarch64/test_aspeed_ast2700.py | 52 +++- 14 files changed, 999 insertions(+), 30 deletions(-) create mode 100644 include/hw/arm/aspeed_ast1700.h create mode 100644 include/hw/misc/aspeed_ltpi.h create mode 100644 include/hw/misc/aspeed_pwm.h create mode 100644 hw/arm/aspeed_ast1700.c create mode 100644 hw/misc/aspeed_ltpi.c create mode 100644 hw/misc/aspeed_pwm.c
From: Kane-Chen-AS <kane_chen@aspeedtech.com> Hi all, LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM 2.0 specification (see Figure 2): https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf LTPI provides a protocol and physical interface for tunneling various low-speed signals between the Host Processor Module (HPM) and the Satellite Controller Module (SCM). In Figure 2 of the specification, the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to connect to up to two AST1700 boards. On the other side, the AST1700 consolidates HPM FPGA functions and multiple peripheral interfaces (GPIO, UART, I2C, I3C, etc.) onto a single board. Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C, and others), it acts as an I/O expander. Once connected over LTPI, the AST27x0 can control additional downstream devices through this link. This patch series is based on the aspeed_next branch and incorporates recent I2C bus label changes. Ref: https://patchwork.kernel.org/project/qemu-devel/patch/20260112083054.4151945-2-kane_chen@aspeedtech.com/ It introduces a basic LTPI controller model and wires it into the AST27x0 SoC. The series also adds the AST1700-specific LTPI expander device and incrementally connects common peripherals on the AST1700 model. For the I3C block, which may cause kernel crashes, its MMIO region is modeled as an unimplemented device to reserve address space and make the missing functionality explicit, ensuring stable guest probing. In the official release images, the AST1700 functions are not included by default. To test the AST1700-related functionality, please include the following DTS files for probing: https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi0.dtsi https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi1.dtsi After including these DTS files in the BMC image, you can verify LTPI functionality using the following scenarios: 1. In U-Boot: Run the ltpi command to trigger the LTPI connection and display the current connection status. 2. In BMC Linux: Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by the AST1700. Any feedback or suggestions are appreciated! Kane --- ChangeLog --------- v5: - Add functional test case for AST1700 I2C - Corrected the From attribution - Fixed incorrect DRAM setting for SPI and I2C controllers - Refine code structure v4: - Add missing Signed-off-by - Fix checkpatch.pl warnings - Refine code structure - Enable AST1700 support only after all devices are ready v3: - Add PWM model - Integrate the SGPIO model - Fix I2C test case failure - Refine code structure v2: - Separate the AST1700 model into a standalone implementation - Refine the mechanism for assigning the AST1700 board number v1: - Initial version --- Cédric Le Goater (1): hw/misc: Add basic Aspeed PWM model Kane-Chen-AS (21): hw/misc: Add LTPI controller hw/arm/aspeed: Attach LTPI controller to AST27X0 platform hw/arm/aspeed: Add AST1700 LTPI expander device model hw/arm/aspeed: Integrate AST1700 device into AST27X0 hw/arm/aspeed: Integrate interrupt controller for AST1700 hw/arm/aspeed: Attach LTPI controller to AST1700 model hw/arm/aspeed: Attach UART device to AST1700 model hw/arm/aspeed: Attach SRAM device to AST1700 model hw/arm/aspeed: Attach SPI device to AST1700 model hw/arm/aspeed: Attach ADC device to AST1700 model hw/arm/aspeed: Attach SCU device to AST1700 model hw/arm/aspeed: Attach GPIO device to AST1700 model hw/arm/aspeed: Introduce 'bus-label' property for AST1700 SoC hw/arm/aspeed: attach I2C device to AST1700 model hw/arm/aspeed: Attach WDT device to AST1700 model hw/arm/aspeed: Attach PWM device to AST1700 model hw/arm/aspeed: Attach SGPIOM device to AST1700 model hw/arm/aspeed: Model AST1700 I3C block as unimplemented device hw/arm/aspeed: Enable AST1700 IO expander support test/functional/aarch64: Parameterize I2C bus ID in AST2700 test test/functional/aarch64: Add I2C test for AST1700 IO expanders include/hw/arm/aspeed_ast1700.h | 55 ++++ include/hw/arm/aspeed_soc.h | 25 +- include/hw/intc/aspeed_intc.h | 2 + include/hw/misc/aspeed_ltpi.h | 33 +++ include/hw/misc/aspeed_pwm.h | 31 ++ hw/arm/aspeed_ast1700.c | 280 ++++++++++++++++++ hw/arm/aspeed_ast27x0.c | 170 ++++++++++- hw/intc/aspeed_intc.c | 60 ++++ hw/misc/aspeed_ltpi.c | 193 ++++++++++++ hw/misc/aspeed_pwm.c | 121 ++++++++ hw/arm/meson.build | 1 + hw/misc/meson.build | 2 + hw/misc/trace-events | 4 + .../functional/aarch64/test_aspeed_ast2700.py | 52 +++- 14 files changed, 999 insertions(+), 30 deletions(-) create mode 100644 include/hw/arm/aspeed_ast1700.h create mode 100644 include/hw/misc/aspeed_ltpi.h create mode 100644 include/hw/misc/aspeed_pwm.h create mode 100644 hw/arm/aspeed_ast1700.c create mode 100644 hw/misc/aspeed_ltpi.c create mode 100644 hw/misc/aspeed_pwm.c -- 2.43.0
Kane, Jamin, For some reason, I don't receive your proposals anymore. My provider seems to drop silently these emails. Have you changed anything recently ? Thanks, C. On 1/20/26 06:18, Kane Chen via qemu development wrote: > From: Kane-Chen-AS <kane_chen@aspeedtech.com> > > Hi all, > > LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM > 2.0 specification (see Figure 2): > https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf > > LTPI provides a protocol and physical interface for tunneling various > low-speed signals between the Host Processor Module (HPM) and the > Satellite Controller Module (SCM). In Figure 2 of the specification, > the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to > connect to up to two AST1700 boards. On the other side, the AST1700 > consolidates HPM FPGA functions and multiple peripheral interfaces > (GPIO, UART, I2C, I3C, etc.) onto a single board. > > Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C, > and others), it acts as an I/O expander. Once connected over LTPI, > the AST27x0 can control additional downstream devices through this link. > > This patch series is based on the aspeed_next branch and incorporates > recent I2C bus label changes. > Ref: https://patchwork.kernel.org/project/qemu-devel/patch/20260112083054.4151945-2-kane_chen@aspeedtech.com/ > > It introduces a basic LTPI controller model and wires it into the > AST27x0 SoC. The series also adds the AST1700-specific LTPI expander > device and incrementally connects common peripherals on the AST1700 > model. For the I3C block, which may cause kernel crashes, its MMIO > region is modeled as an unimplemented device to reserve address space > and make the missing functionality explicit, ensuring stable guest > probing. > > In the official release images, the AST1700 functions are not included > by default. To test the AST1700-related functionality, please include > the following DTS files for probing: > https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi0.dtsi > https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/boot/dts/aspeed/aspeed-ltpi1.dtsi > > After including these DTS files in the BMC image, you can verify LTPI > functionality using the following scenarios: > > 1. In U-Boot: > Run the ltpi command to trigger the LTPI connection and display the > current connection status. > 2. In BMC Linux: > Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by > the AST1700. > > Any feedback or suggestions are appreciated! > > Kane > > --- > > ChangeLog > --------- > v5: > - Add functional test case for AST1700 I2C > - Corrected the From attribution > - Fixed incorrect DRAM setting for SPI and I2C controllers > - Refine code structure > > v4: > - Add missing Signed-off-by > - Fix checkpatch.pl warnings > - Refine code structure > - Enable AST1700 support only after all devices are ready > > v3: > - Add PWM model > - Integrate the SGPIO model > - Fix I2C test case failure > - Refine code structure > > v2: > - Separate the AST1700 model into a standalone implementation > - Refine the mechanism for assigning the AST1700 board number > > v1: > - Initial version > --- > > Cédric Le Goater (1): > hw/misc: Add basic Aspeed PWM model > > Kane-Chen-AS (21): > hw/misc: Add LTPI controller > hw/arm/aspeed: Attach LTPI controller to AST27X0 platform > hw/arm/aspeed: Add AST1700 LTPI expander device model > hw/arm/aspeed: Integrate AST1700 device into AST27X0 > hw/arm/aspeed: Integrate interrupt controller for AST1700 > hw/arm/aspeed: Attach LTPI controller to AST1700 model > hw/arm/aspeed: Attach UART device to AST1700 model > hw/arm/aspeed: Attach SRAM device to AST1700 model > hw/arm/aspeed: Attach SPI device to AST1700 model > hw/arm/aspeed: Attach ADC device to AST1700 model > hw/arm/aspeed: Attach SCU device to AST1700 model > hw/arm/aspeed: Attach GPIO device to AST1700 model > hw/arm/aspeed: Introduce 'bus-label' property for AST1700 SoC > hw/arm/aspeed: attach I2C device to AST1700 model > hw/arm/aspeed: Attach WDT device to AST1700 model > hw/arm/aspeed: Attach PWM device to AST1700 model > hw/arm/aspeed: Attach SGPIOM device to AST1700 model > hw/arm/aspeed: Model AST1700 I3C block as unimplemented device > hw/arm/aspeed: Enable AST1700 IO expander support > test/functional/aarch64: Parameterize I2C bus ID in AST2700 test > test/functional/aarch64: Add I2C test for AST1700 IO expanders > > include/hw/arm/aspeed_ast1700.h | 55 ++++ > include/hw/arm/aspeed_soc.h | 25 +- > include/hw/intc/aspeed_intc.h | 2 + > include/hw/misc/aspeed_ltpi.h | 33 +++ > include/hw/misc/aspeed_pwm.h | 31 ++ > hw/arm/aspeed_ast1700.c | 280 ++++++++++++++++++ > hw/arm/aspeed_ast27x0.c | 170 ++++++++++- > hw/intc/aspeed_intc.c | 60 ++++ > hw/misc/aspeed_ltpi.c | 193 ++++++++++++ > hw/misc/aspeed_pwm.c | 121 ++++++++ > hw/arm/meson.build | 1 + > hw/misc/meson.build | 2 + > hw/misc/trace-events | 4 + > .../functional/aarch64/test_aspeed_ast2700.py | 52 +++- > 14 files changed, 999 insertions(+), 30 deletions(-) > create mode 100644 include/hw/arm/aspeed_ast1700.h > create mode 100644 include/hw/misc/aspeed_ltpi.h > create mode 100644 include/hw/misc/aspeed_pwm.h > create mode 100644 hw/arm/aspeed_ast1700.c > create mode 100644 hw/misc/aspeed_ltpi.c > create mode 100644 hw/misc/aspeed_pwm.c >
Hi Cédric > From: Cédric Le Goater <clg@kaod.org> > Sent: Wednesday, January 21, 2026 12:09 AM > To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell > <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy > Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew > Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open > list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here > <qemu-devel@nongnu.org> > Cc: Troy Lee <troy_lee@aspeedtech.com> > Subject: Re: [PATCH v5 00/22] hw/arm/aspeed: AST1700 LTPI support and > device hookups > > Kane, Jamin, > > For some reason, I don't receive your proposals anymore. My provider seems > to drop silently these emails. Have you changed anything recently ? > The following patch series are ready for review. [v1,00/11] Add SSP/TSP power control and DRAM remap support for AST2700 https://patchwork.kernel.org/project/qemu-devel/cover/20260120092939.2708302-1-jamin_lin@aspeedtech.com/ [v5,00/22] hw/arm/aspeed: AST1700 LTPI support and device hookups https://patchwork.kernel.org/project/qemu-devel/cover/20260120051859.1920565-1-kane_chen@aspeedtech.com/ [PULL,SUBSYSTEM,vbootrom,v3,0/1] Update vbootrom image to commit 1c8e9510b22c https://patchwork.kernel.org/project/qemu-devel/patch/20260116093249.443307-1-jamin_lin@aspeedtech.com/ [PULL,1/1] pc-bios: Update vbootrom image to commit 1c8e9510b22c https://patchwork.kernel.org/project/qemu-devel/patch/20260116093249.443307-2-jamin_lin@aspeedtech.com/ Thanks-Jamin > Thanks, > > C. > > On 1/20/26 06:18, Kane Chen via qemu development wrote: > > From: Kane-Chen-AS <kane_chen@aspeedtech.com> > > > > Hi all, > > > > LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP > > DC-SCM > > 2.0 specification (see Figure 2): > > https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf > > > > LTPI provides a protocol and physical interface for tunneling various > > low-speed signals between the Host Processor Module (HPM) and the > > Satellite Controller Module (SCM). In Figure 2 of the specification, > > the AST27x0 SoC (left) integrates two LTPI controllers, allowing it to > > connect to up to two AST1700 boards. On the other side, the AST1700 > > consolidates HPM FPGA functions and multiple peripheral interfaces > > (GPIO, UART, I2C, I3C, etc.) onto a single board. > > > > Because the AST1700 exposes additional I/O interfaces (GPIO, I2C, I3C, > > and others), it acts as an I/O expander. Once connected over LTPI, the > > AST27x0 can control additional downstream devices through this link. > > > > This patch series is based on the aspeed_next branch and incorporates > > recent I2C bus label changes. > > Ref: > > https://patchwork.kernel.org/project/qemu-devel/patch/20260112083054.4 > > 151945-2-kane_chen@aspeedtech.com/ > > > > It introduces a basic LTPI controller model and wires it into the > > AST27x0 SoC. The series also adds the AST1700-specific LTPI expander > > device and incrementally connects common peripherals on the AST1700 > > model. For the I3C block, which may cause kernel crashes, its MMIO > > region is modeled as an unimplemented device to reserve address space > > and make the missing functionality explicit, ensuring stable guest > > probing. > > > > In the official release images, the AST1700 functions are not included > > by default. To test the AST1700-related functionality, please include > > the following DTS files for probing: > > https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a > > rm64/boot/dts/aspeed/aspeed-ltpi0.dtsi > > https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/a > > rm64/boot/dts/aspeed/aspeed-ltpi1.dtsi > > > > After including these DTS files in the BMC image, you can verify LTPI > > functionality using the following scenarios: > > > > 1. In U-Boot: > > Run the ltpi command to trigger the LTPI connection and display the > > current connection status. > > 2. In BMC Linux: > > Run i2cdetect -y <16-38> to scan and test the I2C buses exposed by > > the AST1700. > > > > Any feedback or suggestions are appreciated! > > > > Kane > > > > --- > > > > ChangeLog > > --------- > > v5: > > - Add functional test case for AST1700 I2C > > - Corrected the From attribution > > - Fixed incorrect DRAM setting for SPI and I2C controllers > > - Refine code structure > > > > v4: > > - Add missing Signed-off-by > > - Fix checkpatch.pl warnings > > - Refine code structure > > - Enable AST1700 support only after all devices are ready > > > > v3: > > - Add PWM model > > - Integrate the SGPIO model > > - Fix I2C test case failure > > - Refine code structure > > > > v2: > > - Separate the AST1700 model into a standalone implementation > > - Refine the mechanism for assigning the AST1700 board number > > > > v1: > > - Initial version > > --- > > > > Cédric Le Goater (1): > > hw/misc: Add basic Aspeed PWM model > > > > Kane-Chen-AS (21): > > hw/misc: Add LTPI controller > > hw/arm/aspeed: Attach LTPI controller to AST27X0 platform > > hw/arm/aspeed: Add AST1700 LTPI expander device model > > hw/arm/aspeed: Integrate AST1700 device into AST27X0 > > hw/arm/aspeed: Integrate interrupt controller for AST1700 > > hw/arm/aspeed: Attach LTPI controller to AST1700 model > > hw/arm/aspeed: Attach UART device to AST1700 model > > hw/arm/aspeed: Attach SRAM device to AST1700 model > > hw/arm/aspeed: Attach SPI device to AST1700 model > > hw/arm/aspeed: Attach ADC device to AST1700 model > > hw/arm/aspeed: Attach SCU device to AST1700 model > > hw/arm/aspeed: Attach GPIO device to AST1700 model > > hw/arm/aspeed: Introduce 'bus-label' property for AST1700 SoC > > hw/arm/aspeed: attach I2C device to AST1700 model > > hw/arm/aspeed: Attach WDT device to AST1700 model > > hw/arm/aspeed: Attach PWM device to AST1700 model > > hw/arm/aspeed: Attach SGPIOM device to AST1700 model > > hw/arm/aspeed: Model AST1700 I3C block as unimplemented device > > hw/arm/aspeed: Enable AST1700 IO expander support > > test/functional/aarch64: Parameterize I2C bus ID in AST2700 test > > test/functional/aarch64: Add I2C test for AST1700 IO expanders > > > > include/hw/arm/aspeed_ast1700.h | 55 ++++ > > include/hw/arm/aspeed_soc.h | 25 +- > > include/hw/intc/aspeed_intc.h | 2 + > > include/hw/misc/aspeed_ltpi.h | 33 +++ > > include/hw/misc/aspeed_pwm.h | 31 ++ > > hw/arm/aspeed_ast1700.c | 280 > ++++++++++++++++++ > > hw/arm/aspeed_ast27x0.c | 170 ++++++++++- > > hw/intc/aspeed_intc.c | 60 ++++ > > hw/misc/aspeed_ltpi.c | 193 > ++++++++++++ > > hw/misc/aspeed_pwm.c | 121 ++++++++ > > hw/arm/meson.build | 1 + > > hw/misc/meson.build | 2 + > > hw/misc/trace-events | 4 + > > .../functional/aarch64/test_aspeed_ast2700.py | 52 +++- > > 14 files changed, 999 insertions(+), 30 deletions(-) > > create mode 100644 include/hw/arm/aspeed_ast1700.h > > create mode 100644 include/hw/misc/aspeed_ltpi.h > > create mode 100644 include/hw/misc/aspeed_pwm.h > > create mode 100644 hw/arm/aspeed_ast1700.c > > create mode 100644 hw/misc/aspeed_ltpi.c > > create mode 100644 hw/misc/aspeed_pwm.c > >
Hi Cédric, I worked with our IT team to investigate the mail delivery issue. We identified that the mail server used for sending the patch series was missing DKIM (DomainKeys Identified Mail) signatures. We believe this is why the emails were being flagged as [SPAM]. We are currently enabling DKIM on the server and expect this to resolve the issue once the configuration is complete. Best regards, Kane
On 1/23/26 06:51, Kane Chen wrote: > Hi Cédric, > > I worked with our IT team to investigate the mail delivery issue. We > identified that the mail server used for sending the patch series was > missing DKIM (DomainKeys Identified Mail) signatures. We believe this > is why the emails were being flagged as [SPAM]. > > We are currently enabling DKIM on the server and expect this to > resolve the issue once the configuration is complete. Thanks for looking ! C.
Hello Jamin, On 1/21/26 01:56, Jamin Lin wrote: > Hi Cédric > >> From: Cédric Le Goater <clg@kaod.org> >> Sent: Wednesday, January 21, 2026 12:09 AM >> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell >> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy >> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew >> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open >> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here >> <qemu-devel@nongnu.org> >> Cc: Troy Lee <troy_lee@aspeedtech.com> >> Subject: Re: [PATCH v5 00/22] hw/arm/aspeed: AST1700 LTPI support and >> device hookups >> >> Kane, Jamin, >> >> For some reason, I don't receive your proposals anymore. My provider seems >> to drop silently these emails. Have you changed anything recently ? >> Thanks for the info. > The following patch series are ready for review. > [v1,00/11] Add SSP/TSP power control and DRAM remap support for AST2700 > https://patchwork.kernel.org/project/qemu-devel/cover/20260120092939.2708302-1-jamin_lin@aspeedtech.com/ I am seeing a 'make check' issue with this one. A 'dram' property link is missing. > [v5,00/22] hw/arm/aspeed: AST1700 LTPI support and device hookups > https://patchwork.kernel.org/project/qemu-devel/cover/20260120051859.1920565-1-kane_chen@aspeedtech.com/ There is a discussion in progress about the bus naming. Not a blocker but it's worth a bit of thinking. > [PULL,SUBSYSTEM,vbootrom,v3,0/1] Update vbootrom image to commit 1c8e9510b22c > https://patchwork.kernel.org/project/qemu-devel/patch/20260116093249.443307-1-jamin_lin@aspeedtech.com/ > [PULL,1/1] pc-bios: Update vbootrom image to commit 1c8e9510b22c > https://patchwork.kernel.org/project/qemu-devel/patch/20260116093249.443307-2-jamin_lin@aspeedtech.com/ The above 3 series I plan to include in the next Aspeed PR. What about the I3C series ? Could you take ownership ? Thanks, C.
+ Nabih, Joe Hi Cédric, > -----Original Message----- > From: Cédric Le Goater <clg@kaod.org> > Sent: Friday, January 23, 2026 2:04 PM > To: Jamin Lin <jamin_lin@aspeedtech.com>; Kane Chen > <kane_chen@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>; > Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; > Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley > <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open > list:All patches CC here <qemu-devel@nongnu.org> > Cc: Troy Lee <troy_lee@aspeedtech.com> > Subject: Re: [PATCH v5 00/22] hw/arm/aspeed: AST1700 LTPI support and > device hookups > > Hello Jamin, > > On 1/21/26 01:56, Jamin Lin wrote: > > Hi Cédric > > > >> From: Cédric Le Goater <clg@kaod.org> > >> Sent: Wednesday, January 21, 2026 12:09 AM > >> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell > >> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; > >> Troy Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; > >> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley > >> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open > >> list:All patches CC here <qemu-devel@nongnu.org> > >> Cc: Troy Lee <troy_lee@aspeedtech.com> > >> Subject: Re: [PATCH v5 00/22] hw/arm/aspeed: AST1700 LTPI support and > >> device hookups > >> > >> Kane, Jamin, > >> > >> For some reason, I don't receive your proposals anymore. My provider > >> seems to drop silently these emails. Have you changed anything recently ? > >> > > Thanks for the info. > > > The following patch series are ready for review. > > [v1,00/11] Add SSP/TSP power control and DRAM remap support for > > AST2700 > > https://patchwork.kernel.org/project/qemu-devel/cover/20260120092939.2 > > 708302-1-jamin_lin@aspeedtech.com/ > > I am seeing a 'make check' issue with this one. A 'dram' property link is > missing. > > > [v5,00/22] hw/arm/aspeed: AST1700 LTPI support and device hookups > > https://patchwork.kernel.org/project/qemu-devel/cover/20260120051859.1 > > 920565-1-kane_chen@aspeedtech.com/ > > There is a discussion in progress about the bus naming. Not a blocker but it's > worth a bit of thinking. > > > [PULL,SUBSYSTEM,vbootrom,v3,0/1] Update vbootrom image to commit > > 1c8e9510b22c > > https://patchwork.kernel.org/project/qemu-devel/patch/20260116093249.4 > > 43307-1-jamin_lin@aspeedtech.com/ [PULL,1/1] pc-bios: Update vbootrom > > image to commit 1c8e9510b22c > > https://patchwork.kernel.org/project/qemu-devel/patch/20260116093249.4 > > 43307-2-jamin_lin@aspeedtech.com/ > > The above 3 series I plan to include in the next Aspeed PR. > > What about the I3C series ? Could you take ownership ? > I will discuss this with Joe and Nabih first. If they agree, I am willing to take ownership of the I3C upstream work starting from v2. Thanks, Jamin > Thanks, > > C.
Hi Cédric, > Subject: RE: [PATCH v5 00/22] hw/arm/aspeed: AST1700 LTPI support and > device hookups > > + Nabih, Joe > > Hi Cédric, > > > -----Original Message----- > > From: Cédric Le Goater <clg@kaod.org> > > Sent: Friday, January 23, 2026 2:04 PM > > To: Jamin Lin <jamin_lin@aspeedtech.com>; Kane Chen > > <kane_chen@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>; > > Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; > > Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley > > <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open > > list:All patches CC here <qemu-devel@nongnu.org> > > Cc: Troy Lee <troy_lee@aspeedtech.com> > > Subject: Re: [PATCH v5 00/22] hw/arm/aspeed: AST1700 LTPI support and > > device hookups > > > > Hello Jamin, > > > > On 1/21/26 01:56, Jamin Lin wrote: > > > Hi Cédric > > > > > >> From: Cédric Le Goater <clg@kaod.org> > > >> Sent: Wednesday, January 21, 2026 12:09 AM > > >> To: Kane Chen <kane_chen@aspeedtech.com>; Peter Maydell > > >> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; > > >> Troy Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; > > >> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley > > >> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; > open > > >> list:All patches CC here <qemu-devel@nongnu.org> > > >> Cc: Troy Lee <troy_lee@aspeedtech.com> > > >> Subject: Re: [PATCH v5 00/22] hw/arm/aspeed: AST1700 LTPI support > > >> and device hookups > > >> > > >> Kane, Jamin, > > >> > > >> For some reason, I don't receive your proposals anymore. My > > >> provider seems to drop silently these emails. Have you changed anything > recently ? > > >> > > > > Thanks for the info. > > > > > The following patch series are ready for review. > > > [v1,00/11] Add SSP/TSP power control and DRAM remap support for > > > AST2700 > > > https://patchwork.kernel.org/project/qemu-devel/cover/20260120092939 > > > .2 > > > 708302-1-jamin_lin@aspeedtech.com/ > > > > I am seeing a 'make check' issue with this one. A 'dram' property link > > is missing. > > > > > [v5,00/22] hw/arm/aspeed: AST1700 LTPI support and device hookups > > > https://patchwork.kernel.org/project/qemu-devel/cover/20260120051859 > > > .1 > > > 920565-1-kane_chen@aspeedtech.com/ > > > > There is a discussion in progress about the bus naming. Not a blocker > > but it's worth a bit of thinking. > > > > > [PULL,SUBSYSTEM,vbootrom,v3,0/1] Update vbootrom image to commit > > > 1c8e9510b22c > > > https://patchwork.kernel.org/project/qemu-devel/patch/20260116093249 > > > .4 43307-1-jamin_lin@aspeedtech.com/ [PULL,1/1] pc-bios: Update > > > vbootrom image to commit 1c8e9510b22c > > > https://patchwork.kernel.org/project/qemu-devel/patch/20260116093249 > > > .4 > > > 43307-2-jamin_lin@aspeedtech.com/ > > > > The above 3 series I plan to include in the next Aspeed PR. > > > > What about the I3C series ? Could you take ownership ? > > > > I will discuss this with Joe and Nabih first. > If they agree, I am willing to take ownership of the I3C upstream work starting > from v2. Joe and Nabih (GOOGLE) have agreed that I will take ownership of the I3C upstream work. I am currently updating the function tests for AST2700 A1 to version 11.00, and will then proceed with upstream support for AST2700 A2. After completing these tasks, I plan to resend the I3C v2 series, with an estimated timeline around mid-February. Thanks-Jamin > > Thanks, > Jamin > > > Thanks, > > > > C.
Hi Cédric, Joe, Nabih > > > What about the I3C series ? Could you take ownership ? > > > > > > > I will discuss this with Joe and Nabih first. > > If they agree, I am willing to take ownership of the I3C upstream work > > starting from v2. > > Joe and Nabih (GOOGLE) have agreed that I will take ownership of the I3C > upstream work. > > I am currently updating the function tests for AST2700 A1 to version 11.00, and > will then proceed with upstream support for AST2700 A2. > After completing these tasks, I plan to resend the I3C v2 series, with an > estimated timeline around mid-February. > > Thanks-Jamin > I have sent the I3C v2 patch series here: https://patchew.org/QEMU/20260203085229.1543287-1-jamin._5Flin@aspeedtech.com/ Thanks Jamin > > > > Thanks, > > Jamin > > > > > Thanks, > > > > > > C.
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