From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886458; cv=none; d=zohomail.com; s=zohoarc; b=Zx00VRbmJsPzFsiz3UUYO75EMDEj0bLq4VEC78+TH7senHMYpT9JOOOaLZ1M6dgSbWWA/GVGVs5SC/REue1EYc59Y4F4iWq6bF9780VTsc+UGVHdfJz/0le0/33Gq1fItA520+IRDUqidhWlqWCLLLsIzcgzLLtga5HmRKSD3IM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768886458; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Ay+/NyinSDyJO+i+MoxpI0h7zqPiP6GG+GTOkanG13c=; b=If8Pl/AF/lCMD2J3hFjjdYZ7helKr0tqnL3KYGHVSm8CUZ3DsldKnRA8JNVFrIUA0ZHZbiRCzF6CoMEf9TrQehggABg+C8bPXmBioPVIVknfeSLhbuic67l+LkUZclCgt1qPYSuwAVcmNRzgLRzmuc05F1iXf13kAy50AQyPmKg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17688864586391007.1809440845115; Mon, 19 Jan 2026 21:20:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vi49B-00049j-Eb; Tue, 20 Jan 2026 00:19:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi499-000496-DE; Tue, 20 Jan 2026 00:19:19 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi494-0004ZS-Ev; Tue, 20 Jan 2026 00:19:19 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:00 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:00 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 01/22] hw/misc: Add LTPI controller Date: Tue, 20 Jan 2026 13:18:32 +0800 Message-ID: <20260120051859.1920565-2-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886459834158500 From: Kane-Chen-AS LTPI (LVDS Tunneling Protocol & Interface) is defined in the OCP DC-SCM 2.0 specification: https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf LTPI is a protocol and physical interface for tunneling various low-speed signals between the HPM and SCM. As shown in Figure 2, the AST27x0 (left) integrates two LTPI controllers, allowing it to connect to up to two extended boards. This commit introduces a simple device model for the ASPEED LTPI controller in QEMU. The model includes basic MMIO read/write operations and sets default register values during reset to emulate a link-up state. Implements register space with read/write callbacks. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/misc/aspeed_ltpi.h | 33 ++++++ hw/misc/aspeed_ltpi.c | 193 ++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 227 insertions(+) create mode 100644 include/hw/misc/aspeed_ltpi.h create mode 100644 hw/misc/aspeed_ltpi.c diff --git a/include/hw/misc/aspeed_ltpi.h b/include/hw/misc/aspeed_ltpi.h new file mode 100644 index 0000000000..3330a49b05 --- /dev/null +++ b/include/hw/misc/aspeed_ltpi.h @@ -0,0 +1,33 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_LTPI_H +#define ASPEED_LTPI_H + +#include "hw/core/sysbus.h" + +#define TYPE_ASPEED_LTPI "aspeed.ltpi-ctrl" +OBJECT_DECLARE_SIMPLE_TYPE(AspeedLTPIState, ASPEED_LTPI) + +#define ASPEED_LTPI_TOTAL_SIZE 0x900 +#define ASPEED_LTPI_CTRL_SIZE 0x200 +#define ASPEED_LTPI_PHY_SIZE 0x100 +#define ASPEED_LTPI_TOP_SIZE 0x100 + +struct AspeedLTPIState { + SysBusDevice parent; + MemoryRegion mmio; + MemoryRegion mmio_ctrl; + MemoryRegion mmio_phy; + MemoryRegion mmio_top; + + uint32_t ctrl_regs[ASPEED_LTPI_CTRL_SIZE >> 2]; + uint32_t phy_regs[ASPEED_LTPI_PHY_SIZE >> 2]; + uint32_t top_regs[ASPEED_LTPI_TOP_SIZE >> 2]; +}; + +#endif /* ASPEED_LTPI_H */ diff --git a/hw/misc/aspeed_ltpi.c b/hw/misc/aspeed_ltpi.c new file mode 100644 index 0000000000..131cea9c6b --- /dev/null +++ b/hw/misc/aspeed_ltpi.c @@ -0,0 +1,193 @@ +/* + * ASPEED LTPI Controller + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/misc/aspeed_ltpi.h" + +#define ASPEED_LTPI_CTRL_BASE 0x000 +#define ASPEED_LTPI_PHY_BASE 0x200 +#define ASPEED_LTPI_TOP_BASE 0x800 + +#define LTPI_CTRL_LINK_MNG 0x42 +#define LTPI_PHY_MODE 0x0 + +static uint64_t aspeed_ltpi_top_read(void *opaque, hwaddr offset, unsigned= size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + return s->top_regs[idx]; +} + +static void aspeed_ltpi_top_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + switch (offset) { + default: + s->top_regs[idx] =3D (uint32_t)val; + break; + } +} + +static const MemoryRegionOps aspeed_ltpi_top_ops =3D { + .read =3D aspeed_ltpi_top_read, + .write =3D aspeed_ltpi_top_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static uint64_t aspeed_ltpi_phy_read(void *opaque, hwaddr offset, unsigned= size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + return s->phy_regs[idx]; +} + +static void aspeed_ltpi_phy_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + switch (offset) { + default: + s->phy_regs[idx] =3D (uint32_t)val; + break; + } +} + +static const MemoryRegionOps aspeed_ltpi_phy_ops =3D { + .read =3D aspeed_ltpi_phy_read, + .write =3D aspeed_ltpi_phy_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static uint64_t aspeed_ltpi_ctrl_read(void *opaque, + hwaddr offset, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + return s->ctrl_regs[idx]; +} + +static void aspeed_ltpi_ctrl_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + AspeedLTPIState *s =3D opaque; + uint32_t idx =3D offset >> 2; + + switch (offset) { + default: + s->ctrl_regs[idx] =3D (uint32_t)val; + break; + } +} + +static const MemoryRegionOps aspeed_ltpi_ctrl_ops =3D { + .read =3D aspeed_ltpi_ctrl_read, + .write =3D aspeed_ltpi_ctrl_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void aspeed_ltpi_reset(DeviceState *dev) +{ + AspeedLTPIState *s =3D ASPEED_LTPI(dev); + + memset(s->ctrl_regs, 0, sizeof(s->ctrl_regs)); + memset(s->phy_regs, 0, sizeof(s->phy_regs)); + memset(s->top_regs, 0, sizeof(s->top_regs)); + /* set default values */ + s->ctrl_regs[LTPI_CTRL_LINK_MNG] =3D 0x11900007; + s->phy_regs[LTPI_PHY_MODE] =3D 0x2; +} + + +static const VMStateDescription vmstate_aspeed_ltpi =3D { + .name =3D TYPE_ASPEED_LTPI, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(ctrl_regs, AspeedLTPIState, + ASPEED_LTPI_CTRL_SIZE >> 2), + VMSTATE_UINT32_ARRAY(phy_regs, AspeedLTPIState, + ASPEED_LTPI_PHY_SIZE >> 2), + VMSTATE_UINT32_ARRAY(top_regs, AspeedLTPIState, + ASPEED_LTPI_TOP_SIZE >> 2), + + VMSTATE_END_OF_LIST() + } +}; + +static void aspeed_ltpi_realize(DeviceState *dev, Error **errp) +{ + AspeedLTPIState *s =3D ASPEED_LTPI(dev); + + memory_region_init(&s->mmio, OBJECT(s), TYPE_ASPEED_LTPI, + ASPEED_LTPI_TOTAL_SIZE); + + memory_region_init_io(&s->mmio_ctrl, OBJECT(s), + &aspeed_ltpi_ctrl_ops, s, + "aspeed-ltpi-ctrl", ASPEED_LTPI_CTRL_SIZE); + + memory_region_init_io(&s->mmio_phy, OBJECT(s), + &aspeed_ltpi_phy_ops, s, + "aspeed-ltpi-phy", ASPEED_LTPI_PHY_SIZE); + + memory_region_init_io(&s->mmio_top, OBJECT(s), + &aspeed_ltpi_top_ops, s, + "aspeed-ltpi-top", ASPEED_LTPI_TOP_SIZE); + + memory_region_add_subregion(&s->mmio, + ASPEED_LTPI_CTRL_BASE, &s->mmio_ctrl); + memory_region_add_subregion(&s->mmio, + ASPEED_LTPI_PHY_BASE, &s->mmio_phy); + memory_region_add_subregion(&s->mmio, + ASPEED_LTPI_TOP_BASE, &s->mmio_top); + + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); +} + +static void aspeed_ltpi_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D aspeed_ltpi_realize; + dc->vmsd =3D &vmstate_aspeed_ltpi; + device_class_set_legacy_reset(dc, aspeed_ltpi_reset); +} + +static const TypeInfo aspeed_ltpi_info =3D { + .name =3D TYPE_ASPEED_LTPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedLTPIState), + .class_init =3D aspeed_ltpi_class_init, +}; + +static void aspeed_ltpi_register_types(void) +{ + type_register_static(&aspeed_ltpi_info); +} + +type_init(aspeed_ltpi_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b1d8d8e5d2..45b16e7797 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -136,6 +136,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_hace.c', 'aspeed_i3c.c', 'aspeed_lpc.c', + 'aspeed_ltpi.c', 'aspeed_scu.c', 'aspeed_sbc.c', 'aspeed_sdmc.c', --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886414; cv=none; d=zohomail.com; s=zohoarc; b=m5JQ0Hj6NsWamJs4BgBH+UtJ4VYDpO8KpWiWbcucshHceJqRkr09BxzFNr4K3Y/V0TZ3ssg52KmxKnO3VOOFgjFYOZr+acxPn6Ftmuqq9aiElbdoguqAOUqVyaZhNd47uXA8BeqNCq5pXHBfbp5p6Cx3G9sFU2ndUEEuKFqybFs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768886414; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=oda5NEQchQMMfsOxPmqqNyV+lz9y8ZRUm//lSrNrrco=; b=XWjTfTz0ybIgraIzW5OQvdBF9GzZ3hEnhwADtc3HeCmBXdLoU9FcrbFbbWspWGcqUATS9ZNtXuw8VGgDcHUHe37BAWKuTeTHW/V4Djw8vbAL6LX7J6kb+tTX5DhSldyeewfUZR/0HUrqv6+soQ6I5jYrVQXjIXzaEevHTmrM5bA= ARC-Authentication-Results: i=1; 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Tue, 20 Jan 2026 13:19:00 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:00 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 02/22] hw/arm/aspeed: Attach LTPI controller to AST27X0 platform Date: Tue, 20 Jan 2026 13:18:33 +0800 Message-ID: <20260120051859.1920565-3-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886417125154100 From: Kane-Chen-AS Connect the LTPI controller device (representing the AST1700 I/O expander) to the AST27X0 SoC model. This patch sets up the memory mapping and device registration according to the AST2700 SoC design, where the LTPI controller is exposed at fixed MMIO regions. This change only handles device instantiation and integration, without implementing the controller's internal logic. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_soc.h | 5 +++++ hw/arm/aspeed_ast27x0.c | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 18ff961a38..bca10c387b 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -43,6 +43,7 @@ #include "hw/fsi/aspeed_apb2opb.h" #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" +#include "hw/misc/aspeed_ltpi.h" =20 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 @@ -55,6 +56,7 @@ #define ASPEED_UARTS_NUM 13 #define ASPEED_JTAG_NUM 2 #define ASPEED_PCIE_NUM 3 +#define ASPEED_IOEXP_NUM 2 =20 struct AspeedSoCState { DeviceState parent; @@ -112,6 +114,7 @@ struct AspeedSoCState { UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; + AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -279,6 +282,8 @@ enum { ASPEED_GIC_REDIST, ASPEED_DEV_IPC0, ASPEED_DEV_IPC1, + ASPEED_DEV_LTPI_CTRL1, + ASPEED_DEV_LTPI_CTRL2, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index d17f446661..3b458f50d1 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -88,6 +88,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_UART10] =3D 0x14C33900, [ASPEED_DEV_UART11] =3D 0x14C33A00, [ASPEED_DEV_UART12] =3D 0x14C33B00, + [ASPEED_DEV_LTPI_CTRL1] =3D 0x14C34000, + [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, [ASPEED_DEV_LTPI] =3D 0x30000000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, @@ -489,6 +491,11 @@ static void aspeed_soc_ast2700_init(Object *obj) object_property_set_int(OBJECT(&s->pcie[i]), "id", i, &error_abort= ); } =20 + for (i =3D 0; i < ASPEED_IOEXP_NUM; i++) { + object_initialize_child(obj, "ltpi-ctrl[*]", + &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); + } + object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "ltpi", &s->ltpi, @@ -972,6 +979,20 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) return; } =20 + /* LTPI controller */ + for (i =3D 0; i < ASPEED_IOEXP_NUM; i++) { + AspeedLTPIState *ltpi_ctrl; + hwaddr ltpi_base; + + ltpi_ctrl =3D ASPEED_LTPI(&s->ltpi_ctrl[i]); + ltpi_base =3D sc->memmap[ASPEED_DEV_LTPI_CTRL1 + i]; + + if (!sysbus_realize(SYS_BUS_DEVICE(ltpi_ctrl), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base= ); + } + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886421; cv=none; d=zohomail.com; s=zohoarc; b=dRo75Y84KCYlG49vKubMWT2Qww+MDXqIKl7ZcUCs9Xv/vd20VdihtxqzDjPaRZDEEp163rOnHWXW20M6NimWuynVt3dWLmYul2jemKhtfB+jaF/IoGgLmpdR5R1k/gt/WUGXCtFxkghj7m3Dr5mxsGkbDHYK7fxzrXFTBdDfzbU= ARC-Message-Signature: i=1; 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Tue, 20 Jan 2026 00:19:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi49E-0004C3-GU; Tue, 20 Jan 2026 00:19:24 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi49C-0004ZS-MY; Tue, 20 Jan 2026 00:19:24 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 03/22] hw/misc: Add basic Aspeed PWM model Date: Tue, 20 Jan 2026 13:18:34 +0800 Message-ID: <20260120051859.1920565-4-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886423699158500 From: C=C3=A9dric Le Goater Add an initial PWM model for Aspeed SoCs, including device state, register definitions, and basic initialization as a sysbus device. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 3 +- include/hw/misc/aspeed_pwm.h | 31 +++++++++ hw/misc/aspeed_pwm.c | 121 +++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 4 ++ 5 files changed, 159 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/aspeed_pwm.h create mode 100644 hw/misc/aspeed_pwm.c diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index bca10c387b..7b08cca908 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -28,6 +28,7 @@ #include "hw/misc/aspeed_hace.h" #include "hw/misc/aspeed_sbc.h" #include "hw/misc/aspeed_sli.h" +#include "hw/misc/aspeed_pwm.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" @@ -88,6 +89,7 @@ struct AspeedSoCState { MemoryRegion secsram; UnimplementedDeviceState sbc_unimplemented; AspeedSDMCState sdmc; + AspeedPWMState pwm; AspeedWDTState wdt[ASPEED_WDTS_NUM]; FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; AspeedMiiState mii[ASPEED_MACS_NUM]; @@ -108,7 +110,6 @@ struct AspeedSoCState { UnimplementedDeviceState video; UnimplementedDeviceState emmc_boot_controller; UnimplementedDeviceState dpmcu; - UnimplementedDeviceState pwm; UnimplementedDeviceState espi; UnimplementedDeviceState udc; UnimplementedDeviceState ltpi; diff --git a/include/hw/misc/aspeed_pwm.h b/include/hw/misc/aspeed_pwm.h new file mode 100644 index 0000000000..4d5b0bbd86 --- /dev/null +++ b/include/hw/misc/aspeed_pwm.h @@ -0,0 +1,31 @@ +/* + * ASPEED PWM Controller + * + * Copyright (C) 2017-2021 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef ASPEED_PWM_H +#define ASPEED_PWM_H + +#include "hw/core/sysbus.h" + +#define TYPE_ASPEED_PWM "aspeed.pwm" +#define ASPEED_PWM(obj) OBJECT_CHECK(AspeedPWMState, (obj), TYPE_ASPEED_PW= M) + +#define ASPEED_PWM_NR_REGS (0x10C >> 2) + +typedef struct AspeedPWMState { + /* */ + SysBusDevice parent; + + /*< public >*/ + MemoryRegion iomem; + qemu_irq irq; + + uint32_t regs[ASPEED_PWM_NR_REGS]; +} AspeedPWMState; + +#endif /* _ASPEED_PWM_H_ */ diff --git a/hw/misc/aspeed_pwm.c b/hw/misc/aspeed_pwm.c new file mode 100644 index 0000000000..de209274af --- /dev/null +++ b/hw/misc/aspeed_pwm.c @@ -0,0 +1,121 @@ +/* + * ASPEED PWM Controller + * + * Copyright (C) 2017-2021 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/misc/aspeed_pwm.h" +#include "qapi/error.h" +#include "migration/vmstate.h" + +#include "trace.h" + +static uint64_t aspeed_pwm_read(void *opaque, hwaddr addr, + unsigned int size) +{ + AspeedPWMState *s =3D ASPEED_PWM(opaque); + uint64_t val =3D 0; + + addr >>=3D 2; + + if (addr >=3D ASPEED_PWM_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "= \n", + __func__, addr << 2); + } else { + val =3D s->regs[addr]; + } + + trace_aspeed_pwm_read(addr << 2, val); + + return val; +} + +static void aspeed_pwm_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + AspeedPWMState *s =3D ASPEED_PWM(opaque); + + trace_aspeed_pwm_write(addr, data); + + addr >>=3D 2; + + if (addr >=3D ASPEED_PWM_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, addr << 2); + return; + } + + s->regs[addr] =3D data; +} + +static const MemoryRegionOps aspeed_pwm_ops =3D { + .read =3D aspeed_pwm_read, + .write =3D aspeed_pwm_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void aspeed_pwm_reset(DeviceState *dev) +{ + struct AspeedPWMState *s =3D ASPEED_PWM(dev); + + memset(s->regs, 0, sizeof(s->regs)); +} + +static void aspeed_pwm_realize(DeviceState *dev, Error **errp) +{ + AspeedPWMState *s =3D ASPEED_PWM(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_pwm_ops, s, + TYPE_ASPEED_PWM, 0x1000); + + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription vmstate_aspeed_pwm =3D { + .name =3D TYPE_ASPEED_PWM, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedPWMState, ASPEED_PWM_NR_REGS), + VMSTATE_END_OF_LIST(), + } +}; + +static void aspeed_pwm_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_pwm_realize; + device_class_set_legacy_reset(dc, aspeed_pwm_reset); + dc->desc =3D "Aspeed PWM Controller"; + dc->vmsd =3D &vmstate_aspeed_pwm; +} + +static const TypeInfo aspeed_pwm_info =3D { + .name =3D TYPE_ASPEED_PWM, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedPWMState), + .class_init =3D aspeed_pwm_class_init, +}; + +static void aspeed_pwm_register_types(void) +{ + type_register_static(&aspeed_pwm_info); +} + +type_init(aspeed_pwm_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 45b16e7797..7afe1d0009 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -137,6 +137,7 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_i3c.c', 'aspeed_lpc.c', 'aspeed_ltpi.c', + 'aspeed_pwm.c', 'aspeed_scu.c', 'aspeed_sbc.c', 'aspeed_sdmc.c', diff --git a/hw/misc/trace-events b/hw/misc/trace-events index eeb9243898..f7870babba 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -299,6 +299,10 @@ aspeed_i3c_write(uint64_t offset, uint64_t data) "I3C = write: offset 0x%" PRIx64 aspeed_i3c_device_read(uint32_t deviceid, uint64_t offset, uint64_t data) = "I3C Dev[%u] read: offset 0x%" PRIx64 " data 0x%" PRIx64 aspeed_i3c_device_write(uint32_t deviceid, uint64_t offset, uint64_t data)= "I3C Dev[%u] write: offset 0x%" PRIx64 " data 0x%" PRIx64 =20 +# aspeed_pwm.c +aspeed_pwm_read(uint64_t offset, uint64_t data) "read: offset 0x%" PRIx64 = " data 0x%" PRIx64 +aspeed_pwm_write(uint64_t offset, uint64_t data) "write: offset 0x%" PRIx6= 4 " data 0x%" PRIx64 + # aspeed_sdmc.c aspeed_sdmc_write(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0= x%" PRIx64 aspeed_sdmc_read(uint64_t reg, uint64_t data) "reg @0x%" PRIx64 " data: 0x= %" PRIx64 --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 20 Jan 2026 13:19:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 04/22] hw/arm/aspeed: Add AST1700 LTPI expander device model Date: Tue, 20 Jan 2026 13:18:35 +0800 Message-ID: <20260120051859.1920565-5-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886651268154100 From: Kane-Chen-AS Introduce a minimal QEMU device model for the ASPEED AST1700, an MCU-less I/O expander used in the LTPI topology defined by the DC-SCM 2.0 specification (see figure 2): https://www.opencompute.org/documents/ocp-dc-scm-2-0-ltpi-ver-1-0-pdf This initial implementation includes: * Definition of aspeed.ast1700 as a SysBusDevice * Setup of a basic memory region to reserve I/O space for future peripheral modeling This stub establishes the foundation for LTPI-related device emulation, without implementing any functional peripherals at this stage. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 23 +++++++++++++++++ hw/arm/aspeed_ast1700.c | 46 +++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 70 insertions(+) create mode 100644 include/hw/arm/aspeed_ast1700.h create mode 100644 hw/arm/aspeed_ast1700.c diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h new file mode 100644 index 0000000000..378dcb437a --- /dev/null +++ b/include/hw/arm/aspeed_ast1700.h @@ -0,0 +1,23 @@ +/* + * ASPEED AST1700 IO Expander + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ASPEED_AST1700_H +#define ASPEED_AST1700_H + +#include "hw/core/sysbus.h" + +#define TYPE_ASPEED_AST1700 "aspeed.ast1700" + +OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700) + +struct AspeedAST1700SoCState { + SysBusDevice parent_obj; + + MemoryRegion iomem; +}; + +#endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c new file mode 100644 index 0000000000..dd38b819b8 --- /dev/null +++ b/hw/arm/aspeed_ast1700.c @@ -0,0 +1,46 @@ +/* + * ASPEED AST1700 IO Expander + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/boards.h" +#include "qom/object.h" +#include "hw/arm/aspeed_ast1700.h" + +#define AST2700_SOC_LTPI_SIZE 0x01000000 + +static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) +{ + AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + /* Occupy memory space for all controllers in AST1700 */ + memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, + AST2700_SOC_LTPI_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D aspeed_ast1700_realize; +} + +static const TypeInfo aspeed_ast1700_info =3D { + .name =3D TYPE_ASPEED_AST1700, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AspeedAST1700SoCState), + .class_init =3D aspeed_ast1700_class_init, +}; + +static void aspeed_ast1700_register_types(void) +{ + type_register_static(&aspeed_ast1700_info); +} + +type_init(aspeed_ast1700_register_types); diff --git a/hw/arm/meson.build b/hw/arm/meson.build index aeaf654790..175942263d 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -70,6 +70,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast10x0_evb.c', 'fby35.c')) arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: = files( + 'aspeed_ast1700.c', 'aspeed_ast27x0.c', 'aspeed_ast27x0_evb.c', 'aspeed_ast27x0-fc.c', --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17688865270241001.6142188532408; Mon, 19 Jan 2026 21:22:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vi49L-0004Im-B7; Tue, 20 Jan 2026 00:19:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi49J-0004H6-Ba; Tue, 20 Jan 2026 00:19:29 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi49H-0004ZS-Q8; Tue, 20 Jan 2026 00:19:29 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 05/22] hw/arm/aspeed: Integrate AST1700 device into AST27X0 Date: Tue, 20 Jan 2026 13:18:36 +0800 Message-ID: <20260120051859.1920565-6-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886529729154100 From: Kane-Chen-AS Connect the AST1700 device as a child of the AST27X0 model to reflect its role in DC-SCM 2.0 LTPI-based architectures. This patch wires the AST1700 device into the platform without introducing functional peripherals. This forms the base for LTPI expander emulation in QEMU using AST27X0 as the host controller. Note: ioexp_num is set to 0 at this stage. Once all related devices and interrupts are fully implemented, ioexp_num will be updated to its expected value. This ensures the machine remains functional at every commit and avoids potential compiler or build issues. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_soc.h | 7 +++++-- hw/arm/aspeed_ast27x0.c | 26 ++++++++++++++++++-------- 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 7b08cca908..f19bab3457 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -45,6 +45,7 @@ #include "hw/char/serial-mm.h" #include "hw/intc/arm_gicv3.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/arm/aspeed_ast1700.h" =20 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" =20 @@ -112,10 +113,10 @@ struct AspeedSoCState { UnimplementedDeviceState dpmcu; UnimplementedDeviceState espi; UnimplementedDeviceState udc; - UnimplementedDeviceState ltpi; UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; AspeedAPB2OPBState fsi[2]; AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM]; + AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM]; }; =20 #define TYPE_ASPEED_SOC "aspeed-soc" @@ -178,6 +179,7 @@ struct AspeedSoCClass { int macs_num; int uarts_num; int uarts_base; + int ioexp_num; const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; @@ -190,7 +192,6 @@ enum { ASPEED_DEV_IOMEM, ASPEED_DEV_IOMEM0, ASPEED_DEV_IOMEM1, - ASPEED_DEV_LTPI, ASPEED_DEV_UART0, ASPEED_DEV_UART1, ASPEED_DEV_UART2, @@ -285,6 +286,8 @@ enum { ASPEED_DEV_IPC1, ASPEED_DEV_LTPI_CTRL1, ASPEED_DEV_LTPI_CTRL2, + ASPEED_DEV_LTPI_IO0, + ASPEED_DEV_LTPI_IO1, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 3b458f50d1..0517a5351d 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -26,7 +26,6 @@ #define AST2700_SOC_IO_SIZE 0x00FE0000 #define AST2700_SOC_IOMEM_SIZE 0x01000000 #define AST2700_SOC_DPMCU_SIZE 0x00040000 -#define AST2700_SOC_LTPI_SIZE 0x01000000 =20 static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_VBOOTROM] =3D 0x00000000, @@ -91,7 +90,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL1] =3D 0x14C34000, [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, - [ASPEED_DEV_LTPI] =3D 0x30000000, + [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, @@ -496,10 +496,14 @@ static void aspeed_soc_ast2700_init(Object *obj) &s->ltpi_ctrl[i], TYPE_ASPEED_LTPI); } =20 + for (i =3D 0; i < sc->ioexp_num; i++) { + /* AST1700 IOEXP */ + object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], + TYPE_ASPEED_AST1700); + } + object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); - object_initialize_child(obj, "ltpi", &s->ltpi, - TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "iomem0", &s->iomem0, @@ -993,14 +997,19 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(ltpi_ctrl), 0, ltpi_base= ); } =20 + /* IO Expander */ + for (i =3D 0; i < sc->ioexp_num; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0, + sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); + } + aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", sc->memmap[ASPEED_DEV_DPMCU], AST2700_SOC_DPMCU_SIZE); - aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->ltpi), - "aspeed.ltpi", - sc->memmap[ASPEED_DEV_LTPI], - AST2700_SOC_LTPI_SIZE); aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", sc->memmap[ASPEED_DEV_IOMEM], @@ -1039,6 +1048,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->macs_num =3D 3; sc->uarts_num =3D 13; sc->num_cpus =3D 4; + sc->ioexp_num =3D 0; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; sc->memmap =3D aspeed_soc_ast2700_memmap; --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886423; cv=none; d=zohomail.com; s=zohoarc; b=Rqf93JtwGeCNxpcCpG/+hTbCHpOE9PgFUhQUB3uLmpvi+oCZEAJFJvfIxi4h6BoGqkLlk1l2Mg23JNAQj9Huh2i9loJdNSjdJQs5Jrixw2HCw7UGLn+6XvxTUrVcARKBOeXrVkCrOhGxtuDTlwfvk7V1gVogbi/cvhF/WWVFVs4= ARC-Message-Signature: i=1; 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charset="utf-8" From: Kane-Chen-AS Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling the propagation of AST1700-originated interrupts to the host SoC. This patch does not implement interrupt sources in AST1700 itself, only the wiring into AST27X0. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_soc.h | 6 +++- include/hw/intc/aspeed_intc.h | 2 ++ hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++ hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++ 4 files changed, 104 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index f19bab3457..b051d0eb3a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -58,6 +58,7 @@ #define ASPEED_UARTS_NUM 13 #define ASPEED_JTAG_NUM 2 #define ASPEED_PCIE_NUM 3 +#define ASPEED_INTC_NUM 2 #define ASPEED_IOEXP_NUM 2 =20 struct AspeedSoCState { @@ -146,7 +147,8 @@ struct Aspeed27x0SoCState { AspeedSoCState parent; =20 ARMCPU cpu[ASPEED_CPUS_NUM]; - AspeedINTCState intc[2]; + AspeedINTCState intc[ASPEED_INTC_NUM]; + AspeedINTCState intcioexp[ASPEED_IOEXP_NUM]; GICv3State gic; MemoryRegion dram_empty; }; @@ -288,6 +290,8 @@ enum { ASPEED_DEV_LTPI_CTRL2, ASPEED_DEV_LTPI_IO0, ASPEED_DEV_LTPI_IO1, + ASPEED_DEV_IOEXP0_INTCIO, + ASPEED_DEV_IOEXP1_INTCIO, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 5d10268fff..b25ef4a464 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -15,6 +15,8 @@ #define TYPE_ASPEED_INTC "aspeed.intc" #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700" +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "-ast2700-ioexp1" +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "-ast2700-ioexp2" #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp" #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp" #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp" diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 0517a5351d..7b1c49bf16 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -91,7 +91,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_IOEXP0_INTCIO] =3D 0x30C18000, [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, + [ASPEED_DEV_IOEXP1_INTCIO] =3D 0x50C18000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, @@ -444,6 +446,10 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INT= C); object_initialize_child(obj, "intcio", &a->intc[1], TYPE_ASPEED_2700_INTCIO); + object_initialize_child(obj, "intc-ioexp0", &a->intcioexp[0], + TYPE_ASPEED_2700_INTCIOEXP1); + object_initialize_child(obj, "intc-ioexp1", &a->intcioexp[1], + TYPE_ASPEED_2700_INTCIOEXP2); =20 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "adc", &s->adc, typename); @@ -688,6 +694,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0, sc->memmap[ASPEED_DEV_INTCIO]); =20 + /* INTCIOEXP0 */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) { + return; + } + + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]), 0, + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]); + + /* INTCIOEXP1 */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) { + return; + } + + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]), 0, + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]); + /* irq sources -> orgates -> INTC */ for (i =3D 0; i < ic->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, @@ -1004,6 +1026,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0, sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); + + icio =3D ASPEED_INTC_GET_CLASS(&a->intcioexp[i]); + /* INTC_IOEXP internal: orgate[i] -> input[i] */ + for (int j =3D 0; j < icio->num_inpins; j++) { + irq =3D qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j); + qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]), 0, + irq); + } + + /* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */ + for (int j =3D 0; j < icio->num_outpins; j++) { + irq =3D qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j); + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j, + irq); + } } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 77fae39205..52f2f946d5 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -793,6 +793,64 @@ static const TypeInfo aspeed_2700_intc_info =3D { .class_init =3D aspeed_2700_intc_class_init, }; =20 +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP2 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp2_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp2_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp2_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP2, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp2_class_init, +}; + +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP1 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp1_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp1_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp1_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP1, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp1_class_init, +}; + static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] =3D { {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS}, {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS}, @@ -950,6 +1008,8 @@ static void aspeed_intc_register_types(void) type_register_static(&aspeed_intc_info); type_register_static(&aspeed_2700_intc_info); type_register_static(&aspeed_2700_intcio_info); + type_register_static(&aspeed_2700_intcioexp1_info); + type_register_static(&aspeed_2700_intcioexp2_info); type_register_static(&aspeed_2700ssp_intc_info); type_register_static(&aspeed_2700ssp_intcio_info); type_register_static(&aspeed_2700tsp_intc_info); --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886477; cv=none; d=zohomail.com; s=zohoarc; b=n+IqlLc7LjJbPRYtMmkIm9XD1aYkmmuwk4QJlXh1iW2x+fW4JGBK2PthbuhUz6V+LWoAdnyrFZw9+9DA6LZYkWAF+uSB7nL+JD2ejOr/a+HZpvbOmeoq9+ApP+TQActPi8wjLB25ZvHtlCf52FomuLwjG+4B2Bp9wfOhsVFYCEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Tue, 20 Jan 2026 00:19:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi49O-0004Ll-I7; Tue, 20 Jan 2026 00:19:34 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi49N-0004ZS-6p; Tue, 20 Jan 2026 00:19:34 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:02 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 07/22] hw/arm/aspeed: Attach LTPI controller to AST1700 model Date: Tue, 20 Jan 2026 13:18:38 +0800 Message-ID: <20260120051859.1920565-8-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886478784154100 From: Kane-Chen-AS Connect the LTPI controller to the AST1700 model by mapping its MMIO region. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 3 +++ hw/arm/aspeed_ast1700.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 378dcb437a..addea3ab1f 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -9,6 +9,7 @@ #define ASPEED_AST1700_H =20 #include "hw/core/sysbus.h" +#include "hw/misc/aspeed_ltpi.h" =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" =20 @@ -18,6 +19,8 @@ struct AspeedAST1700SoCState { SysBusDevice parent_obj; =20 MemoryRegion iomem; + + AspeedLTPIState ltpi; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index dd38b819b8..e4c8565d3f 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -13,6 +13,14 @@ =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 =20 +enum { + ASPEED_AST1700_DEV_LTPI_CTRL, +}; + +static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, +}; + static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); @@ -22,6 +30,25 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); + + /* LTPI controller */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_C= TRL], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0= )); +} + +static void aspeed_ast1700_instance_init(Object *obj) +{ + AspeedAST1700SoCState *s =3D ASPEED_AST1700(obj); + + /* LTPI controller */ + object_initialize_child(obj, "ltpi-ctrl", + &s->ltpi, TYPE_ASPEED_LTPI); + + return; } =20 static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) @@ -36,6 +63,7 @@ static const TypeInfo aspeed_ast1700_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(AspeedAST1700SoCState), .class_init =3D aspeed_ast1700_class_init, + .instance_init =3D aspeed_ast1700_instance_init, }; =20 static void aspeed_ast1700_register_types(void) --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886417; cv=none; d=zohomail.com; s=zohoarc; b=lkQ0yP1kop7bIB2cGfDn2au7y4RHqwgdWfuw7oRQ/2SxFXFIx+u314RrfFoNDFamndF3ZhCE3YNyBBOH2cXR2UeoUXYHe2uu/6zAYpXpv4qBZ4/8lNjpoCEuYclSguXLhrRcbqU/zmhy8wCcRnPuTmNKUq/XjrN9ojRWaAPbUN4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768886417; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=0sJnnYJO4I+jqtSYl1uTiErd4X36c88cKLAROJO1mlo=; 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Tue, 20 Jan 2026 00:19:36 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:03 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:03 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 08/22] hw/arm/aspeed: Attach UART device to AST1700 model Date: Tue, 20 Jan 2026 13:18:39 +0800 Message-ID: <20260120051859.1920565-9-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886419755158500 From: Kane-Chen-AS Connect the UART controller to the AST1700 model by mapping its MMIO region. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index addea3ab1f..b15b13aedd 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -10,6 +10,7 @@ =20 #include "hw/core/sysbus.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/char/serial-mm.h" =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" =20 @@ -21,6 +22,7 @@ struct AspeedAST1700SoCState { MemoryRegion iomem; =20 AspeedLTPIState ltpi; + SerialMM uart; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index e4c8565d3f..450ca6f5c7 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -9,15 +9,18 @@ #include "qemu/osdep.h" #include "hw/core/boards.h" #include "qom/object.h" +#include "hw/core/qdev-properties.h" #include "hw/arm/aspeed_ast1700.h" =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 =20 enum { + ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, }; =20 @@ -31,6 +34,17 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); =20 + /* UART */ + qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2); + qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400); + qdev_prop_set_uint8(DEVICE(&s->uart), "endianness", DEVICE_LITTLE_ENDI= AN); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12= ], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0= )); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -44,6 +58,10 @@ static void aspeed_ast1700_instance_init(Object *obj) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(obj); =20 + /* UART */ + object_initialize_child(obj, "uart[*]", &s->uart, + TYPE_SERIAL_MM); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886644; cv=none; d=zohomail.com; s=zohoarc; b=S1NkBpVs6WXrfrFNUMtW0PkBZ8F8XK3ybNZO1e4O7H9xL/N6H+r1/EoT4wzu8occL/DwQi34uNdN4NL3WgSnjJfJgWfHmo64IfPgnq92P+qP1Kl1/4agwgdMkgkGL2QAt3qHBpZ5aRQYBz2fdQdgOs+nwBtvH4xtM5LsyMZCKFg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768886644; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 20 Jan 2026 00:19:38 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:03 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:03 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 09/22] hw/arm/aspeed: Attach SRAM device to AST1700 model Date: Tue, 20 Jan 2026 13:18:40 +0800 Message-ID: <20260120051859.1920565-10-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886647166154100 From: Kane-Chen-AS Map the SRAM device to AST1700 model Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 17 +++++++++++++++++ hw/arm/aspeed_ast27x0.c | 1 + 3 files changed, 20 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index b15b13aedd..a981bff3b2 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -20,9 +20,11 @@ struct AspeedAST1700SoCState { SysBusDevice parent_obj; =20 MemoryRegion iomem; + uint8_t board_idx; =20 AspeedLTPIState ltpi; SerialMM uart; + MemoryRegion sram; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 450ca6f5c7..c82825d71d 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -13,13 +13,16 @@ #include "hw/arm/aspeed_ast1700.h" =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 +#define AST1700_SOC_SRAM_SIZE 0x00040000 =20 enum { + ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, }; @@ -28,12 +31,21 @@ static void aspeed_ast1700_realize(DeviceState *dev, Er= ror **errp) { AspeedAST1700SoCState *s =3D ASPEED_AST1700(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + char dev_name[32]; =20 /* Occupy memory space for all controllers in AST1700 */ memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, AST2700_SOC_LTPI_SIZE); sysbus_init_mmio(sbd, &s->iomem); =20 + /* SRAM */ + snprintf(dev_name, sizeof(dev_name), "aspeed.ioexp-sram.%d", s->board_= idx); + memory_region_init_ram(&s->sram, OBJECT(s), dev_name, + AST1700_SOC_SRAM_SIZE, errp); + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SR= AM], + &s->sram); + /* UART */ qdev_prop_set_uint8(DEVICE(&s->uart), "regshift", 2); qdev_prop_set_uint32(DEVICE(&s->uart), "baudbase", 38400); @@ -69,11 +81,16 @@ static void aspeed_ast1700_instance_init(Object *obj) return; } =20 +static const Property aspeed_ast1700_props[] =3D { + DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0), +}; + static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D aspeed_ast1700_realize; + device_class_set_props(dc, aspeed_ast1700_props); } =20 static const TypeInfo aspeed_ast1700_info =3D { diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 7b1c49bf16..6933d03fbf 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1021,6 +1021,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) =20 /* IO Expander */ for (i =3D 0; i < sc->ioexp_num; i++) { + qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { return; } --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886520; cv=none; d=zohomail.com; s=zohoarc; b=Kv1PPS4An4SbLBpl7MWXt+PPE3BjSgRiwflT9wHKEequCaOuD3Ti21Z35K5LBPeTaVEhsG3Zi9UnTEeUvwRpgFnjXUa2yuh2CPfHdIdhAXIyYb0ovJpFse4INdnsTT3Ya5bhwaBcOzL0bkogZ43mCbL7QOCjrJOeT+T3U8nds48= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768886520; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 20 Jan 2026 00:19:41 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:03 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:03 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 10/22] hw/arm/aspeed: Attach SPI device to AST1700 model Date: Tue, 20 Jan 2026 13:18:41 +0800 Message-ID: <20260120051859.1920565-11-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Kane-Chen-AS Connect the SPI device to AST1700 model. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_ast1700.h | 3 +++ hw/arm/aspeed_ast1700.c | 30 ++++++++++++++++++++++++++++++ hw/arm/aspeed_ast27x0.c | 2 ++ 3 files changed, 35 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index a981bff3b2..89562eb64f 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -10,6 +10,7 @@ =20 #include "hw/core/sysbus.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/ssi/aspeed_smc.h" #include "hw/char/serial-mm.h" =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" @@ -20,11 +21,13 @@ struct AspeedAST1700SoCState { SysBusDevice parent_obj; =20 MemoryRegion iomem; + MemoryRegion *dram_mr; uint8_t board_idx; =20 AspeedLTPIState ltpi; SerialMM uart; MemoryRegion sram; + AspeedSMCState spi; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index c82825d71d..49f9b67c91 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "hw/core/boards.h" #include "qom/object.h" +#include "qapi/error.h" #include "hw/core/qdev-properties.h" #include "hw/arm/aspeed_ast1700.h" =20 @@ -16,15 +17,19 @@ #define AST1700_SOC_SRAM_SIZE 0x00040000 =20 enum { + ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, + ASPEED_AST1700_DEV_SPI0_MEM, }; =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { + [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, + [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, }; =20 static void aspeed_ast1700_realize(DeviceState *dev, Error **errp) @@ -33,6 +38,11 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); char dev_name[32]; =20 + if (!s->dram_mr) { + error_setg(errp, TYPE_ASPEED_AST1700 ": 'dram' link not set"); + return; + } + /* Occupy memory space for all controllers in AST1700 */ memory_region_init(&s->iomem, OBJECT(s), TYPE_ASPEED_AST1700, AST2700_SOC_LTPI_SIZE); @@ -57,6 +67,20 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_UART12= ], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0= )); =20 + /* SPI */ + object_property_set_link(OBJECT(&s->spi), "dram", + OBJECT(s->dram_mr), errp); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 0)= ); + + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_M= EM], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -74,6 +98,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "uart[*]", &s->uart, TYPE_SERIAL_MM); =20 + /* SPI */ + object_initialize_child(obj, "ioexp-spi[*]", &s->spi, + "aspeed.spi0-ast2700"); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); @@ -83,6 +111,8 @@ static void aspeed_ast1700_instance_init(Object *obj) =20 static const Property aspeed_ast1700_props[] =3D { DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0), + DEFINE_PROP_LINK("dram", AspeedAST1700SoCState, dram_mr, + TYPE_MEMORY_REGION, MemoryRegion *), }; =20 static void aspeed_ast1700_class_init(ObjectClass *klass, const void *data) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6933d03fbf..158f44782b 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1022,6 +1022,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) /* IO Expander */ for (i =3D 0; i < sc->ioexp_num; i++) { qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i); + object_property_set_link(OBJECT(&s->ioexp[i]), "dram", + OBJECT(s->dram_mr), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->ioexp[i]), errp)) { return; } --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886677; cv=none; d=zohomail.com; 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Tue, 20 Jan 2026 13:19:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 11/22] hw/arm/aspeed: Attach ADC device to AST1700 model Date: Tue, 20 Jan 2026 13:18:42 +0800 Message-ID: <20260120051859.1920565-12-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886679703154100 From: Kane-Chen-AS Connect the ADC device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 14 ++++++++++++++ hw/arm/aspeed_ast27x0.c | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 89562eb64f..441655cee7 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -9,6 +9,7 @@ #define ASPEED_AST1700_H =20 #include "hw/core/sysbus.h" +#include "hw/adc/aspeed_adc.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" #include "hw/char/serial-mm.h" @@ -28,6 +29,7 @@ struct AspeedAST1700SoCState { SerialMM uart; MemoryRegion sram; AspeedSMCState spi; + AspeedADCState adc; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 49f9b67c91..3b3cd9c585 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -19,6 +19,7 @@ enum { ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, + ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -27,6 +28,7 @@ enum { static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, + [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -81,6 +83,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SPI0_M= EM], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->spi), 1)= ); =20 + /* ADC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -102,6 +112,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-spi[*]", &s->spi, "aspeed.spi0-ast2700"); =20 + /* ADC */ + object_initialize_child(obj, "ioexp-adc[*]", &s->adc, + "aspeed.adc-ast2700"); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 158f44782b..9b5383dfea 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1044,6 +1044,10 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j, irq); } + + /* ADC */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC)); } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886450; cv=none; d=zohomail.com; s=zohoarc; b=U3b6eP+lOV1b8B5oSNCFwLn8gU+8ormEipqdZ4fh+tLSrFPfWFS8W15qcy4/uFv6+rMFFwxBk4QG5vzidWcLvEsobo2Yonfx8Su136Ctd7xlh82CQV3er1ioQ5czczyThlZeMqd5j5eGariy7nLrUtUzTFkelyOK2zZCsv+pCxE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768886450; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 20 Jan 2026 00:19:46 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 12/22] hw/arm/aspeed: Attach SCU device to AST1700 model Date: Tue, 20 Jan 2026 13:18:43 +0800 Message-ID: <20260120051859.1920565-13-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886451490158500 From: Kane-Chen-AS Connect the SCU device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan w --- include/hw/arm/aspeed_ast1700.h | 3 +++ hw/arm/aspeed_ast1700.c | 17 +++++++++++++++++ hw/arm/aspeed_ast27x0.c | 2 ++ 3 files changed, 22 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 441655cee7..65f1497a2d 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -9,6 +9,7 @@ #define ASPEED_AST1700_H =20 #include "hw/core/sysbus.h" +#include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" @@ -24,12 +25,14 @@ struct AspeedAST1700SoCState { MemoryRegion iomem; MemoryRegion *dram_mr; uint8_t board_idx; + uint32_t silicon_rev; =20 AspeedLTPIState ltpi; SerialMM uart; MemoryRegion sram; AspeedSMCState spi; AspeedADCState adc; + AspeedSCUState scu; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 3b3cd9c585..82f4568af9 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -20,6 +20,7 @@ enum { ASPEED_AST1700_DEV_SPI0, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, + ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -29,6 +30,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, + [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -91,6 +93,16 @@ static void aspeed_ast1700_realize(DeviceState *dev, Err= or **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_ADC], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->adc), 0)= ); =20 + /* SCU */ + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", + s->silicon_rev); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -116,6 +128,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-adc[*]", &s->adc, "aspeed.adc-ast2700"); =20 + /* SCU */ + object_initialize_child(obj, "ioexp-scu[*]", &s->scu, + TYPE_ASPEED_2700_SCU); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); @@ -125,6 +141,7 @@ static void aspeed_ast1700_instance_init(Object *obj) =20 static const Property aspeed_ast1700_props[] =3D { DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0), + DEFINE_PROP_UINT32("silicon-rev", AspeedAST1700SoCState, silicon_rev, = 0), DEFINE_PROP_LINK("dram", AspeedAST1700SoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), }; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 9b5383dfea..dc7a5b8677 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -506,6 +506,8 @@ static void aspeed_soc_ast2700_init(Object *obj) /* AST1700 IOEXP */ object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], TYPE_ASPEED_AST1700); + qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev", + sc->silicon_rev); } =20 object_initialize_child(obj, "dpmcu", &s->dpmcu, --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886516; cv=none; d=zohomail.com; s=zohoarc; b=dW1HiEelMUN44wAvoL9U53D8t1t95UfK/csSkxkaHYrqb4qA4lr8xg2LGKmIPQ7Ox003IY6EvEfD+lQiPyaX/rZWb6WH1eWO2vz6AO1tsXdf2RYNL6PkkjDfFxfRifJ+G8ZHWzY8ngOKEbu5lo/DgC+Z9jNzUmO4P6CPmd3gI+o= ARC-Message-Signature: i=1; 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Tue, 20 Jan 2026 00:20:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi4AA-0005Y8-9v; Tue, 20 Jan 2026 00:20:22 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi4A8-0004v7-Qb; Tue, 20 Jan 2026 00:20:22 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:04 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:04 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 13/22] hw/arm/aspeed: Attach GPIO device to AST1700 model Date: Tue, 20 Jan 2026 13:18:44 +0800 Message-ID: <20260120051859.1920565-14-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886517619158500 From: Kane-Chen-AS Connect the GPIO controller to the AST1700 model by mapping its MMIO region and wiring its interrupt line. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 14 ++++++++++++++ hw/arm/aspeed_ast27x0.c | 5 +++++ 3 files changed, 21 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 65f1497a2d..63cfcb4c24 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -11,6 +11,7 @@ #include "hw/core/sysbus.h" #include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" +#include "hw/gpio/aspeed_gpio.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" #include "hw/char/serial-mm.h" @@ -33,6 +34,7 @@ struct AspeedAST1700SoCState { AspeedSMCState spi; AspeedADCState adc; AspeedSCUState scu; + AspeedGPIOState gpio; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 82f4568af9..c7eaf583e2 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -21,6 +21,7 @@ enum { ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, + ASPEED_AST1700_DEV_GPIO, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -31,6 +32,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, + [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -103,6 +105,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SCU], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->scu), 0)= ); =20 + /* GPIO */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0= )); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -132,6 +142,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-scu[*]", &s->scu, TYPE_ASPEED_2700_SCU); =20 + /* GPIO */ + object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio, + "aspeed.gpio-ast2700"); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index dc7a5b8677..58977e2fa3 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1050,6 +1050,11 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) /* ADC */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].adc), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_ADC)); + + /* GPIO */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); + } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886490; cv=none; d=zohomail.com; s=zohoarc; b=hdC+lMENI0uGMWTyqVZ0bCxnBkNwl2ZqG6p9byxS/61LOBQrbb5f/mDEyJJtkstcsmyBOcFvYevIvARcoM8H1mVa1aYqKFObtXMmxbeDt/lTzg7l1RuT1U8PYc0nhK6SgPhjmaKUdy2H65L+OxLiFdXQHE0SESpjEIni2SaXC48= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768886490; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 20 Jan 2026 00:20:24 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:05 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 14/22] hw/arm/aspeed: Introduce 'bus-label' property for AST1700 SoC Date: Tue, 20 Jan 2026 13:18:45 +0800 Message-ID: <20260120051859.1920565-15-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Kane-Chen-AS The AST2700 SoC can be integrated with multiple AST1700 IO expanders. Without unique identifiers, the I2C bus object names for the primary BMC SoC and multiple expander chips may collide in the QOM (QEMU Object Model) tree. To resolve this, introduce a bus-label property to the AST1700 SoC. This allows the parent SoC (AST2700) to assign a unique prefix (e.g., "ioexp0", "ioexp1") to each AST1700 instance. These labels ensure that the bus naming hierarchy remains distinct and traceable across different expanders. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_ast1700.h | 1 + hw/arm/aspeed_ast1700.c | 1 + hw/arm/aspeed_ast27x0.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 63cfcb4c24..d364203175 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -27,6 +27,7 @@ struct AspeedAST1700SoCState { MemoryRegion *dram_mr; uint8_t board_idx; uint32_t silicon_rev; + char *bus_label; =20 AspeedLTPIState ltpi; SerialMM uart; diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index c7eaf583e2..0f2d2c381d 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -156,6 +156,7 @@ static void aspeed_ast1700_instance_init(Object *obj) static const Property aspeed_ast1700_props[] =3D { DEFINE_PROP_UINT8("board-idx", AspeedAST1700SoCState, board_idx, 0), DEFINE_PROP_UINT32("silicon-rev", AspeedAST1700SoCState, silicon_rev, = 0), + DEFINE_PROP_STRING("bus-label", AspeedAST1700SoCState, bus_label), DEFINE_PROP_LINK("dram", AspeedAST1700SoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), }; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 58977e2fa3..b4b5afe6d3 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -503,11 +503,14 @@ static void aspeed_soc_ast2700_init(Object *obj) } =20 for (i =3D 0; i < sc->ioexp_num; i++) { + g_autofree char *bus_label =3D g_strdup_printf("ioexp%d", i); /* AST1700 IOEXP */ object_initialize_child(obj, "ioexp[*]", &s->ioexp[i], TYPE_ASPEED_AST1700); qdev_prop_set_uint32(DEVICE(&s->ioexp[i]), "silicon-rev", sc->silicon_rev); + qdev_prop_set_string(DEVICE(&s->ioexp[i]), "bus-label", + bus_label); } =20 object_initialize_child(obj, "dpmcu", &s->dpmcu, --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886488; 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Tue, 20 Jan 2026 13:19:05 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 15/22] hw/arm/aspeed: attach I2C device to AST1700 model Date: Tue, 20 Jan 2026 13:18:46 +0800 Message-ID: <20260120051859.1920565-16-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886491355154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS Connect the I2C controller to the AST1700 model by mapping its MMIO region and wiring its interrupt line. Signed-off-by: Kane-Chen-AS --- include/hw/arm/aspeed_ast1700.h | 2 ++ include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed_ast1700.c | 22 ++++++++++++++ hw/arm/aspeed_ast27x0.c | 51 +++++++++++++++++++++++++++++++-- 4 files changed, 74 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index d364203175..7b68b23a84 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -12,6 +12,7 @@ #include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" #include "hw/gpio/aspeed_gpio.h" +#include "hw/i2c/aspeed_i2c.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" #include "hw/char/serial-mm.h" @@ -36,6 +37,7 @@ struct AspeedAST1700SoCState { AspeedADCState adc; AspeedSCUState scu; AspeedGPIOState gpio; + AspeedI2CState i2c; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index b051d0eb3a..4ea2521041 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -290,6 +290,8 @@ enum { ASPEED_DEV_LTPI_CTRL2, ASPEED_DEV_LTPI_IO0, ASPEED_DEV_LTPI_IO1, + ASPEED_DEV_IOEXP0_I2C, + ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, }; diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 0f2d2c381d..ce43fd8988 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -22,6 +22,7 @@ enum { ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_GPIO, + ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_SPI0_MEM, @@ -33,6 +34,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, + [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, @@ -113,6 +115,22 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_GPIO], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0= )); =20 + /* I2C */ + if (s->bus_label) { + qdev_prop_set_string(DEVICE(&s->i2c), "bus-label", s->bus_label); + } else { + snprintf(dev_name, sizeof(dev_name), "ioexp%d.i2c.bus", s->board_i= dx); + qdev_prop_set_string(DEVICE(&s->i2c), "bus-label", dev_name); + } + object_property_set_link(OBJECT(&s->i2c), "dram", + OBJECT(s->dram_mr), errp); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -146,6 +164,10 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-gpio[*]", &s->gpio, "aspeed.gpio-ast2700"); =20 + /* I2C */ + object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c, + "aspeed.i2c-ast2700"); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index b4b5afe6d3..ca35a11291 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -155,6 +155,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_ETH3] =3D 196, [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, + [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP1_I2C] =3D 200, }; =20 /* GICINT 192 */ @@ -211,6 +213,18 @@ static const int ast2700_gic197_intcmap[] =3D { [ASPEED_DEV_PECI] =3D 4, }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GICINT 198 */ +static const int ast2700_gic198_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ +}; + +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 200 */ +static const int ast2700_gic200_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ +}; + /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { int irq; @@ -226,9 +240,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcm= ap[] =3D { {195, 1, 3, ast2700_gic195_intcmap}, {196, 1, 4, ast2700_gic196_intcmap}, {197, 1, 5, ast2700_gic197_intcmap}, - {198, 1, 6, NULL}, + {198, 2, 0, ast2700_gic198_intcmap}, {199, 1, 7, NULL}, - {200, 1, 8, NULL}, + {200, 3, 0, ast2700_gic200_intcmap}, {201, 1, 9, NULL}, }; =20 @@ -261,14 +275,23 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(Aspe= edSoCState *s, int dev, int or_idx; int idx; int i; + OrIRQState *porgates; =20 for (i =3D 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) { if (sc->irqmap[dev] =3D=3D ast2700_gic_intcmap[i].irq) { assert(ast2700_gic_intcmap[i].ptr); or_idx =3D ast2700_gic_intcmap[i].orgate_idx; idx =3D ast2700_gic_intcmap[i].intc_idx; - return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]), + if (idx < ASPEED_INTC_NUM) { + porgates =3D &a->intc[idx].orgates[or_idx]; + return qdev_get_gpio_in(DEVICE(porgates), + ast2700_gic_intcmap[i].ptr[dev] + inde= x); + } else { + idx -=3D ASPEED_INTC_NUM; + porgates =3D &a->intcioexp[idx].orgates[or_idx]; + return qdev_get_gpio_in(DEVICE(porgates), ast2700_gic_intcmap[i].ptr[dev] + inde= x); + } } } =20 @@ -1026,6 +1049,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) =20 /* IO Expander */ for (i =3D 0; i < sc->ioexp_num; i++) { + AspeedI2CClass *i2c_ctl; + qdev_prop_set_uint8(DEVICE(&s->ioexp[i]), "board-idx", i); object_property_set_link(OBJECT(&s->ioexp[i]), "dram", OBJECT(s->dram_mr), &error_abort); @@ -1058,6 +1083,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].gpio), 0, aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO)); =20 + /* I2C */ + i2c_ctl =3D ASPEED_I2C_GET_CLASS(&s->ioexp[i].i2c); + for (int j =3D 0; j < i2c_ctl->num_busses; j++) { + /* + * For I2C on AST1700: + * I2C bus interrupts are connected to the OR gate from bit 0 = to bit + * 15, and the OR gate output pin is connected to the input pi= n of + * GICINT192 of IO expander Interrupt controller (INTC2/3). Th= en, + * the output pin is connected to the INTC (CPU Die) input pin= , and + * its output pin is connected to the GIC. + * + * I2C bus 0 is connected to the OR gate at bit 0. + * I2C bus 15 is connected to the OR gate at bit 15. + */ + irq =3D aspeed_soc_ast2700_get_irq_index(s, + ASPEED_DEV_IOEXP0_I2C += i, + j); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioexp[i].i2c.busses[j]), + 0, irq); + } } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886458; cv=none; d=zohomail.com; s=zohoarc; b=AhYTcrT6HEjk4MlUuEzp/i4ZW75LrCzF5PWOWRbtCc3fuah4KHUrqy2UJGgs7trJnDAHkwQ8XbWYvqksZK4Dh8tkmV07/ezDuXiDgIIHtfiQ+BgClCHBakN03tgrUMygOmIEkpvI2VSF4oHzEn43CtN87xKXZ96EtWh922nn6W4= ARC-Message-Signature: i=1; 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Tue, 20 Jan 2026 00:20:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi4AJ-000603-Jo; Tue, 20 Jan 2026 00:20:35 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi4AI-0004v7-08; Tue, 20 Jan 2026 00:20:31 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 16/22] hw/arm/aspeed: Attach WDT device to AST1700 model Date: Tue, 20 Jan 2026 13:18:47 +0800 Message-ID: <20260120051859.1920565-17-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886459765158500 From: Kane-Chen-AS Connect the WDT device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 4 ++++ hw/arm/aspeed_ast1700.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 7b68b23a84..a830392798 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -15,8 +15,11 @@ #include "hw/i2c/aspeed_i2c.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/ssi/aspeed_smc.h" +#include "hw/watchdog/wdt_aspeed.h" #include "hw/char/serial-mm.h" =20 +#define AST1700_WDT_NUM 9 + #define TYPE_ASPEED_AST1700 "aspeed.ast1700" =20 OBJECT_DECLARE_SIMPLE_TYPE(AspeedAST1700SoCState, ASPEED_AST1700) @@ -38,6 +41,7 @@ struct AspeedAST1700SoCState { AspeedSCUState scu; AspeedGPIOState gpio; AspeedI2CState i2c; + AspeedWDTState wdt[AST1700_WDT_NUM]; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index ce43fd8988..94e0110501 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -25,6 +25,7 @@ enum { ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, + ASPEED_AST1700_DEV_WDT, ASPEED_AST1700_DEV_SPI0_MEM, }; =20 @@ -37,6 +38,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, + [ASPEED_AST1700_DEV_WDT] =3D 0x00C37000, [ASPEED_AST1700_DEV_SPI0_MEM] =3D 0x04000000, }; =20 @@ -138,6 +140,22 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) memory_region_add_subregion(&s->iomem, aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_C= TRL], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0= )); + /* WDT */ + for (int i =3D 0; i < AST1700_WDT_NUM; i++) { + AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); + hwaddr wdt_offset =3D aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_= WDT] + + i * awc->iosize; + + object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), + errp); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + wdt_offset, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]),= 0)); + } + } =20 static void aspeed_ast1700_instance_init(Object *obj) @@ -172,6 +190,12 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); =20 + /* WDT */ + for (int i =3D 0; i < AST1700_WDT_NUM; i++) { + object_initialize_child(obj, "ioexp-wdt[*]", + &s->wdt[i], "aspeed.wdt-ast2700"); + } + return; } =20 --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886612; cv=none; d=zohomail.com; s=zohoarc; b=dp6Nxhi+DWZqBWYPZoYlxBn2Yp6apv2Cz96V4OOmKztF7TkxbmfC6d3V/yqPWYLVaBD0x6n8Qh5v9EcMx3XHAvmPLM5XY3Bgt59olWO0jmSsjfAeT86x1dUqijO74rm2DaaIgYDfcY7VaKY8TpXDGRkWYIriAffT/9FahFRV5YI= ARC-Message-Signature: i=1; a=rsa-sha256; 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Tue, 20 Jan 2026 00:20:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi4AM-00067m-Tz; Tue, 20 Jan 2026 00:20:38 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi4AK-0004v7-Kw; Tue, 20 Jan 2026 00:20:33 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 17/22] hw/arm/aspeed: Attach PWM device to AST1700 model Date: Tue, 20 Jan 2026 13:18:48 +0800 Message-ID: <20260120051859.1920565-18-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886614345158500 From: Kane-Chen-AS Connect the PWM device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 2 ++ hw/arm/aspeed_ast1700.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index a830392798..5fc363d0c2 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -14,6 +14,7 @@ #include "hw/gpio/aspeed_gpio.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/misc/aspeed_ltpi.h" +#include "hw/misc/aspeed_pwm.h" #include "hw/ssi/aspeed_smc.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/char/serial-mm.h" @@ -41,6 +42,7 @@ struct AspeedAST1700SoCState { AspeedSCUState scu; AspeedGPIOState gpio; AspeedI2CState i2c; + AspeedPWMState pwm; AspeedWDTState wdt[AST1700_WDT_NUM]; }; =20 diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 94e0110501..108804f35b 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -18,6 +18,7 @@ =20 enum { ASPEED_AST1700_DEV_SPI0, + ASPEED_AST1700_DEV_PWM, ASPEED_AST1700_DEV_SRAM, ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, @@ -31,6 +32,7 @@ enum { =20 static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SPI0] =3D 0x00030000, + [ASPEED_AST1700_DEV_PWM] =3D 0x000C0000, [ASPEED_AST1700_DEV_SRAM] =3D 0x00BC0000, [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, @@ -133,6 +135,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I2C], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i2c), 0)= ); =20 + /* PWM */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_PWM], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pwm), 0)= ); + /* LTPI controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ltpi), errp)) { return; @@ -186,6 +196,9 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ioexp-i2c[*]", &s->i2c, "aspeed.i2c-ast2700"); =20 + /* PWM */ + object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM); + /* LTPI controller */ object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768886547091761.6999994225364; Mon, 19 Jan 2026 21:22:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vi4AY-0006oI-WB; Tue, 20 Jan 2026 00:20:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi4AP-000685-6I; Tue, 20 Jan 2026 00:20:38 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vi4AN-0004v7-MR; Tue, 20 Jan 2026 00:20:36 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:06 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:06 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 18/22] hw/arm/aspeed: Attach SGPIOM device to AST1700 model Date: Tue, 20 Jan 2026 13:18:49 +0800 Message-ID: <20260120051859.1920565-19-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886548111158500 From: Kane-Chen-AS Connect the SGPIOM device to AST1700 model. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 3 +++ hw/arm/aspeed_ast1700.c | 21 +++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index 5fc363d0c2..c50987fc76 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -12,6 +12,7 @@ #include "hw/misc/aspeed_scu.h" #include "hw/adc/aspeed_adc.h" #include "hw/gpio/aspeed_gpio.h" +#include "hw/gpio/aspeed_sgpio.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/misc/aspeed_ltpi.h" #include "hw/misc/aspeed_pwm.h" @@ -19,6 +20,7 @@ #include "hw/watchdog/wdt_aspeed.h" #include "hw/char/serial-mm.h" =20 +#define AST1700_SGPIO_NUM 2 #define AST1700_WDT_NUM 9 =20 #define TYPE_ASPEED_AST1700 "aspeed.ast1700" @@ -41,6 +43,7 @@ struct AspeedAST1700SoCState { AspeedADCState adc; AspeedSCUState scu; AspeedGPIOState gpio; + AspeedSGPIOState sgpiom[AST1700_SGPIO_NUM]; AspeedI2CState i2c; AspeedPWMState pwm; AspeedWDTState wdt[AST1700_WDT_NUM]; diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 108804f35b..06c35a3a36 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -23,6 +23,8 @@ enum { ASPEED_AST1700_DEV_ADC, ASPEED_AST1700_DEV_SCU, ASPEED_AST1700_DEV_GPIO, + ASPEED_AST1700_DEV_SGPIOM0, + ASPEED_AST1700_DEV_SGPIOM1, ASPEED_AST1700_DEV_I2C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, @@ -37,6 +39,8 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_ADC] =3D 0x00C00000, [ASPEED_AST1700_DEV_SCU] =3D 0x00C02000, [ASPEED_AST1700_DEV_GPIO] =3D 0x00C0B000, + [ASPEED_AST1700_DEV_SGPIOM0] =3D 0x00C0C000, + [ASPEED_AST1700_DEV_SGPIOM1] =3D 0x00C0D000, [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, @@ -150,6 +154,17 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) memory_region_add_subregion(&s->iomem, aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_LTPI_C= TRL], sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ltpi), 0= )); + + /* SGPIOM */ + for (int i =3D 0; i < AST1700_SGPIO_NUM; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) { + return; + } + memory_region_add_subregion(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_SGPIOM0 + = i], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sgpiom[i]), = 0)); + } + /* WDT */ for (int i =3D 0; i < AST1700_WDT_NUM; i++) { AspeedWDTClass *awc =3D ASPEED_WDT_GET_CLASS(&s->wdt[i]); @@ -203,6 +218,12 @@ static void aspeed_ast1700_instance_init(Object *obj) object_initialize_child(obj, "ltpi-ctrl", &s->ltpi, TYPE_ASPEED_LTPI); =20 + /* SGPIOM */ + for (int i =3D 0; i < AST1700_SGPIO_NUM; i++) { + object_initialize_child(obj, "ioexp-sgpiom[*]", &s->sgpiom[i], + "aspeed.sgpio-ast2700"); + } + /* WDT */ for (int i =3D 0; i < AST1700_WDT_NUM; i++) { object_initialize_child(obj, "ioexp-wdt[*]", --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 20 Jan 2026 13:19:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:07 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 19/22] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Date: Tue, 20 Jan 2026 13:18:50 +0800 Message-ID: <20260120051859.1920565-20-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886467550158500 From: Kane-Chen-AS AST1700 exposes more I3C buses than the current dummy I3C model provides. When Linux probes the I3C devices on AST1700 this mismatch can trigger a kernel panic. Model the I3C block as an unimplemented device to make the missing functionality explicit and avoid unexpected side effects. This wires up the I3C interrupt lines for the IO expanders and adds the corresponding device entries for the AST1700 model. No functional I3C emulation is provided yet; this only prevents crashes and documents the missing piece. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- include/hw/arm/aspeed_ast1700.h | 3 +++ include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed_ast1700.c | 15 +++++++++++++++ hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++-- 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index c50987fc76..af2445f4cd 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -19,6 +19,7 @@ #include "hw/ssi/aspeed_smc.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/char/serial-mm.h" +#include "hw/misc/unimp.h" =20 #define AST1700_SGPIO_NUM 2 #define AST1700_WDT_NUM 9 @@ -47,6 +48,8 @@ struct AspeedAST1700SoCState { AspeedI2CState i2c; AspeedPWMState pwm; AspeedWDTState wdt[AST1700_WDT_NUM]; + + UnimplementedDeviceState i3c; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 4ea2521041..b185b04186 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -294,6 +294,8 @@ enum { ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, + ASPEED_DEV_IOEXP0_I3C, + ASPEED_DEV_IOEXP1_I3C, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 06c35a3a36..0b6fdee208 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -15,6 +15,7 @@ =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 #define AST1700_SOC_SRAM_SIZE 0x00040000 +#define AST1700_SOC_I3C_SIZE 0x00010000 =20 enum { ASPEED_AST1700_DEV_SPI0, @@ -26,6 +27,7 @@ enum { ASPEED_AST1700_DEV_SGPIOM0, ASPEED_AST1700_DEV_SGPIOM1, ASPEED_AST1700_DEV_I2C, + ASPEED_AST1700_DEV_I3C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_WDT, @@ -42,6 +44,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SGPIOM0] =3D 0x00C0C000, [ASPEED_AST1700_DEV_SGPIOM1] =3D 0x00C0D000, [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, + [ASPEED_AST1700_DEV_I3C] =3D 0x00C20000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_WDT] =3D 0x00C37000, @@ -181,6 +184,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]),= 0)); } =20 + /* I3C */ + qdev_prop_set_string(DEVICE(&s->i3c), "name", "ioexp-i3c"); + qdev_prop_set_uint64(DEVICE(&s->i3c), "size", AST1700_SOC_I3C_SIZE); + sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp); + memory_region_add_subregion_overlap(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I3C], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i3c), 0), + -1000); } =20 static void aspeed_ast1700_instance_init(Object *obj) @@ -230,6 +241,10 @@ static void aspeed_ast1700_instance_init(Object *obj) &s->wdt[i], "aspeed.wdt-ast2700"); } =20 + /* I3C */ + object_initialize_child(obj, "ioexp-i3c[*]", &s->i3c, + TYPE_UNIMPLEMENTED_DEVICE); + return; } =20 diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index ca35a11291..bad2028bc9 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -156,7 +156,9 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP0_I3C] =3D 199, [ASPEED_DEV_IOEXP1_I2C] =3D 200, + [ASPEED_DEV_IOEXP1_I3C] =3D 201, }; =20 /* GICINT 192 */ @@ -219,12 +221,24 @@ static const int ast2700_gic198_intcmap[] =3D { [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GINTC 199 */ +static const int ast2700_gic199_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I3C] =3D 0, /* 0 - 15 */ +}; + /* Secondary AST1700 Interrupts */ /* A1: GINTC 200 */ static const int ast2700_gic200_intcmap[] =3D { [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ }; =20 +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 201 */ +static const int ast2700_gic201_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I3C] =3D 0, /* 0 - 15 */ +}; + /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { int irq; @@ -241,9 +255,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcm= ap[] =3D { {196, 1, 4, ast2700_gic196_intcmap}, {197, 1, 5, ast2700_gic197_intcmap}, {198, 2, 0, ast2700_gic198_intcmap}, - {199, 1, 7, NULL}, + {199, 2, 1, ast2700_gic199_intcmap}, {200, 3, 0, ast2700_gic200_intcmap}, - {201, 1, 9, NULL}, + {201, 3, 1, ast2700_gic201_intcmap}, }; =20 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1768886578; cv=none; d=zohomail.com; s=zohoarc; b=eNdCavLB0VAxahW08SNw9FUFKgFJnNPbHtN8siR2KJ1mFkfRASZ6W1aBz8oIOzo4LF+hXjYRqqg0lZIhzdEcjirJVOF58Mh0h3JqFl+YJtlZQGtgxL7Bv5OjB0WKjvRXIxzJ5dCdoftx7BlPxi/BTg5EQujD0OvV6BppbSRMckk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768886578; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Tue, 20 Jan 2026 00:21:02 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 20 Jan 2026 13:19:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:07 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PATCH v5 20/22] hw/arm/aspeed: Enable AST1700 IO expander support Date: Tue, 20 Jan 2026 13:18:51 +0800 Message-ID: <20260120051859.1920565-21-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886580154154100 From: Kane-Chen-AS Set ioexp_num to 2 to enable AST1700 IO expander support. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan --- hw/arm/aspeed_ast27x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index bad2028bc9..8118522d7e 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1161,7 +1161,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCla= ss *oc, const void *data) sc->macs_num =3D 3; sc->uarts_num =3D 13; sc->num_cpus =3D 4; - sc->ioexp_num =3D 0; + sc->ioexp_num =3D 2; sc->uarts_base =3D ASPEED_DEV_UART0; sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; sc->memmap =3D aspeed_soc_ast2700_memmap; --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Tue, 20 Jan 2026 13:19:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:08 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 21/22] test/functional/aarch64: Parameterize I2C bus ID in AST2700 test Date: Tue, 20 Jan 2026 13:18:52 +0800 Message-ID: <20260120051859.1920565-22-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=kane_chen@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Kane Chen From: Kane Chen via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1768886572395154100 Content-Type: text/plain; charset="utf-8" From: Kane-Chen-AS The current Aspeed AST2700 functional test case strictly uses I2C bus 1 for its sensor tests. This hard-coded approach prevents the test logic from being reused for other machine types or configurations where I2C bus 1 might be disabled or where a different bus needs to be verified (e.g., I2C expanders). This refactoring allows the same I2C verification logic to be shared across different test scenarios by simply passing the target bus number. Signed-off-by: Kane-Chen-AS --- .../functional/aarch64/test_aspeed_ast2700.py | 28 ++++++++++--------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functi= onal/aarch64/test_aspeed_ast2700.py index 0ced1a2502..438f7eb37c 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -15,11 +15,12 @@ =20 class AST2x00MachineSDK(QemuSystemTest): =20 - def do_test_aarch64_aspeed_sdk_start(self, image): + def do_test_aarch64_aspeed_sdk_start(self, image, bus_id): + bus_str =3D str(bus_id) self.require_netdev('user') self.vm.set_console() self.vm.add_args('-device', - 'tmp105,bus=3Daspeed.i2c.bus.1,address=3D0x4d,id= =3Dtmp-test') + f'tmp105,bus=3Daspeed.i2c.bus.{bus_str},address= =3D0x4d,id=3Dtmp-test-{bus_str}') self.vm.add_args('-drive', 'file=3D' + image + ',if=3Dmtd,format= =3Draw', '-net', 'nic', '-net', 'user', '-snapshot') =20 @@ -53,16 +54,17 @@ def verify_openbmc_boot_and_login(self, name): 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.08/ast2700-default-obmc.tar.gz', 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e= 2cd') =20 - def do_ast2700_i2c_test(self): + def do_ast2700_i2c_test(self, bus_id): + bus_str =3D str(bus_id) exec_command_and_wait_for_pattern(self, - 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-1/device/new_device ', - 'i2c i2c-1: new_device: Instantiated device lm75 at 0x4d') + f'echo lm75 0x4d > /sys/class/i2c-dev/i2c-{bus_str}/device/new= _device ', + f'i2c i2c-{bus_str}: new_device: Instantiated device lm75 at 0= x4d') exec_command_and_wait_for_pattern(self, - 'cat /sys/bus/i2c/devices/1-004d/hwmon/hwmon*/temp1_input', '0= ') - self.vm.cmd('qom-set', path=3D'/machine/peripheral/tmp-test', + f'cat /sys/bus/i2c/devices/{bus_str}-004d/hwmon/hwmon*/temp1_i= nput', '0') + self.vm.cmd('qom-set', path=3Df'/machine/peripheral/tmp-test-{bus_= str}', property=3D'temperature', value=3D18000) exec_command_and_wait_for_pattern(self, - 'cat /sys/bus/i2c/devices/1-004d/hwmon/hwmon*/temp1_input', '1= 8000') + f'cat /sys/bus/i2c/devices/{bus_str}-004d/hwmon/hwmon*/temp1_i= nput', '18000') =20 def do_ast2700_pcie_test(self): exec_command_and_wait_for_pattern(self, @@ -116,12 +118,12 @@ def start_ast2700_test(self, name): =20 self.vm.add_args('-smp', str(num_cpu)) self.do_test_aarch64_aspeed_sdk_start( - self.scratch_file(name, 'image-bmc')) + self.scratch_file(name, 'image-bmc'), 1) =20 - def start_ast2700_test_vbootrom(self, name): + def start_ast2700_test_vbootrom(self, name, bus_id): self.vm.add_args('-bios', 'ast27x0_bootrom.bin') self.do_test_aarch64_aspeed_sdk_start( - self.scratch_file(name, 'image-bmc')) + self.scratch_file(name, 'image-bmc'), bus_id) =20 def test_aarch64_ast2700a1_evb_sdk_v09_08(self): self.set_machine('ast2700a1-evb') @@ -132,7 +134,7 @@ def test_aarch64_ast2700a1_evb_sdk_v09_08(self): self.vm.add_args('-netdev', 'user,id=3Dnet1') self.start_ast2700_test('ast2700-default') self.verify_openbmc_boot_and_login('ast2700-default') - self.do_ast2700_i2c_test() + self.do_ast2700_i2c_test(1) self.do_ast2700_pcie_test() =20 def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08(self): @@ -142,7 +144,7 @@ def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08(self= ): self.archive_extract(self.ASSET_SDK_V908_AST2700A1) self.vm.add_args('-device', 'e1000e,netdev=3Dnet1,bus=3Dpcie.2') self.vm.add_args('-netdev', 'user,id=3Dnet1') - self.start_ast2700_test_vbootrom('ast2700-default') + self.start_ast2700_test_vbootrom('ast2700-default', 1) self.verify_vbootrom_firmware_flow() self.verify_openbmc_boot_start() =20 --=20 2.43.0 From nobody Sun Feb 8 19:49:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 20 Jan 2026 13:19:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 20 Jan 2026 13:19:08 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Kane-Chen-AS Subject: [PATCH v5 22/22] test/functional/aarch64: Add I2C test for AST1700 IO expanders Date: Tue, 20 Jan 2026 13:18:53 +0800 Message-ID: <20260120051859.1920565-23-kane_chen@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260120051859.1920565-1-kane_chen@aspeedtech.com> References: <20260120051859.1920565-1-kane_chen@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Kane-Chen-AS Extend the AST2700 test suite to verify I2C connectivity on AST1700 IO expanders using the DCSCM image. This validates the new bus-label naming scheme by testing communication on both primary and expander-attached I2C buses. Signed-off-by: Kane-Chen-AS --- .../functional/aarch64/test_aspeed_ast2700.py | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tests/functional/aarch64/test_aspeed_ast2700.py b/tests/functi= onal/aarch64/test_aspeed_ast2700.py index 438f7eb37c..f2bdac5177 100755 --- a/tests/functional/aarch64/test_aspeed_ast2700.py +++ b/tests/functional/aarch64/test_aspeed_ast2700.py @@ -50,10 +50,21 @@ def verify_openbmc_boot_and_login(self, name): exec_command_and_wait_for_pattern(self, 'root', 'Password:') exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~= #') =20 + def bring_up_ast1700_and_login(self, name): + wait_for_console_pattern(self, 'Hit any key to stop autoboot') + exec_command_and_wait_for_pattern(self, '0', '=3D>') + exec_command_and_wait_for_pattern(self, 'cp.b 100420000 403000000 = 800000; bootm 403000000#conf-ast2700-dcscm_ast1700-evb.dtb', f'{name} login= :') + exec_command_and_wait_for_pattern(self, 'root', 'Password:') + exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~= #') + ASSET_SDK_V908_AST2700A1 =3D Asset( 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.08/ast2700-default-obmc.tar.gz', 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e= 2cd') =20 + ASSET_SDK_V908_AST2700A1_DCSCM =3D Asset( + 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v= 09.08/ast2700-dcscm-obmc.tar.gz', + '59dc1282db886087342419824edf91806bb4f83febf916ec5350238aa5613= 268') + def do_ast2700_i2c_test(self, bus_id): bus_str =3D str(bus_id) exec_command_and_wait_for_pattern(self, @@ -148,5 +159,18 @@ def test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08(sel= f): self.verify_vbootrom_firmware_flow() self.verify_openbmc_boot_start() =20 + def test_aarch64_ast2700a1_evb_ioexp_v09_08(self): + self.set_machine('ast2700a1-evb') + self.require_netdev('user') + + self.archive_extract(self.ASSET_SDK_V908_AST2700A1_DCSCM) + self.vm.set_machine('ast2700a1-evb,fmc-model=3Dw25q512jv') + self.vm.add_args('-device', + 'tmp105,bus=3Dioexp0.0,address=3D0x4d,id=3Dtmp-te= st-16') + self.start_ast2700_test_vbootrom('ast2700-dcscm', 8) + self.bring_up_ast1700_and_login('ast2700-dcscm') + self.do_ast2700_i2c_test(8) + self.do_ast2700_i2c_test(16) + if __name__ =3D=3D '__main__': QemuSystemTest.main() --=20 2.43.0