[v2] hw/riscv: Add the Tenstorrent Atlantis machine

[PATCH v2 0/6] hw/riscv: Add the Tenstorrent Atlantis machine

Posted by Joel Stanley 3 weeks, 5 days ago

v2 separates out prep patches so the machine can be reviewed
independently. It depends on the following two series:

 AIA: https://lore.kernel.org/qemu-devel/20260109133125.397364-1-joel@jms.id.au
 Boot: https://lore.kernel.org/qemu-devel/20260109131657.396794-1-joel@jms.id.au

Original cover letter:

Introducing Tenstorrent Atlantis!

 The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
 and CoreLab Technology. It is based on the Atlantis SoC, which includes
 the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.

 The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
 RISC-V CPU.

This initial series adds the base machine support including:

 - AIA (Advanced Interrupt Architecture) support
 - PCIe controller and DesignWare I2C integration
 - Serial console and device tree generation
 - Functional tests for OpenSBI+Linux boot

Based-on: 20260114012846.981884-1-joel@jms.id.au 20260109131657.396794-1-joel@jms.id.au

Joel Stanley (3):
  hw/riscv: Add Tenstorrent Atlantis machine
  hw/riscv/atlantis: Integrate i2c buses
  hw/riscv/atlantis: Add some i2c peripherals

Nicholas Piggin (3):
  hw/riscv/atlantis: Add PCIe controller
  tests/functional/riscv64: Add tt-atlantis tests
  hw/riscv/atlantis: Use halting kernel if there is no payload

 MAINTAINERS                                  |   9 +
 docs/system/riscv/tt_atlantis.rst            |  38 +
 docs/system/target-riscv.rst                 |   1 +
 include/hw/riscv/tt_atlantis.h               |  94 ++
 hw/riscv/tt_atlantis.c                       | 916 +++++++++++++++++++
 hw/riscv/Kconfig                             |  21 +
 hw/riscv/meson.build                         |   1 +
 tests/functional/riscv64/meson.build         |   1 +
 tests/functional/riscv64/test_opensbi.py     |   4 +
 tests/functional/riscv64/test_tt_atlantis.py |  68 ++
 10 files changed, 1153 insertions(+)
 create mode 100644 docs/system/riscv/tt_atlantis.rst
 create mode 100644 include/hw/riscv/tt_atlantis.h
 create mode 100644 hw/riscv/tt_atlantis.c
 create mode 100755 tests/functional/riscv64/test_tt_atlantis.py

-- 
2.47.3

Re: [PATCH v2 0/6] hw/riscv: Add the Tenstorrent Atlantis machine

Posted by Cédric Le Goater 3 weeks, 4 days ago

Hello Joel,

On 1/14/26 05:34, Joel Stanley wrote:
> v2 separates out prep patches so the machine can be reviewed
> independently. It depends on the following two series:
> 
>   AIA: https://lore.kernel.org/qemu-devel/20260109133125.397364-1-joel@jms.id.au
>   Boot: https://lore.kernel.org/qemu-devel/20260109131657.396794-1-joel@jms.id.au
> 
> Original cover letter:
> 
> Introducing Tenstorrent Atlantis!
> 
>   The Tenstorrent Atlantis platform is a collaboration between Tenstorrent


What kind of board is the "Tenstorrent Atlantis platform" ? Is it an evb ?

>   and CoreLab Technology. It is based on the Atlantis SoC, which includes

Why isn't the SoC modeled independently ?

Thanks,

C.

>   the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.
> 
>   The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
>   RISC-V CPU.
> 
> This initial series adds the base machine support including:
> 
>   - AIA (Advanced Interrupt Architecture) support
>   - PCIe controller and DesignWare I2C integration
>   - Serial console and device tree generation
>   - Functional tests for OpenSBI+Linux boot
> 
> Based-on: 20260114012846.981884-1-joel@jms.id.au 20260109131657.396794-1-joel@jms.id.au
> 
> Joel Stanley (3):
>    hw/riscv: Add Tenstorrent Atlantis machine
>    hw/riscv/atlantis: Integrate i2c buses
>    hw/riscv/atlantis: Add some i2c peripherals
> 
> Nicholas Piggin (3):
>    hw/riscv/atlantis: Add PCIe controller
>    tests/functional/riscv64: Add tt-atlantis tests
>    hw/riscv/atlantis: Use halting kernel if there is no payload
> 
>   MAINTAINERS                                  |   9 +
>   docs/system/riscv/tt_atlantis.rst            |  38 +
>   docs/system/target-riscv.rst                 |   1 +
>   include/hw/riscv/tt_atlantis.h               |  94 ++
>   hw/riscv/tt_atlantis.c                       | 916 +++++++++++++++++++
>   hw/riscv/Kconfig                             |  21 +
>   hw/riscv/meson.build                         |   1 +
>   tests/functional/riscv64/meson.build         |   1 +
>   tests/functional/riscv64/test_opensbi.py     |   4 +
>   tests/functional/riscv64/test_tt_atlantis.py |  68 ++
>   10 files changed, 1153 insertions(+)
>   create mode 100644 docs/system/riscv/tt_atlantis.rst
>   create mode 100644 include/hw/riscv/tt_atlantis.h
>   create mode 100644 hw/riscv/tt_atlantis.c
>   create mode 100755 tests/functional/riscv64/test_tt_atlantis.py
>

Re: [PATCH v2 0/6] hw/riscv: Add the Tenstorrent Atlantis machine

Posted by Joel Stanley 3 weeks, 4 days ago

On Wed, 14 Jan 2026 at 19:36, Cédric Le Goater <clg@redhat.com> wrote:
>
> Hello Joel,
>
> On 1/14/26 05:34, Joel Stanley wrote:
> > v2 separates out prep patches so the machine can be reviewed
> > independently. It depends on the following two series:
> >
> >   AIA: https://lore.kernel.org/qemu-devel/20260109133125.397364-1-joel@jms.id.au
> >   Boot: https://lore.kernel.org/qemu-devel/20260109131657.396794-1-joel@jms.id.au
> >
> > Original cover letter:
> >
> > Introducing Tenstorrent Atlantis!
> >
> >   The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
>
>
> What kind of board is the "Tenstorrent Atlantis platform" ? Is it an evb ?

An upcoming dev board with the SoC on it.

> >   and CoreLab Technology. It is based on the Atlantis SoC, which includes
>
> Why isn't the SoC modeled independently ?

What I've modelled is the soc, with the exception of the test i2c
sensors. Everything listed (aside from the i2c sensors) is inside the
SoC.

Lets say we add atlantis-evb that has atlantis-soc on it, with memory,
i2c devices, etc. What does that look like? The aspeed machines are a
bit complex to follow these days!

Cheers,

Joel

Re: [PATCH v2 0/6] hw/riscv: Add the Tenstorrent Atlantis machine

Posted by Cédric Le Goater 3 weeks, 4 days ago

On 1/14/26 12:14, Joel Stanley wrote:
> On Wed, 14 Jan 2026 at 19:36, Cédric Le Goater <clg@redhat.com> wrote:
>>
>> Hello Joel,
>>
>> On 1/14/26 05:34, Joel Stanley wrote:
>>> v2 separates out prep patches so the machine can be reviewed
>>> independently. It depends on the following two series:
>>>
>>>    AIA: https://lore.kernel.org/qemu-devel/20260109133125.397364-1-joel@jms.id.au
>>>    Boot: https://lore.kernel.org/qemu-devel/20260109131657.396794-1-joel@jms.id.au
>>>
>>> Original cover letter:
>>>
>>> Introducing Tenstorrent Atlantis!
>>>
>>>    The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
>>
>>
>> What kind of board is the "Tenstorrent Atlantis platform" ? Is it an evb ?
> 
> An upcoming dev board with the SoC on it.
> 
>>>    and CoreLab Technology. It is based on the Atlantis SoC, which includes
>>
>> Why isn't the SoC modeled independently ?
> 
> What I've modelled is the soc, with the exception of the test i2c
> sensors. Everything listed (aside from the i2c sensors) is inside the
> SoC.
> 
> Lets say we add atlantis-evb that has atlantis-soc on it, with memory,
> i2c devices, etc. What does that look like? 

Looks good to me.

> The aspeed machines are a bit complex to follow these days!

Aspeed machines have been around for a decade. Ten years already !

Tenstorrent machines should be similar in 2036. Hopefully sooner.

Thanks,

C.