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It is based on the Atlantis SoC, which includes the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology. The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant RISC-V CPU. This adds the machine containing serial console, interrupt controllers and device tree support. qemu-system-riscv64 -M tt-atlantis -m 512M \ -kernel Image -initrd rootfs.cpio -nographic Signed-off-by: Joel Stanley Co-Developed-by: Nicholas Piggin --- MAINTAINERS | 8 + docs/system/riscv/tt_atlantis.rst | 38 ++ docs/system/target-riscv.rst | 1 + include/hw/riscv/tt_atlantis.h | 79 ++++ hw/riscv/tt_atlantis.c | 641 ++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 16 + hw/riscv/meson.build | 1 + 7 files changed, 784 insertions(+) create mode 100644 docs/system/riscv/tt_atlantis.rst create mode 100644 include/hw/riscv/tt_atlantis.h create mode 100644 hw/riscv/tt_atlantis.c diff --git a/MAINTAINERS b/MAINTAINERS index b5a918426473..0acaf0a3f411 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1725,6 +1725,14 @@ F: hw/*/*sifive*.c F: include/hw/*/*sifive*.h F: tests/functional/test_riscv64_sifive_u.py =20 +Tenstorrent Machines +M: Joel Stanley +L: qemu-riscv@nongnu.org +S: Supported +F: docs/system/riscv/tt_*.rst +F: hw/riscv/tt_*.c +F: include/hw/riscv/tt_*.h + AMD Microblaze-V Generic Board M: Sai Pavan Boddu S: Maintained diff --git a/docs/system/riscv/tt_atlantis.rst b/docs/system/riscv/tt_atlan= tis.rst new file mode 100644 index 000000000000..640cabf7b046 --- /dev/null +++ b/docs/system/riscv/tt_atlantis.rst @@ -0,0 +1,38 @@ +Tenstorrent Atlantis (``tt-atlantis``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The Tenstorrent Atlantis platform is a collaboration between Tenstorrent +and CoreLab Technology. It is based on the Atlantis SoC, which includes +the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology. + +The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant +RISC-V CPU. + +Features +-------- + +* 8-core Ascalon-X CPU Cluster +* Dual x32 LPDDR5 @ 6400 MT/s +* RISC-V compliant Advanced Interrupt Architecture +* PCIe Gen4 +* RISC-V compliant IOMMU +* GPU and Video subsystem +* 2x USB3.1 & 2x USB2.0 +* 2x 1GbE Ethernet +* 2x eMMC5.1/SDIO3.0 storage +* Extensive connectivity (SPI, I2C, UART, GPIO, CANFD) + +Note: the QEMU tt-atlantis machine does not model the platform +exactly or all devices, but it is undergoing improvement. + +Supported software +------------------ + +The Tenstorrent Ascalon CPUs avoid proprietary or non-standard +extensions, so compatibility with existing software is generally +good. The QEMU tt-atlantis machine works with upstream OpenSBI +and Linux with default configurations. + +The development board hardware will require some implementation +specific setup in firmware which is being developed and may +become a requirement or option for the tt-atlantis machine. diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 3ad5d1ddafbb..a8e6b3342186 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -71,6 +71,7 @@ undocumented; you can get a complete list by running riscv/mips riscv/shakti-c riscv/sifive_u + riscv/tt_atlantis riscv/virt riscv/xiangshan-kunminghu =20 diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h new file mode 100644 index 000000000000..6b0777b42c32 --- /dev/null +++ b/include/hw/riscv/tt_atlantis.h @@ -0,0 +1,79 @@ +/* + * Tenstorrent Atlantis RISC-V System on Chip + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright 2025 Tenstorrent, Joel Stanley + */ + +#ifndef HW_RISCV_TT_ATLANTIS_H +#define HW_RISCV_TT_ATLANTIS_H + +#include "hw/core/boards.h" +#include "hw/core/sysbus.h" +#include "hw/intc/riscv_imsic.h" +#include "hw/riscv/riscv_hart.h" + +#define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") +OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE) + +struct TTAtlantisState { + /*< private >*/ + MachineState parent; + + /*< public >*/ + Notifier machine_done; + DeviceState *platform_bus_dev; + FWCfgState *fw_cfg; + const MemMapEntry *memmap; + + RISCVHartArrayState soc; + DeviceState *irqchip; + + int fdt_size; + int aia_guests; /* TODO: This should be hard coded once known */ +}; + +enum { + TT_ATL_SYSCON_IRQ =3D 10, + TT_ATL_UART0_IRQ =3D 38, + TT_ATL_UART1_IRQ =3D 39, + TT_ATL_UART2_IRQ =3D 40, + TT_ATL_UART3_IRQ =3D 41, + TT_ATL_UART4_IRQ =3D 42, +}; + +enum { + TT_ATL_ACLINT, + TT_ATL_BOOTROM, + TT_ATL_DDR_LO, + TT_ATL_DDR_HI, + TT_ATL_FW_CFG, + TT_ATL_I2C0, + TT_ATL_MAPLIC, + TT_ATL_MIMSIC, + TT_ATL_PCIE_ECAM0, + TT_ATL_PCIE_ECAM1, + TT_ATL_PCIE_ECAM2, + TT_ATL_PCIE_MMIO0, + TT_ATL_PCIE_PIO0, + TT_ATL_PCIE_MMIO0_32, + TT_ATL_PCIE_MMIO0_64, + TT_ATL_PCIE_MMIO1, + TT_ATL_PCIE_PIO1, + TT_ATL_PCIE_MMIO1_32, + TT_ATL_PCIE_MMIO1_64, + TT_ATL_PCIE_MMIO2, + TT_ATL_PCIE_PIO2, + TT_ATL_PCIE_MMIO2_32, + TT_ATL_PCIE_MMIO2_64, + TT_ATL_PCI_MMU_CFG, + TT_ATL_SAPLIC, + TT_ATL_SIMSIC, + TT_ATL_SYSCON, + TT_ATL_TIMER, + TT_ATL_UART0, + TT_ATL_WDT0, +}; + +#endif diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c new file mode 100644 index 000000000000..6bde78839a9f --- /dev/null +++ b/hw/riscv/tt_atlantis.c @@ -0,0 +1,641 @@ +/* + * Tenstorrent Atlantis RISC-V System on Chip + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright 2025 Tenstorrent, Joel Stanley + */ + +#include "qemu/osdep.h" +#include "qemu/cutils.h" +#include "qemu/error-report.h" +#include "qemu/guest-random.h" +#include "qemu/units.h" + +#include "hw/core/boards.h" +#include "hw/core/loader.h" +#include "hw/core/sysbus.h" + +#include "target/riscv/cpu.h" +#include "target/riscv/pmu.h" + +#include "hw/riscv/boot.h" +#include "hw/riscv/numa.h" +#include "hw/riscv/riscv_hart.h" + +#include "hw/char/serial-mm.h" +#include "hw/intc/riscv_aclint.h" +#include "hw/intc/riscv_aplic.h" +#include "hw/misc/pvpanic.h" + +#include "system/system.h" +#include "system/device_tree.h" + +#include "hw/riscv/tt_atlantis.h" + +#include "aia.h" + +#define TT_IRQCHIP_NUM_MSIS 255 +#define TT_IRQCHIP_NUM_SOURCES 128 +#define TT_IRQCHIP_NUM_PRIO_BITS 3 +#define TT_IRQCHIP_MAX_GUESTS_BITS 3 +#define TT_IRQCHIP_MAX_GUESTS ((1U << ATL_IRQCHIP_MAX_GUESTS_BITS) - 1U) + +#define IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) + +#define FDT_PCI_ADDR_CELLS 3 +#define FDT_PCI_INT_CELLS 1 +#define FDT_MAX_INT_CELLS 2 +#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_MAX_INT_CELLS) + +#define TT_ACLINT_MTIME_SIZE 0x8050 +#define TT_ACLINT_MTIME 0x0 +#define TT_ACLINT_MTIMECMP 0x8000 +#define TT_ACLINT_TIMEBASE_FREQ 1000000000 + +static const MemMapEntry tt_atlantis_memmap[] =3D { + /* Keep sorted with :'<,'>!sort -g -k 4 */ + [TT_ATL_DDR_LO] =3D { 0x00000000, 0x80000000 }, + [TT_ATL_BOOTROM] =3D { 0x80000000, 0x2000 }, + [TT_ATL_FW_CFG] =3D { 0x80002000, 0xff }, /* qemu o= nly */ + [TT_ATL_SYSCON] =3D { 0x80004000, 0x1000 }, /* qemu o= nly */ + [TT_ATL_MIMSIC] =3D { 0xa0000000, 0x200000 }, + [TT_ATL_ACLINT] =3D { 0xa2180000, 0x10000 }, + [TT_ATL_SIMSIC] =3D { 0xa4000000, 0x200000 }, + [TT_ATL_TIMER] =3D { 0xa8020000, 0x10000 }, + [TT_ATL_WDT0] =3D { 0xa8030000, 0x10000 }, + [TT_ATL_UART0] =3D { 0xb0100000, 0x10000 }, + [TT_ATL_MAPLIC] =3D { 0xcc000000, 0x4000000 }, + [TT_ATL_SAPLIC] =3D { 0xe8000000, 0x4000000 }, + [TT_ATL_DDR_HI] =3D { 0x100000000, 0x1000000000 }, + [TT_ATL_PCIE_ECAM0] =3D { 0x01110000000, 0x10000000 }, + [TT_ATL_PCIE_ECAM1] =3D { 0x01120000000, 0x10000000 }, + [TT_ATL_PCIE_ECAM2] =3D { 0x01130000000, 0x10000000 }, + [TT_ATL_PCIE_MMIO0] =3D { 0x10000000000, 0x10000000000 }, + [TT_ATL_PCIE_MMIO1] =3D { 0x20000000000, 0x10000000000 }, + [TT_ATL_PCIE_MMIO2] =3D { 0x30000000000, 0x10000000000 }, +}; + +static uint32_t next_phandle(void) +{ + static uint32_t phandle =3D 1; + return phandle++; +} + +static void create_fdt_cpus(TTAtlantisState *s, uint32_t *intc_phandles) +{ + uint32_t cpu_phandle; + void *fdt =3D MACHINE(s)->fdt; + + for (int cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { + RISCVCPU *cpu_ptr =3D &s->soc.harts[cpu]; + g_autofree char *cpu_name =3D NULL; + g_autofree char *intc_name =3D NULL; + + cpu_phandle =3D next_phandle(); + + cpu_name =3D g_strdup_printf("/cpus/cpu@%d", s->soc.hartid_base + = cpu); + qemu_fdt_add_subnode(fdt, cpu_name); + + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv57"); + + riscv_isa_write_fdt(cpu_ptr, fdt, cpu_name); + + qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cbom-block-size", + cpu_ptr->cfg.cbom_blocksize); + + qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cboz-block-size", + cpu_ptr->cfg.cboz_blocksize); + + qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cbop-block-size", + cpu_ptr->cfg.cbop_blocksize); + + qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc.hartid_base + c= pu); + qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); + qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); + + intc_phandles[cpu] =3D next_phandle(); + + intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_name); + qemu_fdt_add_subnode(fdt, intc_name); + qemu_fdt_setprop_cell(fdt, intc_name, "phandle", + intc_phandles[cpu]); + qemu_fdt_setprop_string(fdt, intc_name, "compatible", + "riscv,cpu-intc"); + qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); + } +} + +static void create_fdt_memory_node(TTAtlantisState *s, + hwaddr addr, hwaddr size) +{ + void *fdt =3D MACHINE(s)->fdt; + g_autofree char *name =3D g_strdup_printf("/memory@%"HWADDR_PRIX, addr= ); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, addr, 2, size); + qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); +} + +static void create_fdt_memory(TTAtlantisState *s) +{ + hwaddr size_lo =3D MACHINE(s)->ram_size; + hwaddr size_hi =3D 0; + + if (size_lo > s->memmap[TT_ATL_DDR_LO].size) { + size_lo =3D s->memmap[TT_ATL_DDR_LO].size; + size_hi =3D MACHINE(s)->ram_size - size_lo; + } + + create_fdt_memory_node(s, s->memmap[TT_ATL_DDR_LO].base, size_lo); + if (size_hi) { + /* + * The first part of the HI address is aliased at the LO address + * so do not include that as usable memory. Is there any way + * (or good reason) to describe that aliasing 2GB with DT? + */ + create_fdt_memory_node(s, s->memmap[TT_ATL_DDR_HI].base + size_lo, + size_hi); + } +} + +static void create_fdt_aclint(TTAtlantisState *s, uint32_t *intc_phandles) +{ + void *fdt =3D MACHINE(s)->fdt; + g_autofree char *name =3D NULL; + g_autofree uint32_t *aclint_mtimer_cells =3D NULL; + uint32_t aclint_cells_size; + hwaddr addr; + + aclint_mtimer_cells =3D g_new0(uint32_t, s->soc.num_harts * 2); + + for (int cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + aclint_mtimer_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu= ]); + aclint_mtimer_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_TIMER); + } + aclint_cells_size =3D s->soc.num_harts * sizeof(uint32_t) * 2; + + addr =3D s->memmap[TT_ATL_ACLINT].base; + + name =3D g_strdup_printf("/soc/mtimer@%"HWADDR_PRIX, addr); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "riscv,aclint-mtimer"= ); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, addr + TT_ACLINT_MTIME, + 2, 0x1000, + 2, addr + TT_ACLINT_MTIMECMP, + 2, 0x1000); + qemu_fdt_setprop(fdt, name, "interrupts-extended", + aclint_mtimer_cells, aclint_cells_size); +} + +static void create_fdt_one_imsic(void *fdt, const MemMapEntry *mem, int cp= us, + uint32_t *intc_phandles, uint32_t msi_pha= ndle, + int irq_line, uint32_t imsic_guest_bits) +{ + g_autofree char *name =3D NULL; + g_autofree uint32_t *imsic_cells =3D g_new0(uint32_t, cpus * 2); + + for (int cpu =3D 0; cpu < cpus; cpu++) { + imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(irq_line); + } + + name =3D g_strdup_printf("/soc/interrupt-controller@%"HWADDR_PRIX, mem= ->base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "riscv,imsics"); + + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 0); + qemu_fdt_setprop(fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(fdt, name, "msi-controller", NULL, 0); + qemu_fdt_setprop(fdt, name, "interrupts-extended", + imsic_cells, sizeof(uint32_t) * cpus * 2); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); + qemu_fdt_setprop_cell(fdt, name, "riscv,num-ids", TT_IRQCHIP_NUM_MSIS); + + if (imsic_guest_bits) { + qemu_fdt_setprop_cell(fdt, name, "riscv,guest-index-bits", + imsic_guest_bits); + } + qemu_fdt_setprop_cell(fdt, name, "phandle", msi_phandle); +} + +static void create_fdt_one_aplic(void *fdt, + const MemMapEntry *mem, + uint32_t msi_phandle, + uint32_t *intc_phandles, + uint32_t aplic_phandle, + uint32_t aplic_child_phandle, + int irq_line, int num_harts) +{ + g_autofree char *name =3D + g_strdup_printf("/soc/interrupt-controller@%"HWADDR_PRIX, mem->bas= e); + g_autofree uint32_t *aplic_cells =3D g_new0(uint32_t, num_harts * 2); + + for (int cpu =3D 0; cpu < num_harts; cpu++) { + aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(irq_line); + } + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(fdt, name, "#address-cells", 0); + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 2); + qemu_fdt_setprop(fdt, name, "interrupt-controller", NULL, 0); + + qemu_fdt_setprop(fdt, name, "interrupts-extended", + aplic_cells, num_harts * sizeof(uint32_t) * 2); + qemu_fdt_setprop_cell(fdt, name, "msi-parent", msi_phandle); + + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); + qemu_fdt_setprop_cell(fdt, name, "riscv,num-sources", + TT_IRQCHIP_NUM_SOURCES); + + if (aplic_child_phandle) { + qemu_fdt_setprop_cell(fdt, name, "riscv,children", + aplic_child_phandle); + qemu_fdt_setprop_cells(fdt, name, "riscv,delegation", + aplic_child_phandle, 1, TT_IRQCHIP_NUM_SOUR= CES); + } + + qemu_fdt_setprop_cell(fdt, name, "phandle", aplic_phandle); +} + +static void create_fdt_pmu(TTAtlantisState *s) +{ + g_autofree char *pmu_name =3D g_strdup_printf("/pmu"); + void *fdt =3D MACHINE(s)->fdt; + RISCVCPU hart =3D s->soc.harts[0]; + + qemu_fdt_add_subnode(fdt, pmu_name); + qemu_fdt_setprop_string(fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(fdt, hart.pmu_avail_ctrs, pmu_name); +} + +static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, + uint32_t aplic_s_phandle, + uint32_t imsic_s_phandle) +{ + MachineState *ms =3D MACHINE(s); + void *fdt =3D MACHINE(s)->fdt; + g_autofree uint32_t *intc_phandles =3D NULL; + + qemu_fdt_add_subnode(fdt, "/cpus"); + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", + TT_ACLINT_TIMEBASE_FREQ); + qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); + + intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); + + create_fdt_cpus(s, intc_phandles); + + create_fdt_memory(s); + + create_fdt_aclint(s, intc_phandles); + + /* M-level IMSIC node */ + uint32_t msi_m_phandle =3D next_phandle(); + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], ms->smp.cpus, + intc_phandles, msi_m_phandle, + IRQ_M_EXT, 0); + + /* S-level IMSIC node */ + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], ms->smp.cpus, + intc_phandles, imsic_s_phandle, + IRQ_S_EXT, imsic_num_bits(s->aia_guests + 1)); + + uint32_t aplic_m_phandle =3D next_phandle(); + + /* M-level APLIC node */ + create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC], + msi_m_phandle, intc_phandles, + aplic_m_phandle, aplic_s_phandle, + IRQ_M_EXT, s->soc.num_harts); + + /* S-level APLIC node */ + create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC], + imsic_s_phandle, intc_phandles, + aplic_s_phandle, 0, + IRQ_S_EXT, s->soc.num_harts); +} + +static void create_fdt_reset(void *fdt, const MemMapEntry *mem) +{ + uint32_t syscon_phandle =3D next_phandle(); + char *name; + + name =3D g_strdup_printf("/soc/syscon@%"HWADDR_PRIX, mem->base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); + qemu_fdt_setprop_cell(fdt, name, "phandle", syscon_phandle); + g_free(name); + + name =3D g_strdup_printf("/poweroff"); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); + qemu_fdt_setprop_cell(fdt, name, "regmap", syscon_phandle); + qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(fdt, name, "value", PVPANIC_SHUTDOWN); + g_free(name); +} + +static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, + int irqchip_phandle) +{ + g_autofree char *name =3D g_strdup_printf("/soc/serial@%"HWADDR_PRIX, + mem->base); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); + qemu_fdt_setprop_cell(fdt, name, "reg-shift", 2); + qemu_fdt_setprop_cell(fdt, name, "reg-io-width", 4); + qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle); + qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4); + + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); + qemu_fdt_setprop_string(fdt, "/aliases", "serial0", name); +} + +static void create_fdt_fw_cfg(void *fdt, const MemMapEntry *mem) +{ + g_autofree char *name =3D g_strdup_printf("/fw-cfg@%"HWADDR_PRIX, mem-= >base); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "qemu,fw-cfg-mmio"); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); + qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); +} + +static void finalize_fdt(TTAtlantisState *s) +{ + uint32_t aplic_s_phandle =3D next_phandle(); + uint32_t imsic_s_phandle =3D next_phandle(); + void *fdt =3D MACHINE(s)->fdt; + + create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle); + + /* + * We want to do this, but the Linux aplic driver was broken before v6= .16 + * + * qemu_fdt_setprop_cell(MACHINE(s)->fdt, "/soc", "interrupt-parent", + * aplic_s_phandle); + */ + + create_fdt_reset(fdt, &s->memmap[TT_ATL_SYSCON]); + + create_fdt_uart(fdt, &s->memmap[TT_ATL_UART0], TT_ATL_UART0_IRQ, + aplic_s_phandle); +} + +static void create_fdt(TTAtlantisState *s) +{ + MachineState *ms =3D MACHINE(s); + uint8_t rng_seed[32]; + g_autofree char *name =3D NULL; + void *fdt; + + fdt =3D create_device_tree(&s->fdt_size); + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + ms->fdt =3D fdt; + + qemu_fdt_setprop_string(fdt, "/", "model", + "Tenstorrent Atlantis RISC-V Machine"); + qemu_fdt_setprop_string(fdt, "/", "compatible", "tenstorrent,atlantis"= ); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + + qemu_fdt_add_subnode(fdt, "/soc"); + qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); + qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + + qemu_fdt_add_subnode(fdt, "/chosen"); + + /* Pass seed to RNG */ + qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed= )); + + qemu_fdt_add_subnode(fdt, "/aliases"); + + create_fdt_fw_cfg(fdt, &s->memmap[TT_ATL_SYSCON]); + create_fdt_pmu(s); +} + +static DeviceState *create_reboot_device(const MemMapEntry *mem) +{ + DeviceState *dev =3D qdev_new(TYPE_PVPANIC_MMIO_DEVICE); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + qdev_prop_set_uint32(dev, "events", PVPANIC_SHUTDOWN | PVPANIC_PANICKE= D); + + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, mem->base); + + return dev; +} + +static FWCfgState *create_fw_cfg(const MemMapEntry *mem, int num_cpus) +{ + FWCfgState *fw_cfg; + hwaddr base =3D mem->base; + + fw_cfg =3D fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, + &address_space_memory); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, num_cpus); + + return fw_cfg; +} + +static void tt_atlantis_machine_done(Notifier *notifier, void *data) +{ + TTAtlantisState *s =3D container_of(notifier, TTAtlantisState, machine= _done); + MachineState *machine =3D MACHINE(s); + hwaddr start_addr =3D s->memmap[TT_ATL_DDR_LO].base; + hwaddr mem_size; + target_ulong firmware_end_addr, kernel_start_addr; + const char *firmware_name =3D riscv_default_firmware_name(&s->soc); + uint64_t fdt_load_addr; + uint64_t kernel_entry; + RISCVBootInfo boot_info; + + /* + * An user provided dtb must include everything, including + * dynamic sysbus devices. Our FDT needs to be finalized. + */ + if (machine->dtb =3D=3D NULL) { + finalize_fdt(s); + } + + mem_size =3D machine->ram_size; + if (mem_size > s->memmap[TT_ATL_DDR_LO].size) { + mem_size =3D s->memmap[TT_ATL_DDR_LO].size; + } + riscv_boot_info_init_discontig_mem(&boot_info, &s->soc, + s->memmap[TT_ATL_DDR_LO].base, + mem_size); + + firmware_end_addr =3D riscv_find_and_load_firmware(machine, &boot_info, + firmware_name, + &start_addr, NULL); + + if (machine->kernel_filename) { + kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, + firmware_end_addr= ); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, + true, NULL); + kernel_entry =3D boot_info.image_low_addr; + } else { + kernel_entry =3D 0; + } + + fdt_load_addr =3D riscv_compute_fdt_addr(s->memmap[TT_ATL_DDR_LO].base, + s->memmap[TT_ATL_DDR_LO].size, + machine, &boot_info); + riscv_load_fdt(fdt_load_addr, machine->fdt); + + /* load the reset vector */ + riscv_setup_rom_reset_vec(machine, &s->soc, start_addr, + s->memmap[TT_ATL_BOOTROM].base, + s->memmap[TT_ATL_BOOTROM].size, + kernel_entry, + fdt_load_addr); + +} + +static void tt_atlantis_machine_init(MachineState *machine) +{ + TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); + + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); + MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); + MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); + ram_addr_t lo_ram_size, hi_ram_size; + int hart_count =3D machine->smp.cpus; + int base_hartid =3D 0; + + s->memmap =3D tt_atlantis_memmap; + + object_initialize_child(OBJECT(machine), "soc", &s->soc, + TYPE_RISCV_HART_ARRAY); + object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, + &error_abort); + object_property_set_int(OBJECT(&s->soc), "hartid-base", base_hartid, + &error_abort); + object_property_set_int(OBJECT(&s->soc), "num-harts", hart_count, + &error_abort); + object_property_set_int(OBJECT(&s->soc), "resetvec", + s->memmap[TT_ATL_BOOTROM].base, + &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); + + s->irqchip =3D riscv_create_aia(true, s->aia_guests, TT_IRQCHIP_NUM_SO= URCES, + &s->memmap[TT_ATL_MAPLIC], + &s->memmap[TT_ATL_SAPLIC], + &s->memmap[TT_ATL_MIMSIC], + &s->memmap[TT_ATL_SIMSIC], + 0, base_hartid, hart_count); + + riscv_aclint_mtimer_create(s->memmap[TT_ATL_ACLINT].base, + TT_ACLINT_MTIME_SIZE, + base_hartid, hart_count, + TT_ACLINT_MTIMECMP, + TT_ACLINT_MTIME, + TT_ACLINT_TIMEBASE_FREQ, true); + + /* DDR */ + + /* The high address covers all of RAM, the low address just the first = 2GB */ + lo_ram_size =3D s->memmap[TT_ATL_DDR_LO].size; + hi_ram_size =3D s->memmap[TT_ATL_DDR_HI].size; + if (machine->ram_size > hi_ram_size) { + char *sz =3D size_to_str(hi_ram_size); + error_report("RAM size is too large, maximum is %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + + memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", machine->= ram, + 0, lo_ram_size); + memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", machine-= >ram, + 0, hi_ram_size); + memory_region_add_subregion(system_memory, + s->memmap[TT_ATL_DDR_LO].base, ram_lo); + memory_region_add_subregion(system_memory, + s->memmap[TT_ATL_DDR_HI].base, ram_hi); + + /* Boot ROM */ + memory_region_init_rom(bootrom, NULL, "tt-atlantis.bootrom", + s->memmap[TT_ATL_BOOTROM].size, &error_fatal); + memory_region_add_subregion(system_memory, s->memmap[TT_ATL_BOOTROM].b= ase, + bootrom); + + /* + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the + * device tree cannot be altered and we get FDT_ERR_NOSPACE. + */ + s->fw_cfg =3D create_fw_cfg(&s->memmap[TT_ATL_FW_CFG], machine->smp.cp= us); + rom_set_fw(s->fw_cfg); + + /* Reboot and exit */ + create_reboot_device(&s->memmap[TT_ATL_SYSCON]); + + /* UART */ + serial_mm_init(system_memory, s->memmap[TT_ATL_UART0].base, 2, + qdev_get_gpio_in(s->irqchip, TT_ATL_UART0_IRQ), + 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); + + /* Load or create device tree */ + if (machine->dtb) { + machine->fdt =3D load_device_tree(machine->dtb, &s->fdt_size); + if (!machine->fdt) { + error_report("load_device_tree() failed"); + exit(1); + } + } else { + create_fdt(s); + } + + s->machine_done.notify =3D tt_atlantis_machine_done; + qemu_add_machine_init_done_notifier(&s->machine_done); +} + +static void tt_atlantis_machine_class_init(ObjectClass *oc, const void *da= ta) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Tenstorrent Atlantis RISC-V SoC"; + mc->init =3D tt_atlantis_machine_init; + mc->max_cpus =3D 8; + mc->default_cpus =3D 8; + mc->default_ram_size =3D 2 * GiB; + mc->default_cpu_type =3D TYPE_RISCV_CPU_TT_ASCALON; + mc->block_default_type =3D IF_VIRTIO; + mc->no_cdrom =3D 1; + mc->default_ram_id =3D "tt_atlantis.ram"; +} + +static const TypeInfo tt_atlantis_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("tt-atlantis"), + .parent =3D TYPE_MACHINE, + .class_init =3D tt_atlantis_machine_class_init, + .instance_size =3D sizeof(TTAtlantisState), +}; + +static void tt_atlantis_machine_init_register_types(void) +{ + type_register_static(&tt_atlantis_machine_typeinfo); +} + +type_init(tt_atlantis_machine_init_register_types) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 0222c93f878b..89e3661726a1 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -120,6 +120,22 @@ config SPIKE select RISCV_ACLINT select SIFIVE_PLIC =20 +config TENSTORRENT + bool + default y + depends on RISCV64 + imply PCI_DEVICES + imply TEST_DEVICES + select DEVICE_TREE + select RISCV_NUMA + select PVPANIC_MMIO + select SERIAL_MM + select RISCV_ACLINT + select RISCV_APLIC + select RISCV_IMSIC + select FW_CFG_DMA + select PLATFORM_BUS + config XIANGSHAN_KUNMINGHU bool default y diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index e53c180d0d10..026e79591f4b 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -9,6 +9,7 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifiv= e_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) +riscv_ss.add(when: 'CONFIG_TENSTORRENT', if_true: files('tt_atlantis.c')) riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( 'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-h= pm.c')) --=20 2.47.3 From nobody Mon Feb 9 16:35:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768365362003354.36251613572404; Tue, 13 Jan 2026 20:36:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vfsbK-00067m-PF; Tue, 13 Jan 2026 23:35:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vfsbH-00066O-13 for qemu-devel@nongnu.org; Tue, 13 Jan 2026 23:35:19 -0500 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vfsbE-0008IN-PG for qemu-devel@nongnu.org; Tue, 13 Jan 2026 23:35:18 -0500 Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-c0bccb8037eso3517146a12.1 for ; Tue, 13 Jan 2026 20:35:16 -0800 (PST) Received: from donnager-debian.. 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Tue, 13 Jan 2026 20:35:15 -0800 (PST) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza , Sunil V L , qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nicholas Piggin , Weiwei Li , Liu Zhiwei , Michael Ellerman , Joel Stanley , Nick Piggin , Anirudh Srinivasan , qemu-riscv@nongnu.org Subject: [PATCH v2 2/6] hw/riscv/atlantis: Add PCIe controller Date: Wed, 14 Jan 2026 15:04:24 +1030 Message-ID: <20260114043433.1056021-3-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260114043433.1056021-1-joel@jms.id.au> References: <20260114043433.1056021-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=joel.stan@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1768365365114158500 Content-Type: text/plain; charset="utf-8" From: Nicholas Piggin tt-atlantis is likely to use a generic ECAM compatible PCIe memory map, so gpex is not far off the OS programming model Signed-off-by: Nicholas Piggin Signed-off-by: Joel Stanley --- include/hw/riscv/tt_atlantis.h | 2 + hw/riscv/tt_atlantis.c | 218 +++++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 2 + 3 files changed, 222 insertions(+) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 6b0777b42c32..10b06894aeca 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -29,6 +29,7 @@ struct TTAtlantisState { =20 RISCVHartArrayState soc; DeviceState *irqchip; + GPEXHost gpex_host; =20 int fdt_size; int aia_guests; /* TODO: This should be hard coded once known */ @@ -41,6 +42,7 @@ enum { TT_ATL_UART2_IRQ =3D 40, TT_ATL_UART3_IRQ =3D 41, TT_ATL_UART4_IRQ =3D 42, + TT_ATL_PCIE0_INTA_IRQ =3D 96, }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 6bde78839a9f..fa6e4f42a12d 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -27,6 +27,7 @@ #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" #include "hw/misc/pvpanic.h" +#include "hw/pci-host/gpex.h" =20 #include "system/system.h" #include "system/device_tree.h" @@ -73,6 +74,9 @@ static const MemMapEntry tt_atlantis_memmap[] =3D { [TT_ATL_PCIE_ECAM1] =3D { 0x01120000000, 0x10000000 }, [TT_ATL_PCIE_ECAM2] =3D { 0x01130000000, 0x10000000 }, [TT_ATL_PCIE_MMIO0] =3D { 0x10000000000, 0x10000000000 }, + [TT_ATL_PCIE_PIO0] =3D { 0x10000000000, 0x10000 }, /* qemu o= nly */ + [TT_ATL_PCIE_MMIO0_32] =3D { 0x10004000000, 0x4000000 }, /* qemu o= nly */ + [TT_ATL_PCIE_MMIO0_64] =3D { 0x10010000000, 0x0fff0000000 }, /* qemu o= nly */ [TT_ATL_PCIE_MMIO1] =3D { 0x20000000000, 0x10000000000 }, [TT_ATL_PCIE_MMIO2] =3D { 0x30000000000, 0x10000000000 }, }; @@ -83,6 +87,59 @@ static uint32_t next_phandle(void) return phandle++; } =20 +static void create_pcie_irq_map(void *fdt, char *nodename, int legacy_irq, + uint32_t irqchip_phandle) +{ + int pin, dev; + uint32_t irq_map_stride =3D 0; + uint32_t full_irq_map[PCI_NUM_PINS * PCI_NUM_PINS * + FDT_MAX_INT_MAP_WIDTH] =3D {}; + uint32_t *irq_map =3D full_irq_map; + + /* + * This code creates a standard swizzle of interrupts such that + * each device's first interrupt is based on it's PCI_SLOT number. + * (See pci_swizzle_map_irq_fn()) + * + * We only need one entry per interrupt in the table (not one per + * possible slot) seeing the interrupt-map-mask will allow the table + * to wrap to any number of devices. + */ + for (dev =3D 0; dev < PCI_NUM_PINS; dev++) { + int devfn =3D dev * 0x8; + + for (pin =3D 0; pin < PCI_NUM_PINS; pin++) { + int irq_nr =3D legacy_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM= _PINS); + int i =3D 0; + + /* Fill PCI address cells */ + irq_map[i] =3D cpu_to_be32(devfn << 8); + i +=3D FDT_PCI_ADDR_CELLS; + + /* Fill PCI Interrupt cells */ + irq_map[i] =3D cpu_to_be32(pin + 1); + i +=3D FDT_PCI_INT_CELLS; + + /* Fill interrupt controller phandle and cells */ + irq_map[i++] =3D cpu_to_be32(irqchip_phandle); + irq_map[i++] =3D cpu_to_be32(irq_nr); + irq_map[i++] =3D cpu_to_be32(0x4); + + if (!irq_map_stride) { + irq_map_stride =3D i; + } + irq_map +=3D irq_map_stride; + } + } + + qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, + PCI_NUM_PINS * PCI_NUM_PINS * + irq_map_stride * sizeof(uint32_t)); + + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", + 0x1800, 0, 0, 0x7); +} + static void create_fdt_cpus(TTAtlantisState *s, uint32_t *intc_phandles) { uint32_t cpu_phandle; @@ -323,6 +380,54 @@ static void create_fdt_cpu(TTAtlantisState *s, const M= emMapEntry *memmap, IRQ_S_EXT, s->soc.num_harts); } =20 +static void create_fdt_pcie(void *fdt, + const MemMapEntry *mem_ecam, + const MemMapEntry *mem_pio, + const MemMapEntry *mem_mmio32, + const MemMapEntry *mem_mmio64, + int legacy_irq, + uint32_t aplic_s_phandle, + uint32_t imsic_s_phandle) +{ + g_autofree char *name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIX, + mem_ecam->base); + + qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS= ); + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generi= c"); + qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, + mem_ecam->size / PCIE_MMCFG_SIZE_MIN - 1); + qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cell(fdt, name, "msi-parent", imsic_s_phandle); + + qemu_fdt_setprop_sized_cells(fdt, name, "reg", + 2, mem_ecam->base, + 2, mem_ecam->size); + if (!(mem_mmio32->base & 0xffffffffUL)) { + /* XXX: this is a silly hack because it would collide with PIO */ + error_report("mmio32 base must not be 0 mod 2^32"); + exit(1); + } + uint32_t flags =3D FDT_PCI_RANGE_MMIO_64BIT | FDT_PCI_RANGE_PREFETCHAB= LE; + qemu_fdt_setprop_sized_cells(fdt, name, "ranges", + 1, FDT_PCI_RANGE_IOPORT, + 2, 0x0, + 2, mem_pio->base, + 2, mem_pio->size, + 1, FDT_PCI_RANGE_MMIO, + 2, (mem_mmio32->base & 0xffffffffUL), + 2, mem_mmio32->base, + 2, mem_mmio32->size, + 1, flags, + 2, mem_mmio64->base, + 2, mem_mmio64->base, + 2, mem_mmio64->size); + + create_pcie_irq_map(fdt, name, legacy_irq, aplic_s_phandle); +} + static void create_fdt_reset(void *fdt, const MemMapEntry *mem) { uint32_t syscon_phandle =3D next_phandle(); @@ -388,6 +493,14 @@ static void finalize_fdt(TTAtlantisState *s) * aplic_s_phandle); */ =20 + create_fdt_pcie(fdt, + &s->memmap[TT_ATL_PCIE_ECAM0], + &s->memmap[TT_ATL_PCIE_PIO0], + &s->memmap[TT_ATL_PCIE_MMIO0_32], + &s->memmap[TT_ATL_PCIE_MMIO0_64], + TT_ATL_PCIE0_INTA_IRQ, + aplic_s_phandle, imsic_s_phandle); + create_fdt_reset(fdt, &s->memmap[TT_ATL_SYSCON]); =20 create_fdt_uart(fdt, &s->memmap[TT_ATL_UART0], TT_ATL_UART0_IRQ, @@ -420,6 +533,20 @@ static void create_fdt(TTAtlantisState *s) qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); =20 + /* + * The "/soc/pci@..." node is needed for PCIE hotplugs + * that might happen before finalize_fdt(). + */ + name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIX, + s->memmap[TT_ATL_PCIE_ECAM0].base); + qemu_fdt_add_subnode(fdt, name); + name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIX, + s->memmap[TT_ATL_PCIE_ECAM1].base); + qemu_fdt_add_subnode(fdt, name); + name =3D g_strdup_printf("/soc/pci@%"HWADDR_PRIX, + s->memmap[TT_ATL_PCIE_ECAM2].base); + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_add_subnode(fdt, "/chosen"); =20 /* Pass seed to RNG */ @@ -432,6 +559,93 @@ static void create_fdt(TTAtlantisState *s) create_fdt_pmu(s); } =20 +static void gpex_pcie_init_one(TTAtlantisState *s, GPEXHost *gpex_host, + MemoryRegion *mr, + const MemMapEntry *mem_ecam, + const MemMapEntry *mem_pio, + const MemMapEntry *mem_mmio32, + const MemMapEntry *mem_mmio64, + int legacy_irq) +{ + DeviceState *dev; + Object *obj; + MemoryRegion *ecam_alias, *ecam_reg; + MemoryRegion *mmio32_alias, *mmio64_alias, *mmio_reg; + hwaddr ecam_base =3D mem_ecam->base; + hwaddr ecam_size =3D mem_ecam->size; + hwaddr pio_base =3D mem_pio->base; + hwaddr pio_size =3D mem_pio->size; + hwaddr mmio32_base =3D mem_mmio32->base; + hwaddr mmio32_size =3D mem_mmio32->size; + hwaddr mmio64_base =3D mem_mmio64->base; + hwaddr mmio64_size =3D mem_mmio64->size; + qemu_irq irq; + char name[16]; + int i; + + snprintf(name, sizeof(name), "pcie"); + object_initialize_child(OBJECT(s), name, gpex_host, TYPE_GPEX_HOST); + dev =3D DEVICE(gpex_host); + obj =3D OBJECT(dev); + + object_property_set_uint(obj, PCI_HOST_ECAM_BASE, ecam_base, &error_ab= ort); + object_property_set_int(obj, PCI_HOST_ECAM_SIZE, ecam_size, &error_abo= rt); + object_property_set_uint(obj, PCI_HOST_BELOW_4G_MMIO_BASE, mmio32_base, + &error_abort); + object_property_set_int(obj, PCI_HOST_BELOW_4G_MMIO_SIZE, mmio32_size, + &error_abort); + object_property_set_uint(obj, PCI_HOST_ABOVE_4G_MMIO_BASE, mmio64_base, + &error_abort); + object_property_set_int(obj, PCI_HOST_ABOVE_4G_MMIO_SIZE, mmio64_size, + &error_abort); + object_property_set_uint(obj, PCI_HOST_PIO_BASE, pio_base, &error_abor= t); + object_property_set_int(obj, PCI_HOST_PIO_SIZE, pio_size, &error_abort= ); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + ecam_alias =3D g_new0(MemoryRegion, 1); + ecam_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + snprintf(name, sizeof(name), "pcie.ecam"); + memory_region_init_alias(ecam_alias, obj, name, + ecam_reg, 0, ecam_size); + memory_region_add_subregion(mr, ecam_base, ecam_alias); + + mmio_reg =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + + mmio32_alias =3D g_new0(MemoryRegion, 1); + snprintf(name, sizeof(name), "pcie.mmio32"); + memory_region_init_alias(mmio32_alias, obj, name, + mmio_reg, mmio32_base & 0xffffffffUL, mmio32_= size); + memory_region_add_subregion(mr, mmio32_base, mmio32_alias); + + mmio64_alias =3D g_new0(MemoryRegion, 1); + snprintf(name, sizeof(name), "pcie.mmio64"); + memory_region_init_alias(mmio64_alias, obj, name, + mmio_reg, mmio64_base, mmio64_size); + memory_region_add_subregion(mr, mmio64_base, mmio64_alias); + + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); + + for (i =3D 0; i < PCI_NUM_PINS; i++) { + irq =3D qdev_get_gpio_in(s->irqchip, legacy_irq + i); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); + gpex_set_irq_num(GPEX_HOST(dev), i, legacy_irq + i); + } + + gpex_host->gpex_cfg.bus =3D PCI_HOST_BRIDGE(dev)->bus; +} + +static void gpex_pcie_init(TTAtlantisState *s, MemoryRegion *mr) +{ + gpex_pcie_init_one(s, &s->gpex_host, mr, + &s->memmap[TT_ATL_PCIE_ECAM0], + &s->memmap[TT_ATL_PCIE_PIO0], + &s->memmap[TT_ATL_PCIE_MMIO0_32], + &s->memmap[TT_ATL_PCIE_MMIO0_64], + TT_ATL_PCIE0_INTA_IRQ); +} + static DeviceState *create_reboot_device(const MemMapEntry *mem) { DeviceState *dev =3D qdev_new(TYPE_PVPANIC_MMIO_DEVICE); @@ -588,6 +802,9 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) s->fw_cfg =3D create_fw_cfg(&s->memmap[TT_ATL_FW_CFG], machine->smp.cp= us); rom_set_fw(s->fw_cfg); =20 + /* PCIe */ + gpex_pcie_init(s, system_memory); + /* Reboot and exit */ create_reboot_device(&s->memmap[TT_ATL_SYSCON]); =20 @@ -623,6 +840,7 @@ static void tt_atlantis_machine_class_init(ObjectClass = *oc, const void *data) mc->default_cpu_type =3D TYPE_RISCV_CPU_TT_ASCALON; mc->block_default_type =3D IF_VIRTIO; mc->no_cdrom =3D 1; + mc->pci_allow_0_address =3D true; mc->default_ram_id =3D "tt_atlantis.ram"; } =20 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 89e3661726a1..5317eccd06e7 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -129,6 +129,8 @@ config TENSTORRENT select DEVICE_TREE select RISCV_NUMA select PVPANIC_MMIO + select PCI + select PCI_EXPRESS_GENERIC_BRIDGE select SERIAL_MM select RISCV_ACLINT select RISCV_APLIC --=20 2.47.3 From nobody Mon Feb 9 16:35:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768365405601590.1853424777998; Tue, 13 Jan 2026 20:36:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vfsbV-00068o-3E; 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Signed-off-by: Nicholas Piggin Signed-off-by: Joel Stanley --- MAINTAINERS | 1 + tests/functional/riscv64/meson.build | 1 + tests/functional/riscv64/test_opensbi.py | 4 ++ tests/functional/riscv64/test_tt_atlantis.py | 68 ++++++++++++++++++++ 4 files changed, 74 insertions(+) create mode 100755 tests/functional/riscv64/test_tt_atlantis.py diff --git a/MAINTAINERS b/MAINTAINERS index 0acaf0a3f411..91f71077c40a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1732,6 +1732,7 @@ S: Supported F: docs/system/riscv/tt_*.rst F: hw/riscv/tt_*.c F: include/hw/riscv/tt_*.h +F: tests/functional/test_riscv64_tt_*.py =20 AMD Microblaze-V Generic Board M: Sai Pavan Boddu diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv6= 4/meson.build index b996c89d7df9..c4456fabd757 100644 --- a/tests/functional/riscv64/meson.build +++ b/tests/functional/riscv64/meson.build @@ -13,5 +13,6 @@ tests_riscv64_system_quick =3D [ tests_riscv64_system_thorough =3D [ 'boston', 'sifive_u', + 'tt_atlantis', 'tuxrun', ] diff --git a/tests/functional/riscv64/test_opensbi.py b/tests/functional/ri= scv64/test_opensbi.py index d077e40f4278..0f8beb7e7a8c 100755 --- a/tests/functional/riscv64/test_opensbi.py +++ b/tests/functional/riscv64/test_opensbi.py @@ -28,6 +28,10 @@ def test_riscv_sifive_u(self): self.set_machine('sifive_u') self.boot_opensbi() =20 + def test_riscv_tt_atlantis(self): + self.set_machine('tt-atlantis') + self.boot_opensbi() + def test_riscv_virt(self): self.set_machine('virt') self.boot_opensbi() diff --git a/tests/functional/riscv64/test_tt_atlantis.py b/tests/functiona= l/riscv64/test_tt_atlantis.py new file mode 100755 index 000000000000..fb6943509c28 --- /dev/null +++ b/tests/functional/riscv64/test_tt_atlantis.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python3 +# +# Functional test that boots a Linux kernel on a Tenstorrent Atlantis mach= ine +# and checks the console +# +# Copyright (c) Linaro Ltd. +# +# Author: +# Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os + +from qemu_test import Asset, LinuxKernelTest +from qemu_test import skipIfMissingCommands + + +class TTAtlantis(LinuxKernelTest): + + ASSET_KERNEL =3D Asset( + 'https://storage.tuxboot.com/kernels/6.11.9/riscv64/Image', + '174f8bb87f08961e54fa3fcd954a8e31f4645f6d6af4dd43983d5e9841490fb0') + ASSET_ROOTFS =3D Asset( + ('https://github.com/groeck/linux-build-test/raw/' + '9819da19e6eef291686fdd7b029ea00e764dc62f/rootfs/riscv64/' + 'rootfs.ext2.gz'), + 'b6ed95610310b7956f9bf20c4c9c0c05fea647900df441da9dfe767d24e8b28b') + + def do_test_riscv64_tt_atlantis(self, connect_disk): + self.set_machine('tt-atlantis') + kernel_path =3D self.ASSET_KERNEL.fetch() + rootfs_path =3D self.uncompress(self.ASSET_ROOTFS) + + self.vm.set_console() + kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE + + 'earlycon=3Dsbi ' + 'root=3D/dev/vda ') + + if connect_disk: + kernel_command_line +=3D 'root=3D/dev/vda panic=3D-1 noreboot = rootwait ' + self.vm.add_args('-device', + 'virtio-blk,drive=3Ddrive0,serial=3D0x1234,bu= s=3Dpcie.0') + self.vm.add_args('-drive', + f'file=3D{rootfs_path},if=3Dnone,id=3Ddrive0,= format=3Draw') + pattern =3D 'Boot successful.' + else: + kernel_command_line +=3D 'panic=3D0 noreboot ' + pattern =3D 'Cannot open root device' + + self.vm.add_args('-kernel', kernel_path, + '-append', kernel_command_line, + '-no-reboot') + + self.vm.launch() + self.wait_for_console_pattern(pattern) + + os.remove(rootfs_path) + + def test_riscv64_tt_atlantis(self): + self.do_test_riscv64_tt_atlantis(False) + + def test_riscv64_tt_atlantis_disk(self): + self.do_test_riscv64_tt_atlantis(True) + + +if __name__ =3D=3D '__main__': + LinuxKernelTest.main() --=20 2.47.3 From nobody Mon Feb 9 16:35:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768365396443813.4137219076779; Tue, 13 Jan 2026 20:36:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vfsbX-0006AJ-Qk; Tue, 13 Jan 2026 23:35:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vfsbR-00068R-7K for qemu-devel@nongnu.org; Tue, 13 Jan 2026 23:35:29 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vfsbP-0008Jk-Iu for qemu-devel@nongnu.org; Tue, 13 Jan 2026 23:35:28 -0500 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-c2af7d09533so5312082a12.1 for ; Tue, 13 Jan 2026 20:35:26 -0800 (PST) Received: from donnager-debian.. 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Signed-off-by: Joel Stanley --- v2: - Correct count from 4 to 5 - Fix headers location --- include/hw/riscv/tt_atlantis.h | 13 ++++++++++++ hw/riscv/tt_atlantis.c | 39 ++++++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 1 + 3 files changed, 53 insertions(+) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 10b06894aeca..1b4f61c95184 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -11,12 +11,15 @@ =20 #include "hw/core/boards.h" #include "hw/core/sysbus.h" +#include "hw/i2c/designware_i2c.h" #include "hw/intc/riscv_imsic.h" #include "hw/riscv/riscv_hart.h" =20 #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE) =20 +#define TT_ATL_NUM_I2C 5 + struct TTAtlantisState { /*< private >*/ MachineState parent; @@ -30,6 +33,7 @@ struct TTAtlantisState { RISCVHartArrayState soc; DeviceState *irqchip; GPEXHost gpex_host; + DesignWareI2CState i2c[TT_ATL_NUM_I2C]; =20 int fdt_size; int aia_guests; /* TODO: This should be hard coded once known */ @@ -37,6 +41,11 @@ struct TTAtlantisState { =20 enum { TT_ATL_SYSCON_IRQ =3D 10, + TT_ATL_I2C0_IRQ =3D 33, + TT_ATL_I2C1_IRQ =3D 34, + TT_ATL_I2C2_IRQ =3D 35, + TT_ATL_I2C3_IRQ =3D 36, + TT_ATL_I2C4_IRQ =3D 37, TT_ATL_UART0_IRQ =3D 38, TT_ATL_UART1_IRQ =3D 39, TT_ATL_UART2_IRQ =3D 40, @@ -52,6 +61,10 @@ enum { TT_ATL_DDR_HI, TT_ATL_FW_CFG, TT_ATL_I2C0, + TT_ATL_I2C1, + TT_ATL_I2C2, + TT_ATL_I2C3, + TT_ATL_I2C4, TT_ATL_MAPLIC, TT_ATL_MIMSIC, TT_ATL_PCIE_ECAM0, diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index fa6e4f42a12d..2d0add278c20 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -67,6 +67,11 @@ static const MemMapEntry tt_atlantis_memmap[] =3D { [TT_ATL_TIMER] =3D { 0xa8020000, 0x10000 }, [TT_ATL_WDT0] =3D { 0xa8030000, 0x10000 }, [TT_ATL_UART0] =3D { 0xb0100000, 0x10000 }, + [TT_ATL_I2C0] =3D { 0xb0400000, 0x10000 }, + [TT_ATL_I2C1] =3D { 0xb0500000, 0x10000 }, + [TT_ATL_I2C2] =3D { 0xb0600000, 0x10000 }, + [TT_ATL_I2C3] =3D { 0xb0700000, 0x10000 }, + [TT_ATL_I2C4] =3D { 0xb0800000, 0x10000 }, [TT_ATL_MAPLIC] =3D { 0xcc000000, 0x4000000 }, [TT_ATL_SAPLIC] =3D { 0xe8000000, 0x4000000 }, [TT_ATL_DDR_HI] =3D { 0x100000000, 0x1000000000 }, @@ -478,6 +483,20 @@ static void create_fdt_fw_cfg(void *fdt, const MemMapE= ntry *mem) qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); } =20 +static void create_fdt_i2c(void *fdt, const MemMapEntry *mem, uint32_t irq, + int irqchip_phandle) +{ + g_autofree char *name =3D g_strdup_printf("/soc/i2c@%" PRIx64, mem->ba= se); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", "snps,designware-i2c"= ); + qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->s= ize); + qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle); + qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4); + qemu_fdt_setprop_cell(fdt, name, "#address-cells", 1); + qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); +} + static void finalize_fdt(TTAtlantisState *s) { uint32_t aplic_s_phandle =3D next_phandle(); @@ -505,6 +524,13 @@ static void finalize_fdt(TTAtlantisState *s) =20 create_fdt_uart(fdt, &s->memmap[TT_ATL_UART0], TT_ATL_UART0_IRQ, aplic_s_phandle); + + for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { + create_fdt_i2c(fdt, + &s->memmap[TT_ATL_I2C0 + i], + TT_ATL_I2C0_IRQ + i, + aplic_s_phandle); + } } =20 static void create_fdt(TTAtlantisState *s) @@ -813,6 +839,19 @@ static void tt_atlantis_machine_init(MachineState *mac= hine) qdev_get_gpio_in(s->irqchip, TT_ATL_UART0_IRQ), 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 + /* I2C */ + for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { + object_initialize_child(OBJECT(s), "i2c[*]", &s->i2c[i], + TYPE_DESIGNWARE_I2C); + sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_fatal); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); + memory_region_add_subregion(system_memory, + s->memmap[TT_ATL_I2C0 + i].base, + sysbus_mmio_get_region(sbd, 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, + qdev_get_gpio_in(s->irqchip, TT_ATL_I2C0_IRQ + = i)); + } + /* Load or create device tree */ if (machine->dtb) { machine->fdt =3D load_device_tree(machine->dtb, &s->fdt_size); diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 5317eccd06e7..ee876557ef15 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -137,6 +137,7 @@ config TENSTORRENT select RISCV_IMSIC select FW_CFG_DMA select PLATFORM_BUS + select DESIGNWARE_I2C =20 config XIANGSHAN_KUNMINGHU bool --=20 2.47.3 From nobody Mon Feb 9 16:35:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([45.124.203.15]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c4cb5352268sm20702659a12.0.2026.01.13.20.35.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jan 2026 20:35:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768365330; x=1768970130; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to; bh=A9olK44AYgWu2ZXXXtInH5+BcooZTljrg2yaMIZdD0E=; b=CpLQqK5tPB9QLpaFrBkX2Od3l7D4FnKAA6WeoWQoAnUYRvGOexcv7rpVbQHT/ZFyHP JP8yNCHOBqsf03DuHdVufPZShHfCKUvddN5e4JzTXtnsu8dHiwUJvHAXUebQSvwIBlKf K3QZ00ScEIREgQ8gdKqCsQMdMCP03SwlUW7trrIWLVUVt6ST0KAfyfevqnOdn0iFlaYb WLqJHSVF3mmsctNqAwQztqcksKKLqqOrojXejgv35Ge2jwUVXDoo6h7T20Qlz+W91RIO sH4o2bwqMWdZxorhOcukwIEojIsNCPDwN8/h5HdALyMbv5lg9WYjLXSAL7M2NpMsZzNj 9P1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768365330; x=1768970130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=A9olK44AYgWu2ZXXXtInH5+BcooZTljrg2yaMIZdD0E=; b=bBVar0VTh0piptJjiVUYqEoH6XC2AiEIKYBdCDQu1zF4ifRxOU357M/uhzETTlfnC1 FlG/4iFy2hN+xed2FNyf0KmbmpKPXNXdkbXw7VB0vlEfBCECeSYHfmi9RBHCwgJN/4c+ bhasfWfyFKwgXc9bUqhQ6dvuoivdMDVFMFxLh2fBUUU06t9QisZTEHc6rLn+a3PEFksn PEh0bifolM9PuRMa2wGWwI6vuZC5TDgGKXArX1dKn/dRT2aAIuWSfwpOcHlaHiUnA0SB V8nGpZRN6IW4n4ezr7IXcgeenE2/75Nxz5XiRqb+YlE0/gw4t5mgiy+MQw/TofuJzQyj NTYw== X-Forwarded-Encrypted: i=1; AJvYcCWVS9b+kzg5P1Q8slKMi3m0/58SwaDPIQ29M06e6PeBghNQnY1laKpoWVb4cBcq4BeAS7Pg6iL8/km6@nongnu.org X-Gm-Message-State: AOJu0YxKWDbGyyjj4hK0bruFZUd3oD6lrXHODFHaMWFiYHyeVjxhNs8F EvaI/8KGC0z65bhtoHxfDHg2v2w2dK4oiTSSR6T782fBXeS1tasrVGIu X-Gm-Gg: AY/fxX4A9utJlK4MPcUdrwo+5OklOLt2LaRH18VXsHMLRmMa+GW0tU+bWthfz4NZSCr 5gAkGIYGyv1V/2kfvhntVigN5KisQQZEppuhWo93haaxWN+NxcE6Ae92IyMnumj7ywoaOO39HKa y6LGgkuOF7NOnHjEzMCgZWupq/a8Vt380CEIXOs9JLU2MNMhSEFsBT7wUUZJEc6dyTKtOwaMsMX nreG2W+BGxJ5Pe8SDRdNWy4opjdFZN3ptJz0Q5uPo5KGscGVE+R3HLvMpHa73eBRrUpYZO3xHPQ v+S+9cyukRxn7xtAmEsJ08HQTbCuhMp6THH/dijdC327bL6iO4Yu/gRvRrouxCUBBrgyH2QdxMc I0Lbe2jdhVB75mOiaL5x5mrJ6qqDZkNOgQRawgDRD//idD+PmIpZAFHNRJazdhLGuj/JF4jTtqy Oro+wo8yqY2mte0c/I6fEK X-Received: by 2002:a05:6a20:729b:b0:361:2d0c:fd81 with SMTP id adf61e73a8af0-38befaf6a41mr1207832637.28.1768365329916; Tue, 13 Jan 2026 20:35:29 -0800 (PST) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza , Sunil V L , qemu-devel@nongnu.org Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Weiwei Li , Liu Zhiwei , Michael Ellerman , Joel Stanley , Nick Piggin , Anirudh Srinivasan , qemu-riscv@nongnu.org Subject: [PATCH v2 5/6] hw/riscv/atlantis: Add some i2c peripherals Date: Wed, 14 Jan 2026 15:04:27 +1030 Message-ID: <20260114043433.1056021-6-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260114043433.1056021-1-joel@jms.id.au> References: <20260114043433.1056021-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=joel.stan@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1768365414126158500 Content-Type: text/plain; charset="utf-8" Add an I2C RTC device and a temperature sensor. These are not present on the board but help for testing. Signed-off-by: Joel Stanley --- hw/riscv/tt_atlantis.c | 18 ++++++++++++++++++ hw/riscv/Kconfig | 2 ++ 2 files changed, 20 insertions(+) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 2d0add278c20..2e96c5954268 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -497,6 +497,19 @@ static void create_fdt_i2c(void *fdt, const MemMapEntr= y *mem, uint32_t irq, qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); } =20 +static void create_fdt_i2c_device(TTAtlantisState *s, int bus, + const char *compat, int addr) +{ + void *fdt =3D MACHINE(s)->fdt; + hwaddr base =3D s->memmap[TT_ATL_I2C0 + bus].base; + g_autofree char *name =3D g_strdup_printf("/soc/i2c@%"PRIx64"/sensor@%= d", + base, addr); + + qemu_fdt_add_subnode(fdt, name); + qemu_fdt_setprop_string(fdt, name, "compatible", compat); + qemu_fdt_setprop_cell(fdt, name, "reg", addr); +} + static void finalize_fdt(TTAtlantisState *s) { uint32_t aplic_s_phandle =3D next_phandle(); @@ -531,6 +544,9 @@ static void finalize_fdt(TTAtlantisState *s) TT_ATL_I2C0_IRQ + i, aplic_s_phandle); } + + create_fdt_i2c_device(s, 0, "national,lm75", 0x48); + create_fdt_i2c_device(s, 0, "dallas,ds1338", 0x6f); } =20 static void create_fdt(TTAtlantisState *s) @@ -851,6 +867,8 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, qdev_get_gpio_in(s->irqchip, TT_ATL_I2C0_IRQ + = i)); } + i2c_slave_create_simple(s->i2c[0].bus, "ds1338", 0x6f); + i2c_slave_create_simple(s->i2c[0].bus, "tmp105", 0x48); =20 /* Load or create device tree */ if (machine->dtb) { diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index ee876557ef15..0367d25d48da 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -138,6 +138,8 @@ config TENSTORRENT select FW_CFG_DMA select PLATFORM_BUS select DESIGNWARE_I2C + select DS1338 + select TMP105 =20 config XIANGSHAN_KUNMINGHU bool --=20 2.47.3 From nobody Mon Feb 9 16:35:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1768365397446791.6571267503783; Tue, 13 Jan 2026 20:36:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vfsbb-0006B9-2V; Tue, 13 Jan 2026 23:35:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vfsbZ-0006Aq-J8 for qemu-devel@nongnu.org; Tue, 13 Jan 2026 23:35:37 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vfsbY-0008LI-94 for qemu-devel@nongnu.org; Tue, 13 Jan 2026 23:35:37 -0500 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-81e9d0cd082so3684931b3a.0 for ; Tue, 13 Jan 2026 20:35:35 -0800 (PST) Received: from donnager-debian.. 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Signed-off-by: Nicholas Piggin Signed-off-by: Joel Stanley --- hw/riscv/tt_atlantis.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 2e96c5954268..cec17e7cb952 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -745,15 +745,15 @@ static void tt_atlantis_machine_done(Notifier *notifi= er, void *data) firmware_name, &start_addr, NULL); =20 + kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, + firmware_end_addr); if (machine->kernel_filename) { - kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, - firmware_end_addr= ); riscv_load_kernel(machine, &boot_info, kernel_start_addr, true, NULL); - kernel_entry =3D boot_info.image_low_addr; } else { - kernel_entry =3D 0; + riscv_setup_halting_payload(machine, &boot_info, kernel_start_addr= ); } + kernel_entry =3D boot_info.image_low_addr; =20 fdt_load_addr =3D riscv_compute_fdt_addr(s->memmap[TT_ATL_DDR_LO].base, s->memmap[TT_ATL_DDR_LO].size, --=20 2.47.3